JPH0738043A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize suppression of power supply noise by using a lead frame of a single-layer structure. CONSTITUTION:A semiconductor device 50 has a lead frame 51 of a single-layer structure, a semiconductor element 52 and a resin package 53. The lead frame 51 has a lead 54 for grounding and a lead 55 for power supply. The lead 54 for grounding and the lead 55 for power supply are exposed on the lower side of the resin package 52. A pad 65 for grounding of the semiconductor element 52 is connected to the lead 54 for grounding by a wire 60, while a pad 66 for power supply is connected to the lead 55 for power supply by a wire 61.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a power supply noise countermeasure.

In recent years, for example, semiconductor elements for ASIC are
There is a trend toward higher integration and faster operation.

When the semiconductor element is highly integrated, the number of terminals in the semiconductor device incorporating the semiconductor element increases, and the number of terminals increases, for example.
The number exceeds 00.

As the number of terminals increases, the size of the semiconductor device increases, and the lead length and wire length increase.
The lead and wire inductance increases.

Under such circumstances, if the operation speed of the semiconductor device is increased, the impedance of the leads and the wires is increased, and as a result, the power supply noise is increased, and the risk of the semiconductor device malfunctioning due to the power supply noise is increased. Problem is coming.

Therefore, in the semiconductor device, it is necessary to suppress the inductance of the line from the start end of the power supply lead to the end end of the ground lead as much as possible.

From the viewpoint of the manufacturing cost of the semiconductor device, it is desirable that the suppression of inductance can be realized at the lowest possible price.

[0008]

2. Description of the Related Art FIG. 16 shows a semiconductor device 10 disclosed in Japanese Patent Laid-Open No. 4-25163.

The semiconductor device 10 comprises a semiconductor element 11, a multilayer lead frame assembly 12, and a resin package 13.

The multi-layer lead frame assembly 12 includes a lead frame 14, a frame-shaped power plane 15 and a plate-shaped ground plane 1 which are separate members from the lead frame 14.
It is a structure formed by stacking six.

The lead frame 14 is a resin package 1.
3 has many leads protruding outward from the side surface. In addition to the signal lead 17, this lead has a power supply lead 18 and a ground lead 19.

The ground lead 19 is welded to the ground plane 16.

The power supply lead 18 is welded to the power supply plane 15.

The semiconductor element 11 includes a ground plane 16
It is mounted on top.

Ground pad 20 on semiconductor element 11
A wire 21 is provided between the ground plane 16 and the ground plane 16.

A wire 23 is provided between the power supply pad 22 on the semiconductor element 11 and the power supply plane 15.

A wire 25 is provided between the signal pad 24 and the signal lead 17 on the semiconductor element 11.

In the semiconductor device 10 having the above structure, the circuit board 29 is obtained by soldering the signal lead 17 to the signal pad 26, the power supply lead 18 to the power supply pad 27, and the ground lead 19 to the ground pad 28, respectively. It is mounted on top.

Ground pad 20 on semiconductor element 11
And the power supply pad 22 is connected to a place immediately near the semiconductor element 11, and the length of the wires 21 and 23 is larger than that in the case where the pad is connected to a lead having the same configuration as the signal lead. It is considerably shorter.

As a result, the inductance components of the ground and the power supply are reduced.

Generation of power supply noise is suppressed by reducing the inductance component.

[0022]

As can be seen from FIG. 16, the lengths of the wires 21 and 23 are shorter than that of the wire 25, and the inductance components of the wires 21 and 23 are suppressed to be small. However, the ground plane 16
Goes to the ground pad 28 after passing through the ground lead 19, and the power supply plane 15 reaches the power supply pad 27 after passing through the power supply lead 18. The inductance component in the part of the power supply lead 18 still exists.

For this reason, it is difficult to sufficiently reduce the inductive component of the power supply and the ground, and it cannot be said that the power supply noise countermeasure is sufficient.

The multilayer lead frame assembly is shown in FIG.
It is manufactured through the steps shown in FIG.

As can be seen from the figure, the manufacturing process has eight steps 40 to 47, which is considerably more complicated than the manufacturing process of a single-layer lead frame. The cost is considerably higher than that of a single-layer lead frame.

Therefore, the semiconductor device 10 becomes considerably expensive as compared with a general semiconductor device.

Therefore, it is an object of the present invention to provide a semiconductor device which realizes two items, that is, a manufacturing cost is reduced and a power supply noise suppressing effect is improved, by a structure using a single-layered lead frame. And

[0028]

According to a first aspect of the present invention, there is provided a ground lead located in the center, having a size for mounting a semiconductor element, and also serving as a stage, and located near the ground lead. A lead frame having a single layer structure having a power supply lead and signal leads arranged substantially in a radial pattern; and a semiconductor element mounted on the ground lead,
In the state in which the wire between the semiconductor element and the ground lead, the power supply lead and the signal lead, and the ground lead and the power supply lead are exposed on the lower surface,
The lead frame, the semiconductor element, and the resin package for encapsulating the wire, and the ground lead and the power lead forming part of the single-layer lead frame are exposed on the lower surface. .

According to a second aspect of the present invention, there is provided a ground lead which is located at the center, has a size for mounting a semiconductor element, and also serves as a stage, and is electrically insulated from the ground lead. A frame-shaped power supply lead surrounding the ground lead, and a substantially radial arrangement on a portion outside the power supply lead in a state of being electrically insulated from the ground lead and the power supply lead. And a semiconductor element mounted on the ground lead, the lead frame having a single-layer structure having a signal lead formed on the ground lead and an insulating adhesive tape supporting the ground lead to the power lead. The wire between the ground lead, the power supply lead and the signal lead and the ground lead and the power supply lead exposed on the lower surface. Arm, semiconductor devices, and more becomes a resin package for sealing the wire, the single layer structure lead part above ground leads and the power lead forming a frame, in which a structure exposed to the lower surface.

According to a third aspect of the present invention, in the first or second aspect, solder bumps are attached to the surfaces of the ground lead and the power lead exposed on the lower surface of the resin package.

According to a fourth aspect of the present invention, in the first or second aspect, the ground lead and the power source lead each have a plurality of electrically insulated portions.

[0032]

According to the present invention, the ground lead and the power supply lead forming part of the single-layered lead frame are exposed on the lower surface of the resin package. Acts to allow it to be directly connected to the circuit board without intervention.

The configuration in which the ground lead and the power supply lead are formed by a part of the lead frame having a single-layer structure operates so that a member different from the lead frame is not required as the ground lead and the power supply lead.

The solder bump attached to the lower surface of claim 3 is
When the semiconductor device is mounted on the circuit board, it serves to ensure that the ground lead and the power supply lead are electrically connected to the pads on the circuit board.

The plurality of insulated parts of claim 4 act so as to function as a supply path of another power source having a different voltage value.

[0036]

1 to 4 show a semiconductor device 50 according to a first embodiment of the present invention.

The semiconductor device 50 is a QFP type package, and generally has a single-layer structure lead frame 51, a semiconductor element 52, and a resin package 53.

As shown in FIG. 4, the single-layer lead frame 51 is composed of one ground lead 54, one power supply lead 55, many signal leads 56, and a support bar 57. .

The ground lead 54 is located at the center and also serves as a stage, and has a rectangular plate shape having a size several times larger than the size of the semiconductor element 52 on the plane.

The power supply lead 55 has a rectangular frame shape,
It surrounds the ground lead 54 and is located closer to the ground lead 55 than the signal lead 56.

The signal leads 56 are arranged radially outside the power supply leads 55.

The ground lead 54 is electrically insulated from the power supply lead 55 and the signal lead 56 by the support bar cutting portion 58.

Although the power supply leads 55 are supported at their corners by the support bars 57, the support bars 57 are electrically insulated from the signal leads 56, so that the signal leads 56 are supported. Electrically isolated.

The signal leads 56 are electrically insulated from each other.

The ground lead 54, the power supply lead 55, the signal lead 56 and the support bar 57 are mechanically connected by a polyimide adhesive tape 59 having a predetermined shape shown in FIG.

The adhesive tape 59 is used for the central semiconductor element 52.
A rectangular portion 59a having a size corresponding to, four rectangular frame portions 59b protruding from each corner of the rectangular portion 59a,
It is composed of four arm portions 59c that extend radially outward from each rectangular frame portion 59a and a large rectangular frame portion 59d that connects the ends of the arm portions 50c to each other.

In particular, as shown in FIG. 4, a rectangular portion 59a is attached to the center of the ground lead 54.

The rectangular frame portion 59b has the ground lead 5
4 and the power supply lead 55 are attached to each other, and the ground lead 54 and the power supply lead 55 are connected to each other.

The arm 59c is attached to the upper surface of the support bar 57.

The large rectangular frame portion 55d has a signal lead 56.
The signal leads 56 are attached to each other, and the adjacent signal leads 56 are connected to each other to limit the deformation of the tips of the signal leads 56.

As will be described later, the lead frame 51 having the above structure is manufactured through the same steps as a general lead frame and is inexpensive.

Even if the adhesive tape 59 is adhered, a part of the upper surface of the ground lead 54 and the power supply lead 55 is
It is not covered with the adhesive tape 59 and is exposed.

Reference numeral 54a is an exposed upper surface portion of the ground lead 54.

55a is an exposed upper surface portion of the power supply lead 55.

Further, of the support bar code 57, the portion indicated by reference numeral 57a is bent, and the ground lead 54 and the power supply lead 55 are the signal leads 56.
It is located lower than the tip of.

The semiconductor element 52 has a ground lead 54.
It is mounted on the rectangular portion 59a of the adhesive tape 59 at a central position thereof by bonding.

Reference numerals 60, 61 and 62 are wires bonded by wire bonding. Reference numeral 60 is a ground wire, 61 is a power supply wire, and 62 is a signal wire.

Of the many pads on the semiconductor element 52,
The ground pad 65 is connected to the ground lead 54 in the immediate vicinity of the semiconductor element 52 by the ground wire 60.

The power supply pad 66 is connected to the power supply lead 55 located closer to the semiconductor element 52 than the signal lead 56 by the power supply wire 61.

The signal pad 67 is connected to the inner lead 56a of the signal lead 56 by the signal wire 62. The inner leads 56a are silver-plated.

Here, the length of the ground wire 60 is set to l
_g , the length of the power supply wire 61 is l _p , and the signal wire 62
_Let l _{s be} the length of these, then l _g <l _s , l _p <
There is a relationship of l _s and l _g <l _p <l _s .

The resin package 53 seals the semiconductor element 52, the wires 60, 61 and 62, the adhesive tape 59, and the inner lead 56a of the signal lead 56 with resin.

Outer lead 56b of signal lead 56
Is projected from the side surface 53a of the resin package 53 and is shaped.

Ground lead 54 and power supply lead 5
5 is a resin package 53 as shown in FIGS.
Is exposed on the lower surface 53b.

The above is the structure of the semiconductor device 50.

The semiconductor device 50 is mounted on the circuit board 70 as shown in FIG.

The circuit board 70 has an upper surface on which the signal pads 7 are provided.
1, the ground pad 72 and the power pad 73
And a ground layer 74 and a power pad 73 which are internally connected to the ground pad 72 by a via hole.
And a power supply layer 75 connected to each other by a via hole.

In FIG. 5, 76 is solder.

In the semiconductor device 50, the signal lead 56 is soldered to the signal pad 73, the ground lead 54 of the lower surface 53a is soldered to the ground pad 72, and the power supply lead 55 of the lower surface 53a is also soldered. It is soldered to the power supply pad 73 and mounted on the circuit board 70.

As described above, since the ground lead 54 and the power supply lead 55 are directly connected to the ground pad 72 and the power supply pad 73, the ground lead 54 reaches the ground pad 72 of the circuit board 70. Inductance is equal to nothing in that part, and inductance is also equal in part from the power supply lead 55 to the power supply pad 73 of the circuit board 70.

Therefore, the semiconductor device 50 is mounted on the circuit board 70.
The inductance of the ground line in the state of being mounted on is the inductance of the ground wire 60 itself, and the inductance of the power line is mainly the inductance of the power wire 61 itself.

Here, the length l _g of the ground wire 60
And the length l _p of the power supply wire 61 are both short,
The inductance components of 0 and 61 are small.

Therefore, the inductance component of the power supply-ground of the semiconductor device 50 is the same as the semiconductor device 1 of FIG.
Since the inductance component of the power supply-ground of 0 is further suppressed, the semiconductor device 50 is less likely to generate power supply noise than the semiconductor device 10 of FIG. 16 even when operating at high speed.

Next, a method of manufacturing the single-layer structure lead frame 51, which is a main part of the semiconductor device 50, will be described.

As shown in FIGS. 6, 7, and 8, the single-layer structure lead frame 51 is manufactured through steps 80 to 84 similar to the manufacturing of a general lead frame.

Punching Step 80 A blank is punched by a press to obtain a lead frame 90 having a pattern shown in FIG. 7 (A).

Ag Plating Step 81 In the lead frame 90, the tip of the ground lead 54, the power supply lead 55, the signal lead 56 and the support bar 57 are Ag-plated, and the Ag shown in FIG.
The plated lead frame 91 is obtained.

In FIG. 7B, the portion shown in satin is the Ag plated portion 82.

Sinking Step 82 The middle part of the support bar 57 is bent obliquely downward so that the ground lead 54 and the power supply lead 55 are sunk into the signal lead 56.

Reference numeral 57a is a bent portion of the support bar 57.

As a result, the Ag plated submerged lead frame 93 is obtained.

Tape attaching step 83 The polyimide adhesive tape 59 having the pattern shown in FIG.
It is attached to the lead frame 93.

As a result, the lead frame 94 with the Ag plating submerged tape attached thereto, as shown in FIG. 8A, is obtained.

Cutting Step 84 In FIG. 8A, the portions 96 and 97 surrounded by broken lines are cut off.

As a result, the ground lead 54 is separated from the power supply lead 56, and the signal lead 5 is
The tip of 6 is cut off. As a result, the single-layer structure lead frame 51 shown in FIG. 8B is obtained.

As described above, the single-layer structure lead frame 5
1 is manufactured through the same steps as those for manufacturing a general lead frame, and the manufacturing cost is considerably lower than that of the multi-layer reel and frame assembly 12 shown in FIG.

Next, a method of manufacturing the semiconductor device 50 shown in FIGS. 1 to 4 will be described.

The semiconductor device 50 is manufactured by the process 10 shown in FIG.
It is manufactured through 0 to 107.

Die Attaching 100 A semiconductor element 52 having a ground pad 65, a power supply pad 66, and a signal pad 67 in an arbitrary arrangement on the upper surface,
It is mounted on the rectangular portion 59a (see FIG. 8B) of the adhesive tape 59 stretched on the upper surface of the ground lead 54 with an adhesive paste.

Wire Bonding 101 As shown in FIGS. 3 and 4, a ground wire 60 is provided between the ground pad 65 and the ground lead 54.
The power supply wire 61 is placed between the power supply pad 66 and the power supply lead 55, and the signal wire 62 is placed between the signal pad 67 and the signal lead 56.

Resin Sealing 102 As shown in FIG. 11, the lead frame 51 (94) is
It is sandwiched between the lower mold 110 and the upper mold 111 so that the ground lead 54 and the signal lead 56 are in contact with the inner surface 113 of the recess 112 of the lower mold 110, and resin molding is performed to form the resin package 53. To form.

Resin curing 103 Resin curing treatment is performed.

Deflash 104 The exposed surface of the lower surface of the ground lead 54, the lower surface of the power supply lead 55 and the signal lead 56 is deflashed by an abrasive material.

Plating 105 The signal leads 56 protruding by the resin package 53 are solder-plated.

At this time, a jig is used to electrically connect the ground lead 54 and the lead frame 51,
The lower surface 54b (see FIG. 2) of the ground lead 54 exposed on the lower surface of the resin package 53 is plated.

Cutting 106 In FIG. 8B, many portions indicated by a line 114 are cut to separate the semiconductor device from the lead frame.

Shaping 107 Signal lead 5 protruding from the resin package 53
6 is shaped to form the outer lead 56b.

The semiconductor device 50 is completed as described above.

12 and 13 show a semiconductor device 120 according to the second embodiment of the present invention.

In each figure, the same reference numerals are given to the parts corresponding to those shown in FIGS. 3 and 2.

The semiconductor device 120 includes the ground lead 5
Solder bumps 121 are attached to the lower surface 54b of No. 4, and the solder bumps 121 are also attached to the lower surface 55b of the power supply lead 55.
Is attached.

According to the semiconductor device 120 of this embodiment, the presence of the solder bumps 121 ensures that the ground lead 54 and the power supply lead 55, when mounted on the circuit board, are consistent with the pads on the circuit board. It is electrically conducted.

14 and 15 show a semiconductor device 130 according to the third embodiment of the present invention.

In each drawing, the same reference numerals are given to the portions corresponding to the constituent portions shown in FIGS. 2 and 3.

The semiconductor device 130 has a structure in which the semiconductor element has two voltages for operating it, for example, 3.5V and 5V.

The semiconductor device 130 has two power leads 55A and 55B which are electrically insulated, and the ground leads 54A and 5 which are electrically insulated.
4B.

For example, 3.5V is applied to the power supply lead 55A, and 5V is applied to another power supply lead 55B.

[0108]

As described above, according to the first aspect of the present invention, the inductance components of the power supply line and the ground line can be further suppressed as compared with the structure using the multilayer lead frame. Therefore, the generation of power supply noise can be effectively prevented.

Further, according to the invention of claim 1, since the lead frame having the single-layer structure is used, the manufacturing cost can be reduced as compared with the structure using the lead frame having the multi-layer structure.

According to the invention of claim 2, it has the same effect as that of the invention of claim 1.

According to the third aspect of the present invention, when mounted, the ground lead and the power supply lead can be reliably electrically connected to the corresponding pads on the circuit board. It may be ensured that the leads and the leads for the power supply perform the intended function.

According to the fourth aspect of the invention, when the semiconductor element has a plurality of operating voltages, it is possible to effectively prevent the generation of power supply noise for each operating voltage.

[Brief description of drawings]

FIG. 1 is a partially cutaway perspective view of an embodiment of a semiconductor device of the present invention.

FIG. 2 is a perspective view of the semiconductor device of FIG. 1 seen from the lower surface side.

3 is a cross-sectional view of the semiconductor device of FIG.

FIG. 4 is a plan view of the semiconductor device of FIG. 1 in which a resin package is omitted.

5 is a diagram showing a mounted state of the semiconductor device of FIG.

FIG. 6 is a manufacturing process diagram of the single-layer structure lead frame in FIGS. 1 to 5;

FIG. 7 is a diagram illustrating the manufacture of a single-layer structure lead frame.

FIG. 8 is a diagram illustrating the manufacture of a single-layer structure lead frame.

FIG. 9 is a diagram showing an adhesive tape.

FIG. 10 is a manufacturing process diagram of the semiconductor device in FIGS. 1 to 4;

11 is a diagram illustrating a resin sealing step in FIG.

FIG. 12 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

13 is a perspective view of the semiconductor device of FIG. 12 viewed from the lower surface side.

FIG. 14 is a perspective view of a semiconductor device according to a third embodiment of the present invention as seen from the lower surface side.

15 is a cross-sectional view of the semiconductor device of FIG.

FIG. 16 is a diagram showing an example of a conventional semiconductor device.

FIG. 17 is a process drawing showing the method of manufacturing the multilayer lead frame assembly in FIG. 16.

[Explanation of symbols]

50, 120, 130 Semiconductor device 51 Single layer structure lead frame 52 Semiconductor element 53 Resin package 53a Side surface 53b Lower surface 54, 54A, 54B Ground lead 54a Exposed upper surface portion 54b Lower surface 55, 55A, 55B Power supply lead 55a Exposed upper surface portion 55b Lower surface 56 Signal lead 56a Inner lead 56b Outer lead 57 Support bar 57a Bent part 58 Support bar cut part 59 Polyimide adhesive tape 59a Rectangular part 59b Rectangular frame part 59c Arm part 59d Large rectangular frame part 60 Ground wire 61 Power supply Wire 62 Signal wire 65 Ground pad 66 Power supply pad 67 Signal pad 70 Circuit board 71 Signal pad 72 Ground pad 73 Power supply pad 74 Ground layer 75 Power supply layer 76 Solder 0 lead frame 91 Ag plating lead frame 92 Ag plating portion 93 Ag plating sinking leadframe 94 Ag plating sinking tape applying leadframe 110 lower mold 111 the upper mold 112 recess 113 inner surface 114 cut line 121 solder bumps

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Rikuro Sono 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Junichi Kasai 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (4)

[Claims] 1. A ground lead (5) which is located at the center and has a size for mounting a semiconductor element and also serves as a stage.
4), a power supply lead (55) located in the vicinity of the ground lead, and a signal lead (56) arranged in a substantially radial pattern, the lead frame (51) having a single layer structure.
And a semiconductor element (52) mounted on the ground lead
And wires (60, 61, 60, 61, 61) between the semiconductor element and the ground lead, the power supply lead and the signal lead.
62) and a resin package (52) for encapsulating the lead frame, the semiconductor element, and the wire with the ground lead and the power supply lead exposed on the lower surface. A semiconductor device, wherein the grounding lead and the power supply lead forming a part are exposed on the lower surface (53b). 2. A ground lead (5) which is located at the center and has a size for mounting a semiconductor element and also serves as a stage.
4), and a frame-shaped power supply lead (55) surrounding the ground lead in a state of being electrically insulated from the ground lead, and the ground lead and the power supply lead electrically connected to each other. In a state of being electrically insulated, the signal leads (56) which are arranged substantially radially outside the power supply leads and the insulating adhesive tape (59) for supporting the ground leads with respect to the power supply leads. ), And a semiconductor element (52) mounted on the ground lead.
And wires (60, 61, 60, 61, 61) between the semiconductor element and the ground lead, the power supply lead and the signal lead.
62) and a resin package (53) for encapsulating the lead frame, the semiconductor element, and the wire with the ground lead and the power supply lead exposed on the lower surface. A semiconductor device, wherein the grounding lead and the power supply lead forming a part are exposed on the lower surface (53b). 3. The semiconductor device according to claim 1, wherein solder bumps (121) are attached to surfaces of the ground leads and the power leads exposed on the lower surface of the resin package. . 4. The structure according to claim 1 or 2, wherein the ground lead and the power lead have a plurality of electrically insulated portions (54A, 54B, 55A, 55B). Semiconductor device.