JPH0738031A - Manufacture of lead frame and lead frame - Google Patents
Manufacture of lead frame and lead frameInfo
- Publication number
- JPH0738031A JPH0738031A JP20094093A JP20094093A JPH0738031A JP H0738031 A JPH0738031 A JP H0738031A JP 20094093 A JP20094093 A JP 20094093A JP 20094093 A JP20094093 A JP 20094093A JP H0738031 A JPH0738031 A JP H0738031A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- inner lead
- lead frame
- signal
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
LOC(リードオンチップ)構造パッケージを提供する
半導体チップの上に設けられるリードフレーム及びその
製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a lead frame provided on a semiconductor chip which provides a LOC (lead on chip) structure package and a method of manufacturing the same.
【0002】[0002]
【従来の技術】図8〜10に一般的な樹脂封止型半導体
装置の構造例を示す。その構造を簡単に説明すると、半
導体装置は、モールド樹脂1に封止されたリードフレー
ム2と半導体チップ(素子)3を有し、リードフレーム
2は絶縁フィルム4を介して半導体チップ3の回路形成
面の上部に配置され、ボンディングワイヤ5により半導
体チップ3上の電極(ボンディングパッド)6と電気的
に接続される。2. Description of the Related Art FIGS. 8 to 10 show a structural example of a general resin-sealed semiconductor device. The structure will be briefly described. The semiconductor device has a lead frame 2 and a semiconductor chip (element) 3 which are encapsulated in a mold resin 1. The lead frame 2 forms a circuit of the semiconductor chip 3 via an insulating film 4. It is arranged on the upper side of the surface and is electrically connected to the electrode (bonding pad) 6 on the semiconductor chip 3 by the bonding wire 5.
【0003】リードフレーム2は、図11に示すよう
に、半導体チップ3の回路形成面の長手方向(紙面上で
上下方向)に沿って延びる中心線Yの近傍に配置される
共用インナーリード42と、半導体チップ3の回路形成
面上に位置する櫛形の信号インナーリード44と、これ
ら信号インナーリード44同士及び共用インナーリード
42を接続するタイバー46を備えている。このような
半導体装置や、共用インナーリードを備えたリードフレ
ームは、例えば特開昭61−241959号公報、特開
平2−244764号公報、同2−246125号公
報、同3−173464号公報、同3−204965号
公報等に開示されている。As shown in FIG. 11, the lead frame 2 includes a common inner lead 42 arranged near a center line Y extending along the longitudinal direction of the circuit formation surface of the semiconductor chip 3 (vertical direction on the paper surface). The semiconductor chip 3 is provided with comb-shaped signal inner leads 44 located on the circuit formation surface, and tie bars 46 connecting the signal inner leads 44 to each other and the common inner lead 42. Such a semiconductor device and a lead frame provided with a common inner lead are disclosed in, for example, JP-A-61-241959, JP-A-2-244647, JP-A-2-246125, JP-A-3-173464, and the like. It is disclosed in Japanese Patent Laid-Open No. 3-204965.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、上述し
たように信号インナーリード44の近傍に共用インナー
リード42を配置するリードフレーム2においては、図
12に示すように半導体チップ3上のボンディングパッ
ド6から信号インナーリード44へ共用インナーリード
42を飛び越えてワイヤボンディングを行おうとした場
合、ボンディングワイヤ5が共用インナーリード42に
接触してショートしてしまう恐れがある。尚、このショ
ートする可能性は、特に半導体装置全体の厚み(パッケ
ージ厚)が薄くなるにつれて大きくなる。However, in the lead frame 2 in which the common inner lead 42 is arranged near the signal inner lead 44 as described above, as shown in FIG. 12, the bonding pad 6 on the semiconductor chip 3 is removed. When attempting wire bonding by jumping over the common inner lead 42 to the signal inner lead 44, the bonding wire 5 may come into contact with the common inner lead 42 and cause a short circuit. The possibility of short-circuiting increases as the thickness of the entire semiconductor device (package thickness) decreases.
【0005】このような問題に対し、本願出願人は先
に、共用インナーリードをハーフエッチング処理によっ
て信号インナーリードよりも薄く形成し、以てボンディ
ングワイヤと共用インナーリードとの距離をとってショ
ート防止しようとした半導体装置を提案している。In order to solve such a problem, the applicant of the present invention first forms a common inner lead thinner than the signal inner lead by half-etching, thereby preventing a short circuit by keeping a distance between the bonding wire and the common inner lead. I am proposing a semiconductor device that I tried.
【0006】しかしながらこの方法は、リードフレーム
をエッチングによって製作する半導体装置に対してのみ
適用可能であって、エッチング法そのものがコスト高に
なる傾向にあり、生産性も良くない。However, this method can be applied only to a semiconductor device in which a lead frame is manufactured by etching, and the etching method itself tends to increase the cost and the productivity is not good.
【0007】また、ボンディングワイヤと接触する可能
性の高い共用インナーリード部分を、絶縁材料によって
コーティングする方法もあるが、これもエッチング法同
様、製造コストが高いという問題がある。There is also a method of coating the common inner lead portion, which is likely to come into contact with the bonding wire, with an insulating material, but this also has a problem that the manufacturing cost is high like the etching method.
【0008】本発明は、このような問題点に鑑み、コス
ト高となることなくワイヤボンディングの際のショート
の可能性を排除できるようなリードフレーム製造方法及
びリードフレームを提供することを目的とする。In view of the above problems, it is an object of the present invention to provide a lead frame manufacturing method and a lead frame which can eliminate the possibility of a short circuit during wire bonding without increasing the cost. .
【0009】[0009]
【課題を解決するための手段】上記目的を達成するため
本発明は、並列配置された複数の信号用インナーリード
と、信号用インナーリードの先端近傍で各信号用インナ
ーリードに対し略垂直方向に延びる共用インナーリード
とを有するリードフレームの製造方法であって、用意さ
れたリードフレーム用板材を圧延して、その表面に帯状
の凹部を有する所定厚さの板材を形成する成形工程と、
次いで、上記帯状凹部が共用インナーリードを成しかつ
凹部以外の部分が信号用インナーリードを成すように、
上記板材を所定のリードフレーム形状に打ち抜く切断工
程とを有する製造方法を提供する。In order to achieve the above object, the present invention is directed to a plurality of signal inner leads arranged in parallel, and in the vicinity of the tips of the signal inner leads in a direction substantially perpendicular to each signal inner lead. A method of manufacturing a lead frame having a shared inner lead extending, wherein a prepared lead frame plate material is rolled to form a plate material having a predetermined thickness having a band-shaped recess on the surface thereof,
Next, the band-shaped recess forms a common inner lead, and the part other than the recess forms a signal inner lead.
And a cutting step of punching the plate material into a predetermined lead frame shape.
【0010】また、好ましい実施例においては、この製
造方法の成形工程は、対向配置された1対の圧延ローラ
の間にリードフレーム用板材を挿入圧延することにより
なされ、上記圧延ローラの一方の外周面には、上記帯状
凹部を成形するための周状の突起が形成される。In a preferred embodiment, the forming step of this manufacturing method is performed by inserting and rolling a lead frame plate material between a pair of rolling rollers arranged opposite to each other, and the outer periphery of one of the rolling rollers. A circumferential projection is formed on the surface to mold the band-shaped recess.
【0011】更に、別の好ましい実施例では、上記製造
方法は更に、成形された板材表面の所定領域にメッキを
施すメッキ工程を有する。Further, in another preferred embodiment, the above-mentioned manufacturing method further includes a plating step for plating a predetermined area on the surface of the molded plate material.
【0012】また、本発明では、並列配置された複数の
信号用インナーリードと、これら信号用インナーリード
の先端近傍で各信号用インナーリードに対し略垂直方向
に延びる共用インナーリードと、共用インナーリードか
ら信号用インナーリードの各々の間に延びる複数の引き
出しリードとから成り、半導体チップの回路面上でボン
ディングワイヤを介し、共用インナーリード及び信号用
インナーリードと半導体チップとの間で電気的に接続さ
れるリードフレームにおいて、ボンディングワイヤに接
続される共用インナーリードの面は、ボンディングワイ
ヤに接続される信号用インナーリードの面よりも低く形
成されるリードフレームが提供される。Further, according to the present invention, a plurality of signal inner leads arranged in parallel, a common inner lead extending substantially perpendicularly to the respective signal inner leads near the tips of the signal inner leads, and a common inner lead. To a plurality of lead wires extending between each of the signal inner leads, and electrically connected between the common inner lead and the signal inner lead and the semiconductor chip via a bonding wire on the circuit surface of the semiconductor chip. In the above lead frame, the surface of the shared inner lead connected to the bonding wire is formed lower than the surface of the signal inner lead connected to the bonding wire.
【0013】また、本発明では上記リードフレームの好
ましい実施例として、共用インナーリードと信号用イン
ナーリードの厚さはほぼ等しく形成されるリードフレー
ムが提供される。In the present invention, as a preferred embodiment of the lead frame, there is provided a lead frame in which the common inner lead and the signal inner lead are formed to have substantially the same thickness.
【0014】更に、本発明によれば、半導体チップと、
半導体チップの回路面上に位置する複数のインナーリー
ドを備えるリードフレームと、リードフレームと半導体
チップとの間に介挿されて両者を接着する絶縁体と、リ
ードフレームのインナーリードと半導体チップとを電気
的に接続するボンディングワイヤと、これらの要素を封
入するモールド樹脂とを有する半導体装置が提供され、
ここでインナーリードは、並列配置された複数の信号用
インナーリードと、信号用インナーリードの先端近傍で
各信号用インナーリードに対し略垂直方向に延びる共用
インナーリードとを有すると共に、ボンディングワイヤ
に接続される共用インナーリードの面が、ボンディング
ワイヤに接続される信号用インナーリードの面よりも低
く形成される。Further, according to the present invention, a semiconductor chip,
A lead frame having a plurality of inner leads located on the circuit surface of the semiconductor chip; an insulator that is interposed between the lead frame and the semiconductor chip to bond the two; and an inner lead of the lead frame and the semiconductor chip. Provided is a semiconductor device having a bonding wire electrically connected and a mold resin encapsulating these elements,
Here, the inner lead has a plurality of signal inner leads arranged in parallel and a common inner lead extending substantially perpendicularly to each signal inner lead near the tip of the signal inner lead, and is connected to a bonding wire. The surface of the shared inner lead is formed lower than the surface of the signal inner lead connected to the bonding wire.
【0015】また、上記半導体装置の好ましい実施例と
して、上記共用インナーリードから上記信号用インナー
リードの隣り合うインナーリード間に延びる複数の引き
出しリードを有する半導体装置と、共用インナーリード
は信号用インナーリードよりも半導体チップの回路面に
接近する半導体装置が提供される。As a preferred embodiment of the semiconductor device, a semiconductor device having a plurality of lead-outs extending from the shared inner lead between adjacent inner leads of the signal inner lead, and the shared inner lead is a signal inner lead. A semiconductor device closer to the circuit surface of the semiconductor chip is provided.
【0016】[0016]
【作用】共用インナーリードのボンディングワイヤに接
続される面を、信号用インナーリードの面よりも低くす
ることで、信号用インナーリードから半導体チップの電
極へと延びるボンディングワイヤと共用インナーリード
との間隔を大きくすることができ、ボンディングワイヤ
と共用インナーリードとの接触を防止することができ
る。The distance between the bonding wire extending from the signal inner lead to the electrode of the semiconductor chip and the common inner lead is made by making the surface of the common inner lead connected to the bonding wire lower than the surface of the signal inner lead. Can be increased, and contact between the bonding wire and the shared inner lead can be prevented.
【0017】また本発明は、このリードフレームを提供
するにあたり、材料を所定厚の板材に圧延する過程にお
いて、将来、共用インナーリードになるであろうとする
板材部分に、予め板材の長手方向に帯状凹部を形成する
ため、1回の打ち抜き(切断)工程で、他の部分よりも
凹んだ共用インナーリードを形成することができ、エッ
チングなどによる形成法に比較して、簡単かつ低コスト
で所望のリードフレームを提供できる。Further, in providing the lead frame of the present invention, in the process of rolling the material into a plate material having a predetermined thickness, the plate material portion which will become the shared inner lead in the future is preliminarily striped in the longitudinal direction of the plate material. Since the recess is formed, the common inner lead that is recessed compared to the other portions can be formed in one punching (cutting) step, which is simpler and less costly than the forming method by etching or the like. Can provide lead frame.
【0018】[0018]
【実施例】図面を参照しながら本発明の実施例を以下、
説明する。Embodiments of the present invention will be described below with reference to the drawings.
explain.
【0019】図1は本発明による第1実施例としての半
導体装置の樹脂封止前の平面図であり、図2はそのII
−II線に沿った樹脂封止後の断面図である。これらの
図において、10はリードフレーム、12は共用インナ
ーリード、14は信号用インナーリード、16はインナ
ーリード12,14を共通に結合し、樹脂封止後切断除
去されるタイバー、18は共用インナーリード16から
隣り合う信号用インナーリード14間に引き出された引
き出しリード、20は絶縁フィルム、22は半導体チッ
プ、24はボンディングパッド、26,28は金(A
u)から成るボンディングワイヤ、30は封止用のモー
ルド樹脂である。FIG. 1 is a plan view of a semiconductor device as a first embodiment according to the present invention before resin encapsulation, and FIG. 2 is its II.
FIG. 6 is a cross-sectional view after resin sealing, taken along line II. In these figures, 10 is a lead frame, 12 is a common inner lead, 14 is a signal inner lead, 16 is a tie bar that is commonly joined to the inner leads 12 and 14 and is cut and removed after resin sealing, and 18 is a common inner. A lead-out lead drawn from the lead 16 between the adjacent signal inner leads 14, 20 is an insulating film, 22 is a semiconductor chip, 24 is a bonding pad, and 26 and 28 are gold (A
u) is a bonding wire, and 30 is a molding resin for sealing.
【0020】タイバー16によって結合された櫛形のイ
ンナーリード14は、半導体チップ22の回路形成面の
上に位置し、一方、共用インナーリード12は半導体チ
ップ22の中心線Yの近傍に配置される。また、絶縁フ
ィルム20は、信号用インナーリード14及び引き出し
リード18と、半導体チップ22との間で両者を接着し
ている。信号用インナーリード14及び共用インナーリ
ード12は、ボンディングワイヤ26,28により半導
体チップ22上の電極24に電気的に接続されている。
上述したこれらの構成要素は、総てモールド樹脂30に
よって封止され、全体としてLOC構造のパッケージが
形成される。The comb-shaped inner leads 14 joined by the tie bars 16 are located on the circuit forming surface of the semiconductor chip 22, while the shared inner leads 12 are arranged near the center line Y of the semiconductor chip 22. The insulating film 20 adheres the signal inner lead 14 and the lead lead 18 to the semiconductor chip 22. The signal inner lead 14 and the shared inner lead 12 are electrically connected to the electrodes 24 on the semiconductor chip 22 by bonding wires 26 and 28.
All of these components described above are encapsulated by the molding resin 30 to form a package of LOC structure as a whole.
【0021】以上のように構成される半導体装置におい
て本実施例によれば、図1に斜線で表した共用インナー
リード12は、後述するリードフレーム製造法によっ
て、図2に示すように信号用インナーリード14や引き
出しリード18より薄く形成され、半導体チップ22の
上面(回路面)22aから共用インナーリード12の上
面12aまでの高さhは、半導体チップ22上面から信
号用インナーリード14上面までの高さHよりも小さく
なるように形成される(H>h)。このように共用イン
ナーリード12を信号用インナーリード14よりも低く
することにより、電極24からのボンディングワイヤ2
6が、共用インナーリード12を飛び越えて信号用イン
ナーリード14に接続されるにあたって、ボンディング
ワイヤ26と共用インナーリード12とが接触する可能
性は低められ、ショート防止することができる。In the semiconductor device constructed as described above, according to the present embodiment, the common inner leads 12 shown by hatching in FIG. 1 are the inner leads for signal as shown in FIG. 2 by the lead frame manufacturing method described later. The height h from the upper surface (circuit surface) 22a of the semiconductor chip 22 to the upper surface 12a of the common inner lead 12 is formed to be thinner than the leads 14 and the extraction leads 18, and the height h from the upper surface of the semiconductor chip 22 to the upper surface of the signal inner lead 14 is high. It is formed so as to be smaller than H (H> h). By thus lowering the common inner lead 12 lower than the signal inner lead 14, the bonding wire 2 from the electrode 24 is formed.
When 6 is jumped over the common inner lead 12 and connected to the signal inner lead 14, the possibility that the bonding wire 26 and the common inner lead 12 contact each other is reduced, and a short circuit can be prevented.
【0022】図3及び図4は、第1実施例と同様に、共
用インナーリード上面12aを信号用インナーリード1
4や引き出しリード18の上面14a,18aよりも低
くし、半導体チップ回路面22aにより接近させた本発
明の第2実施例を示したものであって、図3はその樹脂
封止前の平面図、図4は図3のIV−IV線に沿う断面
図である。尚、この実施例で第1実施例と同様な構成要
素は同一番号を付すこととする。3 and 4, as in the first embodiment, the common inner lead upper surface 12a is provided with the signal inner lead 1a.
4 and the upper surfaces 14a and 18a of the lead leads 18 and showing the second embodiment of the present invention which is closer to the semiconductor chip circuit surface 22a. FIG. 3 is a plan view before resin sealing. 4 is a sectional view taken along the line IV-IV in FIG. Incidentally, in this embodiment, the same components as those in the first embodiment are designated by the same reference numerals.
【0023】上述したように、本実施例では共用インナ
ーリード12は、引き出しリード18よりも回路面22
aに接近するべく変形されており、第1実施例と異なり
共用インナーリード12は引き出しリード18や信号用
インナーリード14とほぼ同じ厚さを有して形成される
(図4参照)。As described above, in the present embodiment, the shared inner lead 12 is arranged on the circuit surface 22 rather than the extraction lead 18.
Unlike the first embodiment, the shared inner lead 12 is formed to have a thickness substantially the same as that of the lead-out lead 18 and the signal inner lead 14 (see FIG. 4).
【0024】このため、このようなリードフレームを装
着する半導体装置は、第1実施例よりも共用インナーリ
ード12自体の強度を向上することができ、外部からの
衝撃等に対し変形しにくいという利点がある。また、共
用インナーリード12と半導体チップ22との間隔cが
小さくなることにより、半導体チップの発熱部位となる
回路面22aからモールド樹脂30(図2)を介した共
用インナーリード12への熱伝達が高められ(熱抵抗の
低下)、リードフレーム10’を介した半導体装置の外
部放熱が向上する。Therefore, the semiconductor device equipped with such a lead frame can improve the strength of the shared inner lead 12 itself as compared with the first embodiment, and is less likely to be deformed by an external impact or the like. There is. Further, since the distance c between the common inner lead 12 and the semiconductor chip 22 is reduced, heat is transferred from the circuit surface 22a, which is a heat generating portion of the semiconductor chip, to the common inner lead 12 through the molding resin 30 (FIG. 2). It is increased (reduction of thermal resistance), and external heat radiation of the semiconductor device via the lead frame 10 ′ is improved.
【0025】尚、本実施例においても、第1実施例と同
様に、信号用インナーリード14や引き出しリード18
のボンディングワイヤ接着面(即ち、上面14a,18
a)よりも共用インナーリード12の接着面(上面12
a)が低くなるためショート防止効果がある。In this embodiment as well, as in the first embodiment, the signal inner leads 14 and the lead-out leads 18 are provided.
Bonding wire bonding surface (that is, the upper surfaces 14a, 18
Adhesive surface of the common inner lead 12 (upper surface 12)
Since a) becomes low, there is a short-circuit prevention effect.
【0026】上述したリードフレームの製造方法を、第
1実施例のリードフレームの製造法に例をとり、以下説
明する。The lead frame manufacturing method described above will be described below by taking the lead frame manufacturing method of the first embodiment as an example.
【0027】まず、リードフレーム用材料として、例え
ばFe−Ni系合金やCu系合金などの金属材料からな
る一片の板材Mが用意される。次に、この板材Mを図5
(a)に示すような一対のローラR,R’の間に挿入
し、所定厚さの板材M’に圧延成形する。この時、一方
のローラRの外周面には、その中央に図1の斜線部分の
幅Wにほぼ等しい長さ分の周状の突起pが形成されてお
り、このため、圧延後の板材M’には図5(b)に示す
ように、その中央に板材長手方向に沿って他の部分より
も板厚を小とする帯状凹部dが形成されることになる。
尚、第2実施例のリードフレーム10’を製造する場合
には、図示しないが、当然ながら一方のローラRに周状
突起pが、また他方のローラR’外周面にこの突起pに
対応する周状の凹部が形成されることになる。First, as a lead frame material, a piece of plate material M made of a metal material such as an Fe-Ni alloy or a Cu alloy is prepared. Next, this plate material M is shown in FIG.
It is inserted between a pair of rollers R and R'as shown in (a), and rolled into a plate material M'having a predetermined thickness. At this time, on the outer peripheral surface of one roller R, a circumferential protrusion p having a length substantially equal to the width W of the hatched portion in FIG. 1 is formed at the center thereof, and therefore, the rolled plate material M is rolled. As shown in FIG. 5 (b), a strip-shaped recess d having a smaller plate thickness than the other portions is formed in the center of the ′ along the plate material longitudinal direction.
In the case of manufacturing the lead frame 10 'of the second embodiment, although not shown, naturally, one roller R corresponds to the circumferential projection p, and the other roller R'outer peripheral surface corresponds to this projection p. A circumferential recess will be formed.
【0028】次に、このようにして圧延された板材M’
の所定領域に対してメッキ処理が施される。このメッキ
処理は、ボンディングワイヤに電気的接続されるリード
フレーム部分に対し、その接合を確実かつ容易ならしめ
るために行われるものであって、例えば、インナーリー
ド表面にAu(金),Ag(銀)などの金属を被覆する
ものである。Next, the plate material M'rolled in this way
Plating is applied to a predetermined area of the. This plating process is performed to securely and easily bond the lead frame portion electrically connected to the bonding wire. For example, Au (gold), Ag (silver) is formed on the inner lead surface. ) And other metals.
【0029】しかして、その具体的処理方法としては、
メッキ処理するにあたり予め圧延後の板材M’全域に電
荷を印加し、この状態のまま図6(a)に示すように、
離間配置されたマスキングローラNに板材M’を圧接し
て矢印方向に移動し、同時に各マスキングローラNに挟
まれた空間にメッキ液を充填補給する。この結果、直接
マスキングローラNに接触しない板材部分(図1のリー
ドフレームの場合、矢印Aで示した範囲)に対してのみ
メッキ液が浸り、板材M’の移動により図6(b)に示
すようなストライプメッキSが施されることになる。As a concrete processing method,
Before the plating process, electric charges are applied to the whole area of the rolled plate material M ′ in advance, and in this state, as shown in FIG.
The plate material M ′ is pressed against the masking rollers N arranged apart from each other and moved in the direction of the arrow, and at the same time, the space sandwiched between the masking rollers N is filled with the plating solution. As a result, the plating solution is immersed only in the plate material portion (in the case of the lead frame in FIG. 1, the area indicated by the arrow A in the case of the lead frame in FIG. 1) that does not come into direct contact with the masking roller N, and as shown in FIG. Such stripe plating S will be applied.
【0030】そして、以上のようにしてボンディングワ
イヤ接続部分にメッキ層が形成されたならば、次に板材
は図7(a)に示すような板材ロールUから巻き取りロ
ールVへと連続して送り出され、その途中においてプレ
ス機Pによって不要な部分を打ち抜かれる。この際、プ
レス機Pに装着される打ち抜きダイスDは、打ち抜きに
よって、前記帯状凹部dの部分に共用インナーリード1
2(図1)が形成され、かつ凹部以外の部分に信号用イ
ンナーリード14、タイバー16、引き出しリード18
が形成されるように所定形状に成形されており、打ち抜
きにあたっては連続して供給される板材に対して適正な
位置関係を以て配置される。そして、図7(b)に示す
ような所定形状のリードフレームを連続配置するストリ
ップLが得られた後は、適当な切断手段によって個々の
リードフレーム10へと切断され、リードフレーム製造
工程を終了する。After the plating layer is formed on the bonding wire connecting portion as described above, the plate material is continuously transferred from the plate material roll U to the winding roll V as shown in FIG. 7A. It is sent out, and an unnecessary portion is punched out by the press machine P in the middle thereof. At this time, the punching die D mounted on the pressing machine P is punched into the common inner lead 1 in the band-shaped recess d.
2 (FIG. 1) is formed, and the signal inner lead 14, the tie bar 16, and the extraction lead 18 are formed in the portion other than the concave portion.
Are formed into a predetermined shape so that the plate is formed, and when punching, they are arranged in an appropriate positional relationship with respect to the plate materials continuously supplied. Then, after a strip L in which lead frames having a predetermined shape are continuously arranged as shown in FIG. 7B is obtained, the lead frames are cut into individual lead frames 10 by an appropriate cutting means, and the lead frame manufacturing process is completed. To do.
【0031】尚、以上説明したリードフレーム製造方法
に関連し、凹部を形成する工程は、一般的な上下動タイ
プのプレス機によってなされるものでも良く、また打ち
抜き工程に関しても1回の打ち抜きによって、分離され
たリードフレームが排出されるようにしても良い。In connection with the lead frame manufacturing method described above, the step of forming the recess may be performed by a general vertical movement type press machine, and the punching step may be performed by one punching. The separated lead frame may be discharged.
【0032】このようにして得られたリードフレームか
ら、図8、図9に示すような半導体装置を製造するため
には、まず長方形に切り抜いた絶縁フィルム20(絶縁
材両面に、ガラス転移点が160℃程度の熱可塑性樹脂
からなる接着テープを張り付けたもの)をリードフレー
ム10の下に置き、上から5kg、200℃、1s程度
で加圧し、リードフレーム10に絶縁フィルム20を接
着する。In order to manufacture a semiconductor device as shown in FIGS. 8 and 9 from the lead frame thus obtained, first, an insulating film 20 cut into a rectangle (both sides of the insulating material have glass transition points An adhesive tape made of a thermoplastic resin at about 160 ° C.) is placed under the lead frame 10 and pressure is applied from above to 5 kg at 200 ° C. for about 1 s to bond the insulating film 20 to the lead frame 10.
【0033】次いで、このリードフレーム10を半導体
チップ22上に置き、その上から2Kg、260℃、1
s程度で加圧して、チップ22とリードフレーム10を
絶縁フィルム20を介して接着する。その後、仕様に応
じてチップ22上の所定電極24とリードフレーム10
の各インナーリード12,14を図1に示すようにワイ
ヤボンディングし、これをモールド樹脂30で封止した
後、適宜カッティングを行えば、LOC構造のパッケー
ジが提供されることになる。Next, the lead frame 10 is placed on the semiconductor chip 22, and 2 kg from above, 260 ° C., 1
Pressure is applied at about s to bond the chip 22 and the lead frame 10 with the insulating film 20 interposed therebetween. Then, according to the specifications, the predetermined electrodes 24 on the chip 22 and the lead frame 10
Each of the inner leads 12 and 14 is wire-bonded as shown in FIG. 1, sealed with the mold resin 30, and appropriately cut to provide a LOC structure package.
【0034】以上、本発明によるリードフレーム製造方
法、及びこの製造方法によって製造されるリードフレー
ムと半導体装置(パッケージ)を説明したが、リードフ
レームの形状は図示した実施例に限定されるものではな
い。また、説明したリードフレーム製造例では、圧延工
程と切断工程との間にメッキ工程を含んだものである
が、リードフレーム材料によってはこのメッキ工程を省
いても良い。Although the lead frame manufacturing method according to the present invention and the lead frame and the semiconductor device (package) manufactured by this manufacturing method have been described above, the shape of the lead frame is not limited to the illustrated embodiment. . Further, in the example of manufacturing the lead frame described above, the plating step is included between the rolling step and the cutting step, but this plating step may be omitted depending on the lead frame material.
【0035】[0035]
【発明の効果】以上説明したように、本発明に係るイン
ナーリードによれば、共用インナーリードのボンディン
グワイヤに接続される面を、信号用インナーリードの面
よりも低くするため、信号用インナーリードから半導体
チップの電極へと延びるボンディングワイヤと共用イン
ナーリードとの間隔を大きくすることができ、ボンディ
ングワイヤと共用インナーリードとの接触を防止するこ
とができる。As described above, according to the inner lead of the present invention, since the surface of the shared inner lead connected to the bonding wire is made lower than the surface of the signal inner lead, the signal inner lead is formed. It is possible to increase the distance between the bonding wire extending from the to the electrode of the semiconductor chip and the shared inner lead, and it is possible to prevent contact between the bonding wire and the shared inner lead.
【0036】また本発明に係るインナーリード製造方法
によれば、インナーリード用板材を所定厚の板材に圧延
する過程において、将来、共用インナーリードになるで
あろうとする板材部分に、予め板材の長手方向に帯状凹
部を形成するため、1回の打ち抜き(切断)工程で、他
の部分よりも凹んだ共用インナーリードを形成すること
ができ、エッチングなどによる形成法に比較して、簡単
かつ低コストで所望のリードフレームを提供できる。Further, according to the inner lead manufacturing method of the present invention, in the process of rolling the plate material for the inner lead into a plate material having a predetermined thickness, the plate material portion which will become the shared inner lead in the future is preliminarily lengthened. Since the band-shaped recess is formed in one direction, it is possible to form a common inner lead that is recessed more than other parts in a single punching (cutting) step, which is simpler and less costly than a forming method such as etching. Can provide a desired lead frame.
【図1】本発明の第1実施例としての半導体装置の樹脂
封止前の平面図である。FIG. 1 is a plan view of a semiconductor device as a first embodiment of the present invention before resin sealing.
【図2】図1のII−II線に沿った樹脂封止後の半導
体装置の断面図である。2 is a cross-sectional view of the semiconductor device after resin encapsulation taken along the line II-II in FIG.
【図3】本発明の第2実施例としての半導体装置の樹脂
封止前の平面図である。FIG. 3 is a plan view of a semiconductor device as a second embodiment of the present invention before resin sealing.
【図4】図3のIV−IV線に沿った半導体装置の断面
図である。FIG. 4 is a cross-sectional view of the semiconductor device taken along the line IV-IV of FIG.
【図5】本発明によるリードフレーム製造の際の板材圧
延工程を示し、(a)は圧延状態、(b)は圧延後の板
材をそれぞれ示した図である。5A and 5B are views showing a plate material rolling step in manufacturing the lead frame according to the present invention, in which FIG. 5A is a rolled state and FIG. 5B is a diagram showing the rolled plate material.
【図6】圧延工程に続くメッキ工程を示し、(a)はメ
ッキ処理状態、(b)はメッキ後の板材をそれぞれ示し
た図である。6A and 6B are views showing a plating process subsequent to the rolling process, FIG. 6A showing a plating treatment state, and FIG. 6B showing a plate material after plating.
【図7】メッキ工程に続く板材切断工程を示し、(a)
は切断状態、(b)は切断後の板材をそれぞれ示した図
である。FIG. 7 shows a plate material cutting step following the plating step, (a)
Is a cut state, (b) is a diagram showing the plate material after cutting.
【図8】従来の半導体装置の概略構成を示し、一部切り
抜き斜視図である。FIG. 8 is a partially cut-away perspective view showing a schematic configuration of a conventional semiconductor device.
【図9】図8の横断面図である。9 is a cross-sectional view of FIG.
【図10】図8に示す半導体装置の樹脂封止前の分解斜
視図である。10 is an exploded perspective view of the semiconductor device shown in FIG. 8 before resin sealing.
【図11】従来の半導体装置構成に係る問題点を説明す
るものであって、樹脂封止前の半導体装置の部分的平面
図である。FIG. 11 is a partial plan view of the semiconductor device before resin encapsulation, for explaining the problems relating to the conventional semiconductor device configuration.
【図12】図11のXII−XII線に沿う樹脂封止後
の断面図である。12 is a sectional view taken along line XII-XII of FIG. 11 after resin sealing.
10…リードフレーム 12…共用インナーリード 14…信号用インナーリード 16…タイバー 18…引き出しリード 20…絶縁フィルム 22…半導体チップ 24…電極 26…ボンディングワイヤ 30…モールド樹脂 d…帯状凹部 M,M’…リードフレーム用板材 P…プレス機 p…周状突起 R,R’…圧延ローラ 10 ... Lead frame 12 ... Common inner lead 14 ... Signal inner lead 16 ... Tie bar 18 ... Extraction lead 20 ... Insulating film 22 ... Semiconductor chip 24 ... Electrode 26 ... Bonding wire 30 ... Mold resin d ... Strip-shaped recess M, M '... Plate material for lead frame P ... Press machine p ... Circular protrusions R, R '... Rolling roller
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成5年9月21日[Submission date] September 21, 1993
【手続補正1】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】請求項1[Name of item to be corrected] Claim 1
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【手続補正2】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】0009[Correction target item name] 0009
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【0009】[0009]
【課題を解決するための手段】上記目的を達成するため
本発明は、並列配置された複数の信号用インナーリード
と、信号用インナーリードの先端近傍で各信号用インナ
ーリードに対し略垂直方向に延びる共用インナーリード
とを有するリードフレームの製造方法であって、用意さ
れたリードフレーム用板材を圧延もしくはエッチングに
より、その表面に帯状の凹部を有する所定厚さの板材を
形成する成形工程と、次いで、上記帯状凹部が共用イン
ナーリードを成しかつ凹部以外の部分が信号用インナー
リードを成すように、上記板材を所定のリードフレーム
形状に打ち抜く切断工程とを有する製造方法を提供す
る。In order to achieve the above object, the present invention is directed to a plurality of signal inner leads arranged in parallel, and in the vicinity of the tips of the signal inner leads in a direction substantially perpendicular to each signal inner lead. A method of manufacturing a lead frame having a shared inner lead extending, wherein a prepared lead frame plate material is rolled or etched.
More, a forming step of forming a plate material of a predetermined thickness having a strip-shaped recess on its surface, then, as the strip recess portions other than forms and recess shared inner lead forms a signal inner leads, the And a cutting step of punching a plate material into a predetermined lead frame shape.
Claims (9)
ードと、該信号用インナーリードの先端近傍で各信号用
インナーリードに対し略垂直方向に延びる共用インナー
リードとを有するリードフレームの製造方法であって、 用意されたリードフレーム用板材を圧延して、その表面
に帯状の凹部を有する所定厚さの板材を形成する成形工
程と、 次いで、上記帯状凹部が共用インナーリードを成しかつ
凹部以外の部分が信号用インナーリードを成すように、
上記板材を所定のリードフレーム形状に打ち抜く切断工
程とを有することを特徴とするリードフレーム製造方
法。1. A method of manufacturing a lead frame having a plurality of signal inner leads arranged in parallel, and a common inner lead extending in a direction substantially perpendicular to the signal inner leads near the tips of the signal inner leads. There is a forming step of rolling the prepared lead frame plate material to form a plate material having a predetermined thickness having a band-shaped recess on the surface thereof, and then, the band-shaped recess forms a shared inner lead and other than the recess. So that the part of is the inner lead for signal,
And a cutting step of punching the plate material into a predetermined lead frame shape.
圧延ローラによる圧延加工であり、上記圧延ローラの一
方の外周面には、上記帯状凹部を成形する周状の突起が
形成されている請求項1に記載のリードフレーム製造方
法。2. The forming step is a rolling process using a pair of rolling rollers arranged opposite to each other, and a circumferential projection for forming the band-shaped recess is formed on one outer peripheral surface of the rolling roller. The method of manufacturing a lead frame according to claim 1.
メッキを施すメッキ工程を有する請求項1又は2に記載
のリードフレーム製造方法。3. The lead frame manufacturing method according to claim 1, further comprising a plating step of plating a predetermined region on the surface of the molded plate material.
ードと、該信号用インナーリードの先端近傍で各信号用
インナーリードに対し略垂直方向に延びる共用インナー
リードとから成り、半導体チップの回路面上でボンディ
ングワイヤを介し、共用インナーリード及び信号用イン
ナーリードと半導体チップとの間で電気的に接続される
ためのリードフレームであって、 上記ボンディングワイヤに接続される共用インナーリー
ドの面は、ボンディングワイヤに接続される信号用イン
ナーリードの面よりも低く形成されることを特徴とする
リードフレーム。4. A circuit surface of a semiconductor chip, comprising a plurality of signal inner leads arranged in parallel and a shared inner lead extending in a direction substantially perpendicular to the respective signal inner leads near the tips of the signal inner leads. A lead frame for electrically connecting between the common inner lead and the signal inner lead and the semiconductor chip via the bonding wire, and the surface of the common inner lead connected to the bonding wire is A lead frame, which is formed to be lower than a surface of a signal inner lead connected to a bonding wire.
ナーリードの厚さよりも薄く形成される請求項4に記載
のリードフレーム。5. The lead frame according to claim 4, wherein the common inner lead is formed thinner than the signal inner lead.
ードの厚さはほぼ等しく形成される請求項4に記載のリ
ードフレーム。6. The lead frame according to claim 4, wherein the common inner lead and the signal inner lead are formed to have substantially the same thickness.
面上に配置され複数のインナーリードを備えるリードフ
レームと、該リードフレームと半導体チップとの間に介
挿されて両者を接着する絶縁体と、リードフレームのイ
ンナーリードと半導体チップとを電気的に接続するボン
ディングワイヤと、これらの要素を封入するモールド樹
脂とを有し、上記インナーリードは、並列配置された複
数の信号用インナーリードと、該信号用インナーリード
の先端近傍で各信号用インナーリードに対し略垂直方向
に延びる共用インナーリードとを有し、上記ボンディン
グワイヤに接続される共用インナーリードの面は、ボン
ディングワイヤに接続される信号用インナーリードの面
よりも低く形成される半導体装置。7. A semiconductor chip, a lead frame provided on the circuit surface of the semiconductor chip and having a plurality of inner leads, and an insulator interposed between the lead frame and the semiconductor chip to bond them to each other. A bonding wire that electrically connects the inner lead of the lead frame and the semiconductor chip, and a molding resin that encapsulates these elements, the inner lead having a plurality of signal inner leads arranged in parallel, A common inner lead extending in a direction substantially perpendicular to each signal inner lead in the vicinity of the tip of the signal inner lead, and a surface of the common inner lead connected to the bonding wire has a signal connected to the bonding wire. Device formed to be lower than the surface of the inner lead for use.
信号用インナーリードの隣り合うインナーリード間に延
びる複数の引き出しリードを有する請求項7に記載の半
導体装置。8. The semiconductor device according to claim 7, further comprising a plurality of lead leads extending from the common inner lead to adjacent inner leads of the signal inner lead.
ードよりも半導体チップの回路面に接近する請求項7又
は8に記載の半導体装置。9. The semiconductor device according to claim 7, wherein the shared inner lead is closer to the circuit surface of the semiconductor chip than the signal inner lead.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20094093A JPH0738031A (en) | 1993-07-21 | 1993-07-21 | Manufacture of lead frame and lead frame |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20094093A JPH0738031A (en) | 1993-07-21 | 1993-07-21 | Manufacture of lead frame and lead frame |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0738031A true JPH0738031A (en) | 1995-02-07 |
Family
ID=16432829
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20094093A Pending JPH0738031A (en) | 1993-07-21 | 1993-07-21 | Manufacture of lead frame and lead frame |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0738031A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007128988A (en) * | 2005-11-01 | 2007-05-24 | Sanyo Electric Co Ltd | Solid-state electrolytic capacitor and method of manufacturing same |
-
1993
- 1993-07-21 JP JP20094093A patent/JPH0738031A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007128988A (en) * | 2005-11-01 | 2007-05-24 | Sanyo Electric Co Ltd | Solid-state electrolytic capacitor and method of manufacturing same |
US7854772B2 (en) | 2005-11-01 | 2010-12-21 | Sanyo Electric Co., Ltd. | Solid electrolytic capacitor and manufacturing method therefor |
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