JP3185455B2 - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JP3185455B2
JP3185455B2 JP07126493A JP7126493A JP3185455B2 JP 3185455 B2 JP3185455 B2 JP 3185455B2 JP 07126493 A JP07126493 A JP 07126493A JP 7126493 A JP7126493 A JP 7126493A JP 3185455 B2 JP3185455 B2 JP 3185455B2
Authority
JP
Japan
Prior art keywords
lead
inner lead
resin
semiconductor chip
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP07126493A
Other languages
Japanese (ja)
Other versions
JPH06260592A (en
Inventor
寛隆 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP07126493A priority Critical patent/JP3185455B2/en
Publication of JPH06260592A publication Critical patent/JPH06260592A/en
Application granted granted Critical
Publication of JP3185455B2 publication Critical patent/JP3185455B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To provide a resin sealed semiconductor device wherein heat dissipation effect is improved, possibility of short-circuiting at the time of wire bonding is excluded, generation of PKG crack is restrained, and reliability is improved. CONSTITUTION:A plurality of outer leads 18 are led out from a common inner lead 12 so as to stretch between adjacent inner leads of a plurality of inner leads. Only the outer leads and the inner leads are connected with a semiconductor chip 22, partially interposing insulator 20.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は樹脂封止型半導体装置に
関し、特に、ＬＯＣ（Ｌｅａｄ Ｏｎ Ｃｈｉｐ）構造
のパッケージに適用される有用な技術に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device, and more particularly to a technique useful for a package having a LOC (Lead On Chip) structure.

【０００２】[0002]

【従来の技術】図ｌｌに従来の樹脂封止型半導体装置の
構成の一例を示す。同図に示すように、リードフレーム
２は絶縁フィルム４を介して素子（半導体チップ）３の
回路形成面の上部まで配置され、ボンディングワイヤ５
によりチップ３上の電極（ボンディングパッド）６と電
気的に接続される。そして、これらはモールド樹脂ｌで
封止され、全体としてＬＯＣ構造のパッケージが形成さ
れる。2. Description of the Related Art FIG. 11 shows an example of the configuration of a conventional resin-encapsulated semiconductor device. As shown in FIG. 1, the lead frame 2 is disposed up to the upper part of the circuit forming surface of the element (semiconductor chip) 3 via the insulating film 4, and the bonding wire 5
Thus, it is electrically connected to the electrode (bonding pad) 6 on the chip 3. These are sealed with a mold resin 1 to form a package having a LOC structure as a whole.

【０００３】リードフレーム２は、図１２に示すよう
に、半導体チップ３の回路形成面のＹ方向（紙面上で上
下方向）の中心線の近傍に位置する共用インナーリード
（バスバーインナーリード）４２と、半導体チップ３の
回路形成面上に位置する櫛形のインナーリード４４と、
該インナーリードを共通に結合するタイバー４６とを備
えている。このような樹脂封止型半導体装置や共用イン
ナーリードが設けられた半導体装置の例は、例えば特開
昭６１−２４１９５９号公報、特開平２−２４４７４６
号公報、同２−２４６１２５公報、同３−１７３４６４
号公報、同３−２０４９６５公報等に開示されている。As shown in FIG. 12, a lead frame 2 has a shared inner lead (bus bar inner lead) 42 located near a center line of the circuit forming surface of the semiconductor chip 3 in the Y direction (vertical direction on the paper). A comb-shaped inner lead 44 located on a circuit forming surface of the semiconductor chip 3,
And a tie bar 46 for commonly connecting the inner leads. Examples of such a resin-encapsulated semiconductor device and a semiconductor device provided with a common inner lead are disclosed in, for example, JP-A-61-241959 and JP-A-2-244746.
Gazette, JP-A-2-246125, and 3-173364
And JP-A-3-204965.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、上述し
た従来の半導体装置では、以下に記述するような種々の
問題点がある。まず、半導体チップ３上の発熱の大きい
部分（つまり各リードの部分）では、リードの量が比較
的少ないため、その放熱効果が不十分となり、そのため
に半導体装置の信頼性が劣化するという問題がある。However, the conventional semiconductor device described above has various problems as described below. First, in a portion of the semiconductor chip 3 where heat generation is large (that is, each lead portion), since the amount of leads is relatively small, the heat radiation effect becomes insufficient, and the reliability of the semiconductor device deteriorates. is there.

【０００５】また、ボンディングパッド６からインナー
リード４４へ共用インナーリード４２を越えてワイヤボ
ンディングを行おうとすると（１２（Ｂ）参照）、ボン
ディングワイヤ５が共用インナーリード４２に接触して
ショートしてしまう可能性がある。この傾向は、特にパ
ッケージ（ＰＫＧ）の厚さが薄くなると一層顕著にな
る。When wire bonding is performed from the bonding pad 6 to the inner lead 44 over the common inner lead 42 (see FIG. 12 (B)), the bonding wire 5 contacts the common inner lead 42 to cause a short circuit. there is a possibility. This tendency becomes more remarkable especially when the thickness of the package (PKG) is reduced.

【０００６】また、吸湿半田リフローを行うと、絶縁フ
ィルム４が吸収した水分が内部で蒸発しフィルムが発泡
状態となってＰＫＧクラックが発生し易くなる。特に、
ＰＫＧの厚さが薄くなると樹脂厚もそれに応じて薄くな
り、共用インナーリード４２の部分からＰＫＧクラック
が発生し易くなる。[0006] Further, when the moisture absorption solder reflow is performed, the moisture absorbed by the insulating film 4 evaporates inside, and the film becomes a foamed state, and PKG cracks are easily generated. In particular,
When the thickness of the PKG is reduced, the thickness of the resin is correspondingly reduced, and PKG cracks are easily generated from the portion of the common inner lead 42.

【０００７】また、絶縁フィルム４を半導体チップ３に
接着する際、両者間に空気を巻き込んで封入しボイドＶ
（図１２（Ａ）参照）が生じる場合があるが、この状態
でパッケージングを行うと吸湿半田リフロー時にパッケ
ージが加熱されボイド内の水分が蒸発してＰＫＧクラッ
クが発生し易くなる。特に、５０μｍ程度の薄い絶縁フ
ィルムではこの傾向が顕著に現れる。When the insulating film 4 is bonded to the semiconductor chip 3, air is entrapped and sealed between the two to form a void V.
(Refer to FIG. 12 (A)) may occur. However, if packaging is performed in this state, the package is heated during the reflow of the moisture-absorbing solder, and the moisture in the voids evaporates, so that PKG cracks are likely to occur. In particular, this tendency appears remarkably in a thin insulating film of about 50 μm.

【０００８】このようなクラックの不都合は、例えば図
１３に一例として示されるように、隣合うインナーリー
ド４４間の絶縁フィルム４ａを除去することで多少改善
される。しかしこの方法では、絶縁フィルムの張り付け
精度の向上、絶縁フィルムのカット金型の複雑化等が必
要となり、そのために、絶縁フィルムの取扱性が低下す
るといった問題が発生し、絶縁フィルムの薄膜化は困難
になる。また、多少なりともボイドＶ’が生じる（図１
３参照）。The inconvenience of such a crack is somewhat alleviated by removing the insulating film 4a between the adjacent inner leads 44, for example, as shown as an example in FIG. However, in this method, it is necessary to improve the accuracy of attaching the insulating film and to complicate the cutting die of the insulating film, which causes a problem that the handling property of the insulating film is reduced. It becomes difficult. In addition, a void V 'is generated to some extent (FIG. 1).
3).

【０００９】また、絶縁フィルム４とリードフレーム２
の張り付け精度が０．ｌｍｍ程度のため、共用インナー
リード４２をボンディングパッド６のすぐ横に配置する
と、該パッドが絶縁フィルム４に覆われてしまう場合が
ある。また、共用インナーリード４２とパッド６の距離
が短すぎるとワイヤボンディングが満足に行えなくなる
ため、両者間の距離は少なくとも０．５ｍｍ程度は確保
する必要がある。Also, the insulating film 4 and the lead frame 2
The sticking accuracy is 0. If the common inner lead 42 is disposed right beside the bonding pad 6, the pad may be covered with the insulating film 4. Further, if the distance between the common inner lead 42 and the pad 6 is too short, wire bonding cannot be performed satisfactorily. Therefore, it is necessary to secure a distance of at least about 0.5 mm.

【００１０】本発明は、上記従来技術における問題点に
鑑み創作されたものであって、放熱効果を向上させ、ワ
イヤボンディングの際のショートの可能性を排除すると
共に、ＰＫＧクラックの発生を抑制し、ひいては信頼性
の向上に寄与することができる樹脂封止型半導体装置の
提供を目的としている。The present invention has been made in view of the above-mentioned problems in the prior art, and improves the heat radiation effect, eliminates the possibility of a short circuit at the time of wire bonding, and suppresses the occurrence of PKG cracks. It is another object of the present invention to provide a resin-encapsulated semiconductor device that can contribute to improvement in reliability.

【００１１】[0011]

【課題を解決するための手段】上記課題を解決するた
め、本発明に係る樹脂封止型半導体装置は、半導体チッ
プと、該半導体チップの回路形成面上に位置する複数の
並列した信号用インナーリードおよび該インナーリード
先端の外側にインナーリードと略直角に配置された共用
インナーリードからなるリードフレームと、前記半導体
チップおよび前記各リードフレームの間に介在して両者
を接着する絶縁体と、前記各インナーリードと前記半導
体チップとを電気的に接続するボンディングワイヤと、
パッケージを形成するためのモールド樹脂とからなる樹
脂封止型半導体装置において、隣合う前記インナーリー
ド同士の間に配置される引き出しリードを前記共用イン
ナーリードに突設し、前記絶縁体を、前記インナーリー
ドの先端と前記引き出しリードの先端との間で前記イン
ナーリードおよび前記引き出しリードに交差させて配設
し、且つ隣接する前記インナーリードと前記引き出しリ
ードとの間の前記絶縁体に、透孔を穿設したことを特徴
とするものである。In order to solve the above-mentioned problems, a resin-encapsulated semiconductor device according to the present invention comprises a semiconductor chip and a plurality of parallel signal inner members located on a circuit forming surface of the semiconductor chip. A lead frame comprising a lead and a common inner lead disposed substantially perpendicular to the inner lead on the outer side of the tip of the inner lead; an insulator interposed between the semiconductor chip and each of the lead frames to bond them; and Bonding wires for electrically connecting each inner lead and the semiconductor chip,
In the resin-encapsulated semiconductor device comprising a molding resin for forming a package, adjacent the inner Lee
Drawer lead placed between
Projecting from the inner lead, and attaching the insulator to the inner lead.
Between the tip of the lead and the tip of the drawer lead.
Disposed across the knurled lead and the drawer lead
And the adjacent inner lead and the drawer
A hole is formed in the insulator between the base and the insulator .

【００１２】この樹脂封止型半導体装置では、引き出し
リードを設けることにより共用インナーリードが枝分か
れした形状となり、リード部分で発生する熱が効果的に
放出されることになる。また、絶縁体が、インナーリー
ドの先端と引き出しリードの先端との間で配設される。
換言すれば、インナーリードの先端と、共用インナーリ
ードとの間、及び引き出しリードの先端と、半導体チッ
プの外縁との間には、絶縁体が配設されないことにな
る。従って、インナーリード及び共用インナーリードを
支持する絶縁体の面積が必要最小限で形成可能になる。
これに加えて、隣接するインナーリードと引き出しリー
ドとの間の絶縁体に透孔が穿設されることで、さらに絶
縁体の面積が小さく形成可能になる。これにより、チッ
プ接着時の空気巻き込みが極めて効果的に抑止され、且
つテープ自体による吸湿量も大幅に小さくなり、吸湿半
田リフロー時のＰＫＧクラックの発生がより確実に防止
可能となる。また、隣接するインナーリードと引き出し
リードとの間の絶縁体に透孔が穿設される構造とするこ
とで、透孔穿設のための金型形状が単純となり、且つ成
形作業も容易になる。即ち、安価且つ容易に、絶縁体面
積の縮小化が可能になる。 In this resin-encapsulated semiconductor device, by providing the lead-out lead, the common inner lead has a branched shape, and the heat generated in the lead portion is effectively released. Also, if the insulator is
And between the tip of the lead and the tip of the drawer lead.
In other words, the tip of the inner lead and the common inner lead
Between the semiconductor chip and the tip of the extraction lead and the semiconductor chip.
There will be no insulator between the outer edge of the
You. Therefore, the inner lead and the common inner lead
The supporting insulator can be formed with a minimum necessary area.
In addition, adjacent inner leads and drawer leads
Holes are drilled in the insulator between the
The area of the edge body can be formed small. As a result,
Entrapment of air during bonding is extremely effectively suppressed, and
The amount of moisture absorption by the tape itself is also significantly reduced,
Prevents the generation of PKG cracks during field reflow
It becomes possible. In addition, the adjacent inner lead and drawer
The structure shall be such that a through hole is formed in the insulator between the lead.
Thus, the shape of the mold for drilling the through-hole is simplified, and
Forming work is also easy. That is, the insulator surface can be inexpensively and easily.
The product can be reduced.

【００１３】[0013]

【実施例】図ｌに本発明の実施例に係る樹脂封止型半導
体装置の構成の一例を示す。図中、（Ａ）は樹脂封止前
の平面構成を示し、（Ｂ）は（Ａ）のＡ−Ａ’線に沿っ
た樹脂封止後の断面構成を示すものである。また、１０
はリードフレーム、１２は共用インナーリード（バスバ
ーインナーリード）、１４は信号用インナーリード、１
６は該インナーリードを共通に結合するタイバー、１８
は共用インナーリード１２から引き出された引き出しリ
ード、２０は絶縁フィルム、２２は半導体チップ、２４
はボンディングパッド、２６，２８は金（Ａｕ）線から
成るボンディングワイヤ、３０は封止用のモールド樹脂
を示す。FIG. 1 shows an example of the configuration of a resin-sealed semiconductor device according to an embodiment of the present invention. In the drawing, (A) shows a planar configuration before resin sealing, and (B) shows a cross-sectional configuration after resin sealing along line AA ′ in (A). Also, 10
Is a lead frame, 12 is a common inner lead (bus bar inner lead), 14 is a signal inner lead, 1
6 is a tie bar for connecting the inner leads in common, 18
Is a lead lead drawn out of the common inner lead 12, 20 is an insulating film, 22 is a semiconductor chip, 24
Is a bonding pad, 26 and 28 are bonding wires made of gold (Au) wire, and 30 is a molding resin for sealing.

【００１４】図１に示すように本実施例では、タイバー
１６（樹脂封止後切断除去される）によって結合された
櫛形のインナーリード１４は半導体チップ２２の回路形
成面上に位置し、一方、共用インナーリード１２は半導
体チップ２２の回路形成面のＹ方向（紙面上で上下方
向）の中心線の近傍に位置しており、これら各リードは
全体としてリードフレームｌ０を構成している。また、
絶縁フィルム２０はリードフレーム１０と半導体チップ
２２の間に介在して両者を接着している。インナーリー
ド１４および共用インナーリード１２は、ボンディング
ワイヤ２６，２８により半導体チップ２２上の電極（ボ
ンディングパッド２４）に電気的に接続されている。そ
して、上述した各部材はモールド樹脂３０で封止され、
全体としてＬＯＣ構造のパッケージが形成される。As shown in FIG. 1, in the present embodiment, the comb-shaped inner leads 14 joined by the tie bars 16 (cut and removed after resin sealing) are located on the circuit forming surface of the semiconductor chip 22. The common inner lead 12 is located near the center line of the circuit forming surface of the semiconductor chip 22 in the Y direction (vertical direction on the paper), and these leads as a whole constitute a lead frame 10. Also,
The insulating film 20 is interposed between the lead frame 10 and the semiconductor chip 22 to bond them. The inner lead 14 and the common inner lead 12 are electrically connected to electrodes (bonding pads 24) on the semiconductor chip 22 by bonding wires 26 and 28. And each above-mentioned member is sealed with mold resin 30,
As a whole, a package having a LOC structure is formed.

【００１５】さらに本実施例では、隣合うインナーリー
ド１４同士の間に配置される引き出しリード１８が、共
用インナーリード１２に突設されている。また、絶縁フ
ィルム２０は、インナーリード１４の先端と、引き出し
リード１８の先端との間で、インナーリード１４および
引き出しリード１８に交差するようにして配設されてい
る。つまり、引き出しリード１８と各インナーリード１
４のみが部分的に絶縁フィルム２０を介在して半導体チ
ップ２２に接着されている。即ち、絶縁フィルム２０は
インナーリード１４の先端より内側に配置される。な
お、本明細書において、「内側」とはインナーリードの
先端に対し、チップ２２の外縁部側を言う。Further, in the present embodiment, the inner
Lead 14 arranged between the leads 14
Protruding from the inner lead 12. Also, insulation
The film 20 has a tip of the inner lead 14 and a drawer.
Between the tip of the lead 18 and the inner lead 14 and
It is arranged so as to cross the drawer lead 18.
You. That is, the lead 18 and each inner lead 1
Only the semiconductor chip 4 partially has the insulating film 20 interposed therebetween.
It is adhered to the top 22. That is, the insulating film 20 is disposed inside the tip of the inner lead 14. In this specification, “inside” refers to the inner lead .
The outer edge side of the tip 22 with respect to the tip.

【００１６】以下、作製方法について説明する。まず、
リードフレーム１０をエッチングまたはプレスにより作
製する。このリードフレームｌ０の材質はＦｅ−Ｎｉ系
またはＣｕ系である。次に、長方形に切り抜いた絶縁フ
ィルム２０（接着テープ−基材−接着テープの３層構造
で、接着テープはガラス転移点が１６０°Ｃ程度の熱可
塑性樹脂で作られる）をリードフレームｌ０の下に配置
し、上から５ｋｇ、温度２００°Ｃ、ｌｓ程度で加圧す
ると、リードフレーム１０にテープが接着される。Hereinafter, the manufacturing method will be described. First,
The lead frame 10 is manufactured by etching or pressing. The material of the lead frame 10 is Fe-Ni or Cu. Next, an insulating film 20 cut into a rectangular shape (adhesive tape-substrate-adhesive tape has a three-layer structure, and the adhesive tape is made of a thermoplastic resin having a glass transition point of about 160 ° C.) is placed under the lead frame 10. When pressure is applied at about 5 kg, temperature of 200 ° C., and about 1 s from above, the tape is adhered to the lead frame 10.

【００１７】次いで、絶縁フィルム２０が付着されたリ
ードフレーム１０をチップ２２上に位置決めし、上から
２ｋｇ、温度２６０°Ｃ、１ｓ程度で加圧すると、該チ
ップ２２とリードフレームｌ０が（絶縁フィルム２０を
介在して）接着される。これをワイヤボンディングする
と、図示のようになる。そして、これをモールド樹脂３
０で封止して適宜カッティングを行えば、ＬＯＣ構造の
パッケージが出来上がる。Next, the lead frame 10 having the insulating film 20 attached thereto is positioned on the chip 22 and pressurized at 2 kg from above, at a temperature of 260 ° C. for about 1 s, and the chip 22 and the lead frame 10 are (insulated film). 20). When this is wire-bonded, the result is as shown in the figure. And this is molded resin 3
If sealing is performed at 0 and cutting is performed appropriately, a package having a LOC structure is completed.

【００１８】上述した本実施例の構成によれば、以下の
利点が得られる。まず、引き出しリード１８を設けたこ
とにより共用インナーリード１２が枝分かれした形状と
なるので表面積が増加し、リードの部分で発生した熱を
効果的に放出することができる。つまり、放熱効果を向
上させることができる。According to the configuration of this embodiment described above, the following advantages can be obtained. First, by providing the lead-out lead 18, the common inner lead 12 has a branched shape, so that the surface area increases, and the heat generated in the lead portion can be effectively released. That is, the heat radiation effect can be improved.

【００１９】また、共用インナーリード１２をパッド２
４とインナーリード１４の間のどこにでも配置できるの
で、パッド配置の自由度が増すとともに金線２６と共用
インナーリード１２の接触を防ぐことが可能である。ま
た、絶縁フィルム２０（接着テープ）の幅を狭くできる
ので、チップ接着時の空気巻き込みを防止でき、これに
よって吸湿半田リフロー時のＰＫＧクラックを発生し難
くすることが可能となる。また、テープ自体の吸湿量が
減少するためテープ発泡によるクラックが減少する。The common inner lead 12 is connected to the pad 2
Since it can be arranged anywhere between the inner lead 4 and the inner lead 14, it is possible to increase the degree of freedom of pad arrangement and prevent the gold wire 26 from being in contact with the common inner lead 12. Further, since the width of the insulating film 20 (adhesive tape) can be reduced, air entrapment at the time of chip bonding can be prevented, thereby making it difficult to generate a PKG crack at the time of reflow soldering. In addition, since the amount of moisture absorbed by the tape itself is reduced, cracks due to tape foaming are reduced.

【００２０】さらに、共用インナーリード１２は絶縁フ
ィルム２０を用いて直接半導体チップ２２に接着しない
（つまり引き出しリード１８で接着する）ので、共用イ
ンナーリード１２とパッド２４をボンディングワイヤで
接続する場合、該ボンディングワイヤの他端側は引き出
しリード１８上に接続すればよい。従って、共用インナ
ーリード１２とパッド２４の距離を従来形よりも短縮す
ることができる。Further, since the common inner lead 12 is not directly adhered to the semiconductor chip 22 using the insulating film 20 (that is, adhered by the lead-out lead 18), when the common inner lead 12 and the pad 24 are connected by a bonding wire, the common inner lead 12 is not bonded to the semiconductor chip 22. The other end of the bonding wire may be connected to the lead 18. Therefore, the distance between the common inner lead 12 and the pad 24 can be reduced as compared with the conventional type.

【００２１】また、共用インナーリードの下部には絶縁
フィルムが設けられないため、絶縁フィルムの位置決め
精度をラフにしてもパッドとの接触の問題が起こらな
い。なお、この場合共用インナーリードは素子表面から
浮いた形状となるがリードフレーム自体の強度によリワ
イヤボンディングは充分可能である。Further, since the insulating film is not provided below the common inner lead, the problem of contact with the pad does not occur even if the positioning accuracy of the insulating film is roughened. In this case, the common inner lead has a shape floating above the element surface, but rewire bonding is sufficiently possible depending on the strength of the lead frame itself.

【００２２】次に、本実施例の各変形例について図２〜
図７を参照しながら説明する。図２に示す第ｌ変形例で
は、ボンディングパッド２４ａを共用インナーリード１
２の内側、すなわち共用インナーリード１２と信号用イ
ンナーリード１４の先端との間の領域に設けたことを特
徴としている。このような構成とすれば、従来のように
ボンディングワイヤが共用インナーリードをクロスオ一
バーすることによる接触（ショート）の問題は起こらな
い。Next, FIGS.
This will be described with reference to FIG. In the first modification shown in FIG. 2, the bonding pad 24a is
2, that is, in a region between the common inner lead 12 and the tip of the signal inner lead 14. With such a configuration, the problem of contact (short) due to the crossover of the common inner lead by the bonding wire does not occur as in the related art.

【００２３】図３に示す第２変形例では、共用インナー
リード１２ａの引出しリード１８をディプレス（図中、
Ｐで示す部分）し屈曲変形させて共用インナーリード側
を押し下げチップ２２側に近づけたことを特徴としてい
る。なお、ディプレスした共用インナーリード１２ａの
部分はチップ２２に平行に対向させずに斜めに傾斜した
状態で屈曲した形状でもよい。In the second modification shown in FIG. 3, the lead 18 of the common inner lead 12a is depressed (in the drawing,
(The portion indicated by P) is bent and deformed to push down the common inner lead side to approach the chip 22 side. The depressed portion of the common inner lead 12a may be bent not obliquely but not in parallel with the chip 22.

【００２４】このようなディプレス処理を施すことによ
り、ワイヤ越えがし易くなる。また共用インナーリード
１２ａ上にワイヤボンディングする場合に安定してワイ
ヤボンディングを行うことができ、さらにはノイズ対策
にも有効である。また、共用インナーリードの上側の樹
脂が厚くなり強度が高まるため、従来のようにこの部分
からのクラック発生が防止される。By performing such a depressing process, the wire can be easily passed over. Further, when wire bonding is performed on the common inner lead 12a, wire bonding can be stably performed, and it is also effective for noise suppression. Further, since the resin on the upper side of the common inner lead is thickened and the strength is increased, the occurrence of cracks from this portion as in the related art is prevented.

【００２５】図４，図５にそれぞれ示す第３，第４変形
例では、半導体チップ２２にリードフレームを接着する
ための絶縁フィルム２０ａ，２０ｂを部分的に（つまり
インナーリード１４と引き出しリード１８の近傍部分の
みに）付着させたことを特徴としている。In the third and fourth modifications shown in FIGS. 4 and 5, respectively, the insulating films 20a and 20b for bonding the lead frame to the semiconductor chip 22 are partially (that is, the inner leads 14 and the lead leads 18). (Only in the vicinity).

【００２６】図４の例では、絶縁フィルム２０ａはイン
ナーリード１４と平行に各インナーリード１４および引
き出しリード１８に対応して分割されている。図５の例
では、隣接するインナーリード１４と引き出しリード１
８との間の絶縁フィルム２０ｂに、空白部（即ち、透
孔）が穿設されている。 In the example of FIG. 4, the insulating film 20a is divided in parallel with the inner leads 14 corresponding to the inner leads 14 and the lead-out leads 18. Example of FIG.
Then, the adjacent inner lead 14 and drawer lead 1
8, a blank portion (that is, a transparent portion) is provided on the insulating film 20b.
Holes) are drilled.

【００２７】このように絶縁フィルムを部分的に付ける
ことにより、接着テープの使用量を少なくでき、またリ
ード１４，１８で加圧される部分の接着テープ面績を少
なくできるので、接着時の空気封入防止が図られボイド
によるＰＫＧクラックの発生およびテープ自体の吸湿に
よるクラック発生を抑制することが可能となる。By partially attaching the insulating film in this manner, the amount of the adhesive tape used can be reduced, and the surface area of the adhesive tape pressed by the leads 14 and 18 can be reduced. It is possible to prevent encapsulation, thereby suppressing the occurrence of PKG cracks due to voids and the occurrence of cracks due to moisture absorption of the tape itself.

【００２８】なお、図４，図５に示す半導体装置の作製
方法は、個別にｌ枚ずつ付けてもよいが、図ｌに示した
ように接着テープ（絶縁フィルム）を付けてから、カッ
ト金型で切り抜いてもよい。なお、現状技術のＬＯＣ構
造では、カット金型を用いてリードで加圧されない部分
を全て除くのは難しいが、この形状であれば可能であ
る。即ち、従来の図１３のようなＵ字形に除去すること
は金型製作が複雑となり成形作業も面倒になるが、上記
本発明の形状（即ち、絶縁フィルム２０ａ、絶縁フィル
ム２０ｂに示した形状）であれば金型も単純となり成形
作業も容易になる。つまり、安価且つ容易に、絶縁フィ
ルム面積の縮小化が可能になる。 In the method of manufacturing the semiconductor device shown in FIGS. 4 and 5, the semiconductor device may be individually attached one by one. However, as shown in FIG. You may cut out with a mold. In the LOC structure according to the state of the art, it is difficult to remove all parts that are not pressed by the leads using a cutting die, but this shape is possible. That is, the die manufacturing to remove the U-shape, such as a conventional 13 also becomes troublesome molding operation becomes complicated, the shape of the present invention (i.e., the insulating film 20a, the insulating fill
(The shape shown in FIG. 20b) , the mold becomes simpler and the molding operation becomes easier. In other words, it is cheap and easy
It is possible to reduce the lum area.

【００２９】図６に示す第５変形例では、引き出しリー
ド１８ａをタイバー１６に連結したことを特徴としてい
る。このような構造とすることにより、リードの変形を
少なくでき、またリード部分の量が多くなることで放熱
性の向上を図ることができ、さらには共用インナーリー
ド１２上へのワイヤボンディングをより安定に行うこと
ができる。The fifth modification shown in FIG. 6 is characterized in that the lead 18a is connected to the tie bar 16. By adopting such a structure, the deformation of the lead can be reduced, and the heat dissipation can be improved by increasing the amount of the lead portion. Further, the wire bonding on the common inner lead 12 can be more stable. Can be done.

【００３０】図７に示す第６変形例では、上述した第５
変形例の構成に加えて、図３の実施例のように共用イン
ナーリード１２ａに対しディプレス処理（図中、Ｐで示
す部分）を施したことを特徴としている。このような構
造とすることにより、第５変形例で得られる放熱性の向
上や安定したワイヤボンディングの効果に加えて、前述
のように図３の第２変形例で得られるディプレスによる
効果が得られる。In the sixth modification shown in FIG.
In addition to the configuration of the modified example, a depressing process (portion indicated by P in the figure) is performed on the common inner lead 12a as in the embodiment of FIG. By adopting such a structure, in addition to the effect of improving heat dissipation and the effect of stable wire bonding obtained in the fifth modification, the effect of depressing obtained in the second modification of FIG. can get.

【００３１】図８は本発明に係る実施例のさらに別の変
形例を示す。この例は、信号用インナーリード１４の先
端に対向する位置の共用インナーリード１２を、ハーフ
エッチング処理等により、他の部分より薄くして薄肉部
３１（斜線部）を形成したものである。このような薄肉
部３１を設けることにより、ボンディングワイヤ２６が
共用インナーリード１２をクロスオーバーして信号用イ
ンナーリード１４に接続される場合に、このボンディン
グワイヤ２６と共用インナーリード１２との接触防止が
さらに確実に達成される。その他の構成および作用効果
は前記図ｌの実施例と同様である。FIG. 8 shows still another modification of the embodiment according to the present invention. In this example, the common inner lead 12 at a position facing the tip of the signal inner lead 14 is made thinner than the other portions by half-etching or the like to form a thin portion 31 (hatched portion). By providing such a thin portion 31, when the bonding wire 26 is connected to the signal inner lead 14 by crossing over the common inner lead 12, the contact between the bonding wire 26 and the common inner lead 12 can be prevented. More reliably achieved. The other configuration and operation and effect are the same as those of the embodiment of FIG.

【００３２】図９は図８の実施例の変形例を示す。この
例は、前記薄肉部３１を共用インナーリード１２の全長
にわたって形成した構成であり、その他の構成および作
用効果は図８の例と同様である。FIG. 9 shows a modification of the embodiment of FIG. This example has a configuration in which the thin portion 31 is formed over the entire length of the common inner lead 12, and the other configurations and operational effects are the same as those in the example of FIG.

【００３３】図ｌ０は、上記薄肉部３１を形成した共用
インナーリード１２を図６の実施例に適用した構成を示
す。このような構成により、放熱性の向上等図６の構成
の効果に加えてボンディングワイヤ接触防止の効果がさ
らに高められる。なお、この薄肉部３１はその他の各種
実施例における共用インナーリードに対し適用して形成
可能である。FIG. 10 shows a configuration in which the common inner lead 12 having the thin portion 31 is applied to the embodiment of FIG. With such a configuration, in addition to the effects of the configuration shown in FIG. The thin portion 31 can be formed by applying to the common inner lead in the other various embodiments.

【００３４】[0034]

【発明の効果】以上説明したように、本発明に係る樹脂
封止型半導体装置によれば、隣合うインナーリード同士
の間に配置される引き出しリードを共用インナーリード
に突設し、絶縁体を、インナーリードの先端と引き出し
リードの先端との間でインナーリードおよび引き出しリ
ードに交差させて配設し、且つ隣接するインナーリード
と引き出しリードとの間の絶縁体に、透孔を穿設したの
で、放熱性を向上させ、ワイヤボンディングの際のショ
ートの可能性を排除すると共に、絶縁体面積を必 要最小
限に小さくしてＰＫＧクラックの発生を抑止することが
できる。 As described above, according to the resin-encapsulated semiconductor device of the present invention, adjacent inner leads are connected to each other.
Shared inner lead with drawer lead placed between
And pull out the insulator from the tip of the inner lead.
Insert the inner lead and drawer
Inner lead that is placed across the
A through hole was made in the insulator between
This improves heat dissipation and improves the performance of wire bonding.
Thereby eliminating the possibility of over preparative, it must minimize the insulator area
To minimize the occurrence of PKG cracks
it can.

【図面の簡単な説明】[Brief description of the drawings]

【図ｌ】 本発明の一実施例としての樹脂封止型半導体
装置の構成を示す図で、（Ａ）は樹脂封止前の平面図、
（Ｂ）は（Ａ）のＡ−Ａ’線に沿った樹脂封止後の断面
図である。1A and 1B are diagrams showing a configuration of a resin-sealed semiconductor device as one embodiment of the present invention, wherein FIG.
(B) is a cross-sectional view after resin sealing along the line AA 'in (A).

【図２】 図１の実施例の第ｌ変形例の構成を示す図で
ある。FIG. 2 is a diagram showing a configuration of a first modification of the embodiment in FIG. 1;

【図３】 図ｌの実施例の第２変形例の構成を示す図
で、（Ａ）は樹脂封止前の平面図、（Ｂ）は（Ａ）のＡ
−Ａ’線に沿った断面図である。FIGS. 3A and 3B are diagrams showing a configuration of a second modification of the embodiment in FIG. 1; FIG. 3A is a plan view before resin sealing; FIG.
It is sectional drawing which followed the -A 'line.

【図４】 図ｌの実施例の第３変形例の構成を示す図で
ある。FIG. 4 is a diagram showing a configuration of a third modification of the embodiment in FIG. 1;

【図５】 図ｌの実施例の第４変形例の構成を示す図で
ある。FIG. 5 is a diagram showing a configuration of a fourth modification of the embodiment in FIG. 1;

【図６】 図ｌの実施例の第５変形例の構成を示す図で
ある。FIG. 6 is a diagram showing a configuration of a fifth modification of the embodiment in FIG. 1;

【図７】 図ｌの実施例の第６変形例の構成を示す図
で、（Ａ）は樹脂封止前の平面図、（Ｂ）は（Ａ）のＡ
−Ａ’線に沿った断面図である。7A and 7B are diagrams showing a configuration of a sixth modification of the embodiment in FIG. 1; FIG. 7A is a plan view before resin sealing, and FIG.
It is sectional drawing which followed the -A 'line.

【図８】 本発明の別の実施例の構成を示す図で、
（Ａ）は樹脂封止前の平面図、（Ｂ）は（Ａ）のＡ−
Ａ’線に沿った断面図である‘FIG. 8 is a diagram showing a configuration of another embodiment of the present invention;
(A) is a plan view before resin sealing, and (B) is A- in FIG.
A 'is a sectional view taken along the line A'.

【図９】 図８の実施例の変形例の構成を示す図で、
（Ａ）は樹脂封止前の平面図、（Ｂ）は（Ａ）のＡ−
Ａ’線に沿った断面図である。FIG. 9 is a diagram showing a configuration of a modification of the embodiment of FIG. 8;
(A) is a plan view before resin sealing, and (B) is A- in FIG.
It is sectional drawing which followed the A 'line.

【図ｌ０】 図８の実施例の別の適用例の平面図であ
る。FIG. 10 is a plan view of another application example of the embodiment of FIG. 8;

【図１１】 従来形の一例としての樹脂封止型半導体装
置の構成を示す図で、（Ａ）は一部切り欠き斜視図、
（Ｂ）は（Ａ）の横断面図、（Ｃ）は樹脂封止前の分解
斜視図である。11A and 11B are diagrams illustrating a configuration of a resin-encapsulated semiconductor device as an example of a conventional type, in which FIG.
(B) is a cross-sectional view of (A), and (C) is an exploded perspective view before resin sealing.

【図１２】 図８の構成に係る問題点の説明図で、
（Ａ）は樹脂封止前の平面図、（Ｂ）は（Ａ）のＡ−
Ａ’線に沿った樹脂封止後の断面図である。FIG. 12 is an explanatory diagram of a problem with the configuration of FIG. 8;
(A) is a plan view before resin sealing, and (B) is A- in FIG.
It is sectional drawing after resin sealing along the A 'line.

【図１３】 従来形の他の例としての樹脂封止型半導体
装置の構成を示す図である。FIG. 13 is a diagram showing a configuration of a resin-sealed semiconductor device as another example of the conventional type.

【符号の説明】[Explanation of symbols]

ｌ０…リードフレーム １２，１２ａ…共用インナーリード（バスバーインナー
リード） １４…信号用インナーリード １６…タイバー １８，１８ａ…引き出しリード ２０，２０ａ，２０ｂ…絶縁体（絶縁フィルム） ２２…半導体チップ ２４，２４ａ…ボンディングパッド ２６，２８…ボンディングワイヤ（金線） ３０…モールド樹脂 Ｐ…共用インナーリードのディプレスした部分10 Lead frame 12, 12a Shared inner lead (bus bar inner lead) 14 Signal inner lead 16 Tie bar 18, 18a Leader lead 20, 20a, 20b Insulator (insulating film) 22 Semiconductor chip 24, 24a ... Bonding pads 26 and 28 ... Bonding wires (gold wires) 30 ... Mold resin P ... Depressed portions of common inner leads

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体チップと、該半導体チップの回路
形成面上に位置する複数の並列した信号用インナーリー
ドおよび該インナーリード先端の外側にインナーリード
と略直角に配置された共用インナーリードからなるリー
ドフレームと、前記半導体チップおよび前記リードフレ
ームの間に介在して両者を接着する絶縁体と、前記各イ
ンナーリードと前記半導体チップとを電気的に接続する
ボンディングワイヤと、パッケージを形成するためのモ
ールド樹脂とからなる樹脂封止型半導体装置において、 隣合う前記インナーリード同士の間に配置される引き出
しリードを前記共用インナーリードに突設し、 前記絶縁体を、前記インナーリードの先端と前記引き出
しリードの先端との間で前記インナーリードおよび前記
引き出しリードに交差させて配設し、 且つ隣接する前記インナーリードと前記引き出しリード
との間の前記絶縁体に、透孔を穿設したことを特徴とす
る樹脂封止型半導体装置。1. A semiconductor chip, comprising: a plurality of parallel signal inner leads located on a circuit forming surface of the semiconductor chip; and a shared inner lead disposed outside a tip of the inner lead at a substantially right angle to the inner lead. A lead frame, an insulator interposed between the semiconductor chip and the lead frame and bonding the two, a bonding wire for electrically connecting the inner leads to the semiconductor chip, and a package for forming a package. In a resin-encapsulated semiconductor device made of a mold resin, a lead lead disposed between adjacent inner leads is projected from the shared inner lead, and the insulator is connected to a tip of the inner lead and the lead. The inner lead and the lead-out lead intersect with the tip of the lead. Arranged to, and the insulator between the adjacent the inner leads the outgoing lead, resin-encapsulated semiconductor device, characterized in that the drilled hole.
JP07126493A 1993-03-05 1993-03-05 Resin-sealed semiconductor device Expired - Fee Related JP3185455B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP07126493A JP3185455B2 (en) 1993-03-05 1993-03-05 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07126493A JP3185455B2 (en) 1993-03-05 1993-03-05 Resin-sealed semiconductor device

Publications (2)

Publication Number Publication Date
JPH06260592A JPH06260592A (en) 1994-09-16
JP3185455B2 true JP3185455B2 (en) 2001-07-09

Family

ID=13455697

Family Applications (1)

Application Number Title Priority Date Filing Date
JP07126493A Expired - Fee Related JP3185455B2 (en) 1993-03-05 1993-03-05 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JP3185455B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10214933A (en) * 1997-01-29 1998-08-11 Toshiba Corp Semiconductor device and its manufacturing
JP2016004887A (en) * 2014-06-17 2016-01-12 Ｓｈマテリアル株式会社 Lead frame, and method of manufacturing lead frame

Also Published As

Publication number Publication date
JPH06260592A (en) 1994-09-16

Similar Documents

Publication Publication Date Title
US6756689B2 (en) Power device having multi-chip package structure
US6946722B2 (en) Multi-part lead frame with dissimilar materials
JPH08222681A (en) Resin sealed semiconductor device
JPH08330508A (en) Semiconductor integrated circuit and its manufacturing method
JP2004153220A (en) Lead frame, its manufacturing method, plastic molding semiconductor device and its manufacturing device
KR880014671A (en) Resin Filled Semiconductor Device
JPH0455341B2 (en)
KR960005039B1 (en) Semiconductor device
JP3684434B2 (en) Chip size semiconductor package and manufacturing method thereof
JP3185455B2 (en) Resin-sealed semiconductor device
JP3670371B2 (en) Semiconductor device and manufacturing method thereof
JPH03280453A (en) Semiconductor device and manufacture thereof
JP2518247Y2 (en) Lead frame
JP3406147B2 (en) Semiconductor device
JP2002164496A (en) Semiconductor device and method for manufacturing the same
JPH0758273A (en) Lead frame and semiconductor device using same
JP2582534B2 (en) Method for manufacturing semiconductor device
JP2000058738A (en) Lead frame and semiconductor device
JP2963952B2 (en) Semiconductor device
JPH05291473A (en) Plastic sealed semiconductor device and leadframe for use with it
JPH0547835A (en) Mounting structure of semiconductor device
JPH06291245A (en) Semiconductor device
JPH0582701A (en) Resin sealed semiconductor device
JPH031551A (en) Resin-sealed semiconductor device
JPH02303056A (en) Manufacture of semiconductor integrated circuit

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees