JPH0736780A - Method and device for storing block data - Google Patents

Abstract

PURPOSE:To shorten the time required to store the prescribed block data in the block data to be inputted in succession. CONSTITUTION:When '10' is set from the non-operation state where '00' is set to a register SR, the start is standing by. When the head of block data is inputted, the register SR becomes an end waiting state set to the '01'. In this state, the block data are stored and the '00' is stored in the register SR when block data is ended to become a non-operation state. On the other hand, when '11' is set to the register SR from the non-operation state, the continuous operation state is produced to store the block data to be inputted in succession in an updating state. In this state, when '01' is set to the register SR, the end waiting state is produced. The stand-by state continues till the block data to be inputted at this point are ended. When the input of the block data is ended, the non-operation state is produced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a block data storing method and apparatus for storing continuously inputted block data at a predetermined timing.

[0002]

2. Description of the Related Art Conventionally, for example, in image processing,
Image data for one frame (screen) continuously input from an image pickup device such as a television camera is input to a storage device called a frame memory for recording with a digital value indicating a gray level, or a gray level distribution of the image data. Histogram processing for obtaining is performed. In this case, such image processing is performed by using 1 in the image data input to the frame memory.
By storing the image data for one frame from the head data of the frame, the processing for one time can be executed.

By the way, when image data is recorded in a frame memory, for example, since the timing of issuing a recording instruction and the timing of inputting the first data of one frame in the image data are asynchronous, after the recording instruction is issued. The image data for one frame is recorded after waiting until the leading data of one frame in the image data is input.

FIG. 7 shows an example in which the state transition of the above operation is controlled using a register SR for indicating a recording instruction or a recording state. That is, the state S00 indicates a non-operating state in which the recording operation is prohibited. When "10" is written in the register SR, the state becomes S10, and the image data input standby state is set. In this case, the FSTART signal is output when the input of one frame in the image data is started, and the FEND signal is output (0 when the input ends).
Is activated in the FSTA.
When the RT signal becomes "0", the register SR is in the state S.
It is set to the end standby state indicated by 01. In the end standby state, the image data is stored in the frame memory and the register SR maintains "01" during that period. Then, when the FEND signal becomes "0" due to the recording of the image data for one frame, the register SR becomes "00" and transitions to the non-operation state S00, and the recording operation ends.

FIG. 8 shows the register S in the recording operation.
FIG. 6 is a timing chart showing respective states of R, FSTART signal, and FEND signal. In this case, it is indicated that a recording instruction is issued at time Tc, image data recording is started at time Ts, and the recording operation is ended at time Te. Therefore, in the example shown in FIG. 8, the time Tr (hereinafter referred to as processing time) required to record one frame of image data after issuing a recording instruction is Tr = Te-Tc = (Te-Ts) + (Ts-Tc), and the time required to input one frame of image data (hereinafter referred to as recording time) and the time from when the recording instruction is issued until the actual recording of image data is started (hereinafter It is the sum of the waiting time). In this case, since the recording time is always constant, the processing time Tr varies depending on the waiting time, that is, the timing of issuing the recording instruction.

FIG. 9 shows an example of the timing when the processing time Tr becomes the shortest, and shows the case where the recording instruction is issued immediately before the input of the head data of one frame in the image data. Further, FIG. 10 is an example of the timing when the processing time becomes the longest, and shows the case where the recording instruction is issued immediately after the input of the head data of one frame in the image data. Therefore, the possible range of the processing time Tr is (Te-Ts) <Tr <2 · (Te-Ts), and therefore the processing time Tr needs to be twice as long as the recording time in the longest case. become.

[0007]

By the way, in image processing, in recent years, there has been an increasing demand for higher processing speed. Depending on the processing application, the time required for data processing of recorded image data is increased. Despite being short
The time required for recording may occupy a problematic part of the image processing time. However, in the above-described conventional recording method, it is difficult to speed up the image processing because at least the recording time is required as the processing time depending on the timing of the recording instruction. This applies not only to image processing but also to measurement processing such as histogram processing.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a block data storage method and apparatus capable of shortening the storage time of predetermined block data in continuously input block data. To do.

[0009]

SUMMARY OF THE INVENTION The present invention is a block data storing method for storing block data to be continuously input at a predetermined timing, when a continuous operation is commanded from a non-operating state in which block data storage is prohibited. Stores the block data in the updated state, and when an end standby is instructed, shifts to the non-operation state when the storage of the block data being input is completed at the instruction timing.

In this case, when a start standby command is issued from the non-operating state, the block data to be input next may be stored and then the non-operating state may be entered. Further, in a block data storage device that stores continuously input block data in a storage circuit at a predetermined timing, the non-operating state is sequentially set to each of a continuous operating state and an end standby state, and the end standby state is set. When it is done, a state setting circuit is provided that is set to the non-operation state when the block data being input is finished at that setting timing.
When the state setting circuit is set to the continuous operation state, the block data is stored in the storage circuit in the updated state, and when the state setting circuit is set to the non-operation state, the subsequent storage operation is prohibited. A control circuit is provided.

In this case, the state setting circuit may be configured to set the end standby state when the input of the next block data is completed when the start standby state is set in the non-operating state.

[0012]

In the block data storing method according to the first aspect of the present invention, when the continuous operation is instructed, the block data continuously input are stored in the updated state. When the end standby is instructed, the storage operation is prohibited when the storage of the block data being input is completed at the command timing. Therefore, when the end standby is commanded in the continuous operation command state, the block data storage ends when the input of the block data being input at that time ends, so the block standby data is stored after the end standby is commanded. The time to do can be shortened.

In the block data storing method according to the second aspect, when the start standby state is commanded from the non-operating state, the next block data is stored and then the non-operating state is entered, so that the latest data is stored. can do.

In the block data storage device according to the third aspect, when the continuous operation state is set in the state setting circuit, the control circuit stores the block data continuously input in the storage circuit in the updated state. Then, when the end standby state is set in the state setting circuit, the state setting circuit is set to the non-operation state when the block data being input ends at the timing when the end standby state is set. The control circuit prohibits the storage operation when the state setting circuit is set to the non-operating state. Therefore, when the state setting circuit is set to the continuous operation state and then the end standby state is set, the block data storage ends when the input of the block data being input at that point ends. It is possible to shorten the time from setting the end standby state to storing the block data.

In the block data storage device according to the fourth aspect, when the start standby state is set in the state setting circuit, the state setting circuit is set to the end standby state when the input of the next block data is completed. . Therefore, the latest data can be stored in the memory circuit.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment in which the present invention is applied to a frame image data storage device will be described below with reference to FIGS. FIG. 2 schematically shows the overall configuration. In FIG. 2, a television camera or C is connected to the signal input terminal 1.
A video signal is input from a CD camera (not shown), and the video signal is output to the A / D conversion circuit 2 and the image address generation circuit 3. The A / D conversion circuit 2 A / D converts the video signal from the signal input terminal 1 and outputs it as recording image data to the frame memory 5 as a storage circuit through the data switching circuit 4. The image address generating circuit 3 takes out a synchronizing signal component included in the video signal, generates a recording image address based on the synchronizing signal, and outputs it to the frame memory 5 through the address switching circuit 6. The image address generation circuit 3 also generates a frame start signal FSTART and a frame end signal FEND based on the input video signal and outputs it to the state setting circuit 7.

The state setting circuit 7 has a register SR, which is stored in the register SR on the basis of an address signal input to the address signal terminal 8 from an external device (not shown) and a data signal input to the data signal terminal 9. A predetermined numerical value is set, and the frame start signal FSTART and the frame end signal FE from the image address generation circuit 3 are set.
The numerical value of the register SR is changed based on ND. Then, the state setting circuit 7 outputs the numerical value set in the register SR to the control circuit 10 as a state signal.

The control circuit 10 outputs an address switching signal to the address switching circuit 6 and a data switching signal to the data switching circuit 4 on the basis of the status signal from the status setting circuit 7 and the read address to control the frame memory. The signal is output to the frame memory 5.

The data switching circuit 4 is the A / D conversion circuit 2
In addition, it is connected to the data signal terminal 9 and selectively connects the A / D conversion circuit 2 or the data signal terminal 9 to the data terminal of the frame memory 5 in accordance with the switching by the data switching signal from the control circuit 10. . Further, the address switching circuit 6 is connected to an address signal terminal 8 in addition to the image address generating circuit 3, and selects the image address generating circuit 3 or the address signal terminal 8 in accordance with switching by an address switching signal from the control circuit 10. Frame memory 5
Connect to the address terminal of. And the frame memory 5
Is set to each writable or readable state by a frame memory control signal from the control circuit 10.

Here, the state setting circuit 7 has a register S.
It has R, and the state is set based on the numerical value set in the register SR. Figure 1
The relationship between the numerical value set in the register SR of the state setting circuit 7 and the state transition of the state setting circuit 7 according to the numerical value is shown. In FIG. 1, the state setting circuit 7 is normally set to the non-operation state shown by S00. The non-operating state is a recording prohibited state in which the start of recording is not instructed.

When "10" is set in the register SR for starting recording in the non-operating state, the state shifts to the start standby state shown in S10. In this start standby state, the FSTART signal indicating the start of one frame in the image data forming the video signal is active "0".
When the FSTART signal is input, the process waits until the state becomes, and the state transits to the end waiting state shown in S01.
The end standby state is FEN indicating the end of image data.
By waiting until the D signal becomes active "0", when the FEND signal is input, the non-operating state shown in S00 is entered.

On the other hand, the state setting circuit 7 transits to the continuous operation state shown in S11 when "11" is set in the register SR in the non-operation state shown in S00. The continuous operation state is to instruct the control circuit 10 to store one frame of continuously input image data in the frame memory 5 in an updated state. When "01" is set in the register SR to start recording from the continuous operation state, the state is changed to the end standby state shown in S01.

Here, the operation of the state setting circuit 7 will be specifically described. That is, in the state shown by S00 in FIG. 1, "00" is output from the state setting circuit 7. At this time, the control circuit 10 switches the address switching signal so that the address switching circuit 6 selects the address signal terminal 8 and switches the data switching signal so that the data switching circuit 4 selects the data signal terminal 9. ,
Further, the frame memory control signal is set to read. Therefore, the external device can access the frame memory 5.

When the image data forming the video signal is stored in the frame memory 5 by the normal processing operation, "10" is set in the state setting circuit 7. Then, since the output from the state setting circuit 7 changes from "00" to "10", the control circuit 10 determines that the recording is instructed. Then, when the first data of one frame in the image data is input, the frame start signal FSTART is output from the image address generation circuit 3, so that “01” is set in the register SR of the state setting circuit 7. As a result, since "01" is output from the state setting circuit 7, the control circuit 10 switches the address switching circuit 6 to input the image image address from the image address generating circuit 3 in response to the address switching signal. , The data switching circuit 4 switches to input the recording image data from the A / D conversion circuit 2, and the frame memory control signal is set to write. By the above operation, one frame of image data is stored in the frame memory 5.

When the input of one frame of the image data is completed, the image address generation circuit 3 outputs the frame end signal FEND, so that the register SR
Is set to "00". As a result, the control circuit 10
Ends the recording operation by switching the output signal.

By the way, when executing the shortening processing operation which finishes the recording operation in a shorter time than the above-mentioned normal processing operation, "11" is set in the register SR of the state setting circuit 7 (see FIG. 1). Then, since the state setting circuit 7 outputs "11" as the state signal, the control circuit 10
The address switching circuit 6 is switched to input the recording image address from the image address generating circuit 3, and the data switching circuit 4 selects the recording image data from the A / D conversion circuit 2 as a data switching signal. Write and set the frame memory control signal. By the above operation, one frame in the image data forming the video signal is stored in the frame memory 5 in the updated state.

Then, in the continuous operation state, when "01" is set in the register SR to start recording (see FIG. 1), the state setting circuit 7 transits to the end standby state shown in S01. When the frame end signal FEND is input in this state, the state setting circuit 7 transits to the non-operation state shown in S00. By the above operation, the frame memory 5 stores one frame of the image data being input at the timing of instructing the end standby state.

FIG. 3 shows the operation timing as described above. From FIG. 3, when the state setting circuit 7 is set to the state shown in S11 in advance, the time Tr from the instruction to end the recording to the end of the recording is Tr = Te−Tc, and Tr is The shortest time is when the recording end is instructed immediately before the output of the frame end signal FEND indicating the end of one frame in the image data, as shown in FIG. 4, and Tr is substantially zero. Further, Tr becomes the longest time when the instruction is given immediately after the output of the frame start signal FSTART indicating the start of one frame in the image data, as shown in FIG. 5, and Tr becomes substantially Te-Ts. Therefore, the possible value of Tr is 0 <Tr <(Te-Ts) (1).

Here, the time Tr from the issuance of the recording instruction at the above-mentioned normal processing speed to the end of the recording Tr
From FIG. 8, Tr = Te-Tc = (Te-Ts) + (Ts-Tc). In this case, since 0 <(Ts-Tc) <(Te-Ts), the possible value of Tr is (Te-Ts) <Tr <2 · (Te-Ts) (2).

Therefore, by comparing the above equations (1) and (2), the recording time shortening processing operation can be shortened to half the processing time on average as compared with the processing time in the normal processing operation. . Specifically, the video signal is NTS
In the case of the C method, the normal processing operation is 60 to 120 msec.
What was required is that the shortening processing operation can be shortened to 0 to 60 msec.

In short, according to the above configuration, when the recording processing time is shortened, one frame of image data that is continuously input is stored in the frame memory 5 in an updated state and the end standby state is set. Since the storage operation is ended when the storage of one frame of the image data stored at the timing is completed, unlike the conventional example in which the frame image data to be input after issuing the recording command is stored, It is possible to shorten the recording operation.

FIG. 6 shows a second embodiment in which the present invention is applied to a configuration for measuring image frame data such as histogram processing. The same parts as those in the first embodiment are designated by the same reference numerals and their description is omitted. To do. In FIG. 6, the image data input by the video signal is input to the data measuring means 10 as image data via the A / D conversion circuit 2. The video signal is input to the frame signal generation circuit 11, and the frame start signal FSTA is generated by the synchronization signal component of the video signal.
It outputs RT and a frame end signal FEND. The state setting circuit 7 operates similarly to the first embodiment. Further, the data measuring means 10 controls the storage operation of the image data by the status signal from the status setting circuit 7.

According to the second embodiment, the state setting circuit 7
Since the grayscale data of the image data can be stored in the data measuring means 10 in accordance with the setting state of, the processing time from the storage start command to the storage of the image data is the same as in the first embodiment. It can be shortened.

[0034]

As is clear from the above description, the block data storage method and apparatus of the present invention have the following effects. According to the block data storage method of claim 1, when the end standby is commanded in the continuous operation command state, the block data storage ends when the input of the block data being input at that time ends.
It is possible to shorten the time from the end standby command until the block data is stored.

According to the block data storing method of the second aspect, when the start standby state is commanded from the non-operating state, the next block data is stored and then the non-operating state is entered, so that the latest data is stored. Can be memorized.

According to the block data storage device of the third aspect, the states are sequentially set from the non-operating state to the continuous operating state and the end standby state, and when the end standby state is set, the set timing is set. A state setting circuit is provided that is set to a non-operating state when the block data being input is completed, and when the state setting circuit is set to the continuous operating state, the block data is stored in the storage circuit in an updated state. At the same time, when the state setting circuit is set to the non-operating state, a control circuit for prohibiting the subsequent storage operation is provided. Therefore, after the end standby state is set in the state setting circuit until the block data is stored. The time can be shortened.

According to the block data storage device of the fourth aspect, when the start standby state is set in the non-operating state, the state setting circuit is set to the end standby state when the input of the next block data is completed. Since it was configured as
The latest data can be stored in the memory circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing state transitions in a first embodiment of the present invention.

FIG. 2 is a schematic diagram of the whole.

FIG. 3 is a timing chart showing a recording operation.

FIG. 4 is a timing chart showing the shortest recording time.

FIG. 5 is a timing chart showing the longest recording time.

FIG. 6 is a view corresponding to FIG. 2 showing a second embodiment of the present invention.

FIG. 7 is a view corresponding to FIG. 1 showing a conventional example.

FIG. 8 is a view corresponding to FIG.

FIG. 9 is a view corresponding to FIG.

FIG. 10 is a view corresponding to FIG.

[Explanation of Codes] 5 is a frame memory (memory circuit), 7 is a state setting circuit,
Reference numeral 10 is a control circuit.

Claims (4)

[Claims] 1. A block data storage method for storing block data that is continuously input at a predetermined timing. When a continuous operation is instructed from a non-operation state in which block data storage is prohibited, the block data is updated. A block data storing method characterized in that, when the end standby is instructed, the block data is stored and the inactive state is entered at the end of the storage of the block data being input. 2. The block data storage method according to claim 1, wherein when a start standby command is issued from the non-operating state, the block data to be input next is stored and then the non-operating state is entered. 3. A block data storage device for storing successively input block data in a storage circuit at a predetermined timing, the block data storage device being provided so as to be sequentially set from a non-operating state to a continuous operating state and an end standby state. When the above end standby state is set, the state setting circuit that is set to the non-operation state when the block data being input is finished at that setting timing, and when this state setting circuit is set to the continuous operation state Block data storage, characterized in that the block data is stored in the storage circuit in an updated state, and a control circuit for prohibiting a subsequent storage operation when the state setting circuit is set to a non-operating state. apparatus. 4. The state setting circuit is configured to be set to an end standby state when the input of the next block data is completed when the start standby state is set in the non-operating state. The block data storage device according to claim 3.