JPH06347484A - Random sampling memory circuit - Google Patents

Abstract

PURPOSE:To renew the wave form data in a random sampling rapidly by reforming a data pickup means, because there are disadvantages to take too much time until the trigger permission is given, and to take too much time to renew the wave form, in a digital oscilloscope. CONSTITUTION:A RAM 8 which consists of a serial access memory 4, and a dynamic RAM 5 which can set the address from a low address and a column address is used as a memory, a processed data of an A/D 1 is stored at first in the serial access memory 4, and when the storage is finished, the data is to be transferred to the dynamic RAM 5, next.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a data acquisition / storage circuit in a random sampling type digital oscilloscope.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to FIGS. 2, 3, 4, and 5. When the observed signal is sampled and stored with a sample clock that is slower than the period of the observed signal and this waveform is displayed, the sample time and the data of the observed signal (time difference between the trigger point and the sample clock) is held by some method. I have to keep it. As one of the methods, there is a random sampling method.

In the random sampling method, the sample clock and the trigger are asynchronous. Therefore, when the waveform data is taken into the memory, the time from the point where the input signal passes the trigger level to the next sample clock is measured. Similarly, in the case of an input signal sampled by the next sample clock, the time difference is similarly measured, and the input waveform is stored and displayed by superimposing data of several waveforms with the trigger point as a reference. About the operation when doing this random sample,
This will be described with reference to FIGS. 3, 4, and 5. FIG. 3 shows a storage state of data divided into blocks, and FIG. 4 shows an observation signal A and a reproduced waveform point B. FIG. 5 shows the time relationship between the trigger signal and the sample clock. In FIG. 3, the data processed from analog to digital by the A / D converter is A
The data is divided into blocks according to the time length Δtn of the trigger and the sample clock as in the time sequence 8 of the / D data, and the data sampled at the constant period ts (see FIG. 5) is the block 3, the block 2, and the block 4. , Block 1, and so on. If this data is rearranged 9 and read out as shown by the arrow,
Data reproduction of the observation signal is performed as shown in. Now, in order to execute the above-mentioned operation, in the conventional technique, as shown in FIG.
As shown in, the data first processed from analog to digital by the A / D converter 1, for example, the data block 3 is
It is stored in the static RAM 6. Next, as for the data stored in the static RAM 6, the first data 3-1 is read by the μ controller 2, the address (start address calculation) for the time length Δt _{3 of} the trigger and the sample clock is skipped, and the static RAM 7 Written in.
Next, the data 3-2 is read out, the address (skipping address operation) for a fixed period ts of the sample clock is skipped, and is written in the static RAM 7, and this operation is repeated one after another. The end of the data is static RA
Only after being written to M7, the next trigger is allowed,
The data of block 2 is taken in, and similarly, block 4 and block 1 are continued. The data of the static RAM B7 is transferred to the I / O port in the reading order of the arrow.

[0004]

As described above, since the entire address management for the data address rearrangement such as the calculation of the start address of the acquired data and the calculation of the skipped address is performed by the μ-con processing, in the above-mentioned conventional technique, the trigger There is a drawback that it takes a long time to authorize and the update of the displayed waveform becomes slow. An object of the present invention is to improve the data acquisition means and speed up the waveform data update at random sampling.

[0005]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a serial access memory unit and a dynamic RAM (eg, a row address and a column address) which can be set after the A / D converter. Video RA
A RAM composed of the M) section is connected.

[0006]

With this connection, the A / D converted data is first stored in the serial access memory unit, and then the data is transferred from the serial access memory unit to the dynamic RAM unit. As a result, the data is collectively transferred from the serial access memory unit to the dynamic RAM unit without rearrangement, and it takes no time to update the data.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. The output of the A / D converter 1 is a RAM composed of a serial access memory unit 4 and a dynamic RAM unit 5.
8 is connected to the data input section of the serial access memory section 4, and the control input of the RAM 8 is connected to AB, RD, and WR of the μ controller 2. The output of the dynamic RAM section 5 is connected to the I / O port.
Data block 3 digitally processed by the A / D converter 1
Is a serial access memory unit 4 and a dynamic RA
The serial access memory unit 4 of the RAM 3 including the M unit 5 sequentially stores 3-1, 3-2, ..., 3-n. After the storage in the serial access memory unit 4 is completed, the stored data is designated by the μ controller 2 to specify the row address 3 of the dynamic RAM unit 5.
N pieces of 1-byte data from -1 to 3-n are stored in the dynamic RAM unit 5 once. Then the next trigger is allowed and the data in block 2 is acquired. Similar to block 3, when block 2 is completed, block 4 and block 1 are continued. Reading to the I / O port
By changing the address as shown by the arrow, waveform reproduction by random sample can be executed.

[0008]

According to the present invention, since the address management is simplified even in the random sampling method, the data update time is shortened, the display screen looks like real time, and a high-quality digital oscilloscope can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a block diagram showing a conventional configuration.

FIG. 3 is a block diagram illustrating a storage state of data at random sampling.

FIG. 4 is an explanatory diagram showing a relationship between an observed waveform and a reproduced waveform.

FIG. 5 is a waveform diagram showing a relationship between a sample clock and a trigger signal.

[Explanation of symbols]

 1 A / D 2 μ controller 4 Serial access memory 5 Dynamic RAM 6 Static RAMA 7 Static RAMB 8 RAM

Claims (1)

[Claims] 1. A RAM unit comprising an A / D converter, a serial access memory unit at a subsequent stage of the A / D converter, a dynamic RAM unit capable of address setting from a row address and a column address, and the inside of the RAM unit. A random sampling storage circuit capable of batch transfer, which is composed of a serial access memory unit and a microcomputer controlling the dynamic RAM unit.