JP3267393B2 - Random sampling storage circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a data acquisition and storage circuit in a digital oscilloscope of a random sampling system.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to FIGS. 2, 3, 4 and 5. FIG. When the observed signal is sampled and stored with a sample clock that is slower than the observed signal period, and this waveform is displayed, the sample time and the observed signal data (the time difference between the trigger point and the sample clock) are held in some way. Must be kept. One of the methods is a random sampling method.

In the random sampling method, a sample clock and a trigger are asynchronous. Therefore, when the waveform data is taken into the memory, the time from the point at which the input signal has passed the trigger level to the next sample clock is measured. Similarly, in the case of an input signal sampled at the next sample clock, the time difference is similarly measured, and the input waveform is stored and displayed by overlaying some waveform data on the basis of the trigger point. Regarding the operation when performing this random sample,
This will be described with reference to FIGS. 3, 4, and 5. FIG. 3 shows the storage state of the divided data, and FIG. 4 shows the observation signal A and the reproduced waveform point B. FIG. 5 shows the time relationship between the trigger signal and the sample clock. In FIG. 3, data processed from analog to digital by the A / D converter is A / D converter.
/ D is divided into blocks according to the time length Δtn of the trigger and the sample clock as shown in the time sequence 8 of the data, and the data sampled at a constant period ts (see FIG. 5) is represented by blocks 3, 2, and 4. , Block 1, etc., are taken in randomly. The data is rearranged 9 and read out as indicated by the arrow.
The data reproduction of the observation signal is performed as shown in FIG. Now, in order to execute the above-described operation, in the related art, FIG.
As shown in FIG. 1, data that is first processed from analog to digital by the A / D converter 1, for example, the data block 3,
It is stored in the static RAM 6. Next, from the data stored in the static RAM 6, the data 3-1 is first read out by the microcomputer 2, skipping the address (start address calculation) of the time length Δt _{3 of} the trigger and the sample clock, and skipping the static RAM 7 Is written to.
Next, the data 3-2 is read out, the address (skip address calculation) for the fixed period ts of the sample clock is skipped, and the data is written into the static RAM 7, and this operation is repeated one after another. The end of the data is the static RA
Only after being written to M7, the next trigger is allowed,
The data of block 2 is fetched, and so on with block 4 and block 1. The data in the static RAMB 7 is transferred to the I / O port in the reading order of the arrow.

[0004]

As described above, the entire address management for rearranging data such as the start address calculation of acquired data and the skip address calculation is performed by the μ-con process. There is a drawback in that it takes time until the permission is given, and the update of the display waveform is delayed. SUMMARY OF THE INVENTION It is an object of the present invention to improve data acquisition means and to speed up updating of waveform data at the time of random sampling.

[0005]

In order to achieve the above object, the present invention provides a serial access memory unit, a dynamic RAM (for example, a dynamic RAM capable of setting an address from a row address and a column address) after an A / D converter. Video RA
M) is connected to a RAM composed of sections.

[0006]

With this connection, A / D conversion is performed first.
Digital data is stored in the serial access memory,
Next, from the serial access memory section to the dynamic RAM
The digital data is transferred to the unit.
As a result, the digital data is transferred from the serial access memory unit to the dynamic RAM unit at once without rearrangement, so that it takes no time to update the data.

[0007]

An embodiment of the present invention will be described below with reference to FIG. The digital data output from the A / D converter 1 is
Serial access memory unit 4 and dynamic RAM unit 5
Serial access memory section 4 of RAM 8 composed of
The control input of the RAM 8 is connected to AB, RD, WR of the μ-con 2. The output of the dynamic RAM unit 5 is connected to an I / O port. Digitally processed by the A / D converter 1 and at the time of trigger and sample clock as shown in the time sequence 8.
Divided into blocks according to the time order according to the length Δtn
The data block 3 obtained is a RAM 8 composed of a serial access memory unit 4 and a dynamic RAM unit 5.
, 3-2,.
.., 3-n are sequentially stored. When the data is stored in the serial access memory unit 4 and the row address 3 of the dynamic RAM unit 5 is designated by the microcomputer 2 with the stored data, n pieces of 1-byte data from 3-1 to 3-n Is stored in the dynamic RAM unit 5 at one time. Subsequently, the next trigger is permitted, and the data of block 2 is captured. As with block 3, if block 2 ends, block 4 and block 1 are continued. I / O
Reading from the port, if Yuke instead sequential column address <br/> scan as shown by the arrow, waveform reproduction by random samples can be performed.

[0008]

According to the present invention, since the address management is simplified even in the random sampling method, the data update time is shortened, the display screen becomes real-time sense, and a high-quality digital oscilloscope can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a block diagram showing a conventional configuration.

FIG. 3 is a block diagram illustrating a data storage state at the time of random sampling.

FIG. 4 is an explanatory diagram showing a relationship between an observed waveform and a reproduced waveform.

FIG. 5 is a waveform chart showing a relationship between a sample clock and a trigger signal.

[Explanation of symbols]

 1 A / D 2 μcon 4 Serial access memory 5 Dynamic RAM 6 Static RAMA 7 Static RAMB 8 RAM

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G01R 13/00-13/42 G06F 3/05 311 G06F 15/78 510

Claims (1)

(57) [Claims] An analog data is inputted and a digital data is inputted.
An A / D converter for converting and outputting the converted data;
Digital data that stores digital data sequentially for each block.
Access memory section and the stored data for each block.
The row address according to the time order of the block.
And a dynamic RAM unit for storing data in a fixed manner.
The data stored in the dynamic RAM unit is stored in the dynamic RAM unit.
Read from / to RAM by changing column address sequentially
A random sampling storage circuit.