JPS6355586A - Graphic display device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention erases the contents of the frame memory in the display mode at the same time as it is read using the read/write function of the memory during the display period for the last one screen. By doing so, mode switching is made faster.

[Industrial application field]

The present invention relates to a Tarafink display device, and more particularly to an improvement in a frame memory control method for improving the followability of a graph ink cursor.

[Conventional technology]

The graphic cursor must follow at high speed the movements of the pick device that specify various elements in the display screen.

That is, when modifying, deleting, etc. various elements displayed on the display screen, the elements are designated with a pick device. At that time, the graphic cursor follows the pick device's instructions and moves onto the specified element, but in the double buffer method, which uses two frame memories to store image data to be displayed, the graphic ink cursor moves to the specified element. The following speed could not necessarily be said to be fast.

In the conventional double buffer method, as shown in Figure 4, one frame memory (for example, 2°
While displaying the image data stored in the frame memory (in this case, 2 in the figure) on the display device 5 via the video signal generation circuit 4 (display mode) Image data is written from the graphic processing unit 1 to the image data (write mode).

When data writing to the frame memory 2 is completed, the modes of the two frame memories 2 and 2 are reversed, and
The contents of the frame memory 2 are displayed, and data is written to the frame memory 2 during that time.

In this way, the data of the two frame memories 2.2' is constantly updated by alternately repeating the state in which one is in the write mode and the other in the display mode.

In this operation, conventionally, when the frame memory enters the write mode, as shown in FIG. Generation circuit 7 is buffer list 6
The image data (data such as figures) generated by analyzing the contents of is written to the frame memory [period indicated by "W" in the same figure], and when that is finished, the flyback period of the raster on the display side is used. Then, the modes of the two frame memories are reversed. By repeating the above operation, new image data is processed one after another.

In this process, the cursor position information specified by the pick device 8 is taken into the figure generation circuit 7 via the pick device control circuit 9, and based on this, image data for displaying the cursor at the above position is generated. generated and stored in frame memory in write mode. This frame memory is then set to the display mode [“R” in the same figure.
When the period indicated by ' is reached, the cursor will be displayed at the position specified above.

[Problem that the invention seeks to solve]

To move the cursor in this way, it is necessary to switch the frame memory mode, but as mentioned above, first erase the memory contents in the write mode, and then write the image data to the memory. Therefore, the write cycles were “E” and “W” mentioned above.
Therefore, even if the amount of image data to be written is small, the write cycle will require a longer time than the time required for erasing, and it is not possible to shorten the write cycle. I can't do it,
The cursor tracking speed could not be increased to a satisfactory level.

SUMMARY OF THE INVENTION An object of the present invention is to provide a graph ink display device capable of increasing the following speed of the graphic cursor.

[Means for solving problems]

The present invention provides a graphic display device with a display period corresponding to one screen immediately before a mode switching operation is performed.
By providing an erase control means that reads the contents of the frame memory in the display mode at that time and erases that portion, the contents of the frame memory can be erased during the display period for the last one screen in the display mode. In write mode, only image data is written.

[For production]

The time required to erase the contents of the frame memory is constant, and by performing this during display mode, in write mode, all that is required is the net time required to write the image data, and therefore the write cycle is reduced. The graphics cursor tracking speed is reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a detailed explanatory diagram of the present invention. In the same figure,
1 is a graphic processing unit, which includes a buffer list 6 and a graphic generation circuit 7.
Consists of. The image data generated by the figure generation circuit 7 by analyzing the buffer list 6 is stored in one of the two frame memories 2, 2 (for example, this is referred to as 2 in the figure).
will be written to. On the other hand, the display device (the same figure shows C as an example)
RT) 5 through the video signal generation circuit 4,
Of the two frame memories 2 and 2°, the contents of the display mode memory (2° in this case) are transferred and displayed. Furthermore, information indicating the position specified on the CRTS by the pickup device 8 is taken into the graphic generation circuit 7. The configuration up to this point is unchanged from the previous version.

In this embodiment, in addition to the above configuration, an erase control means 3 is provided. An example of this configuration is shown in FIG.

As seen in the figure, the erase control means 3
and Write ilJ control circuit [hereinafter simply R/
[abbreviated as W control circuit] 11, and a timer 12. and a memory selection circuit 13.

Note that while the cursor is moving, the displayed content remains constant, so during the operations described below, the data written to the frame memories 2 and 2'' will differ only in the position of the cursor, and the amount of data will vary. Therefore, the time required to write data [W in Figure 3] is constant,
Furthermore, the time required to erase the contents of the frame memories 2, 2' (E in FIG. 3) is also constant.

FIG. 3(a) to TCI are timing diagrams showing the operation of the erase control means 3 configured as described above, and are timing charts showing the operation of the frame memory 2, 2° immediately after the image data to be displayed changes.
The amount of data written in the frame memory 2, 2' is divided into three types, and the operation timing of each frame memory 2, 2' is shown below.

From time t0 shown in the figure, two frame memories 2.2
Assume that the amount of data written to ′ is different from the previous one. In this case, the memory selection circuit 13 first specifies the memory into which data is to be written. The figure shows a state in which the frame memory 2 is designated to write mode and the frame memory 2' is designated to display mode at time *II to.

Memory designation (No. 8) output from the memory selection circuit 13 sets the timer 12 and is input to the R/W control circuit 11.

Upon receiving this signal, the R/W control circuit 11 sets the frame memories 2 and 2° to the write mode and display mode, respectively. In the first cycle starting from time t0, the R/W control circuit 11 writes erase data to all addresses of the frame memory 2 before writing data from the graphic processing unit 1 to the frame memory 2 set to the write mode. The contents will be deleted. This operation is executed by outputting erase data to the frame memory 2 while sequentially specifying addresses of the frame memory 2 using the address designation signal A. The above processing is an erasing operation indicated by E from time t0 to tl, and the time Z''L+-to required for this is constant as described above.

When erasing the contents of the frame memory 2 is completed, the R/W control circuit 11 causes the graphic processing section 1 to write data into the frame memory 2. The hit time X, indicated by W in the figure, is 1. -1. It is.

The time X required for this writing is determined by setting the writing start and end times t and t2 in the timer 12 to the R/W control circuit 1.
By notifying from 1, it is automatically detected and set by the timer 12, and used for subsequent operations.

During the above operation, ie, from time t0 to time t2, the frame memory 2' remains in the display mode and does not change.

Upon receiving a notification from the graphic processing unit l that writing to the frame memory 2 has been completed, the memory selection circuit 13 selects a time t.
At step 2, a signal is output which designates the modes of the two frame memories 2 and 2 to display and write, respectively.

Upon receiving this designation, the R/W control circuit 11 performs the same operation as described above to erase data from the frame memory 2" [E between t! and t in the figure], and then the graphic processing section 1 [W between t and t in the figure] is executed.

Time required for erasing and writing to the frame memory 2° 1. -1. is the same as the data written to the frame memory 2 described above, so the amount of data is also the same, and therefore equal to the time X required for the first erasing and writing to the frame memory 2.

During this time, the operation of the frame memory 2 in the display mode is performed as follows.

When the frame memory 2 is set to the display mode at time t2, the address designation signal A sent out by the video signal generation circuit 4 is input to this frame memory 2 via the R/W control circuit 11, and the address designation signal A sent out from the video signal generation circuit 4 is input to the frame memory 2 via the R/W control circuit 11, and the address designation signal A sent out from the video signal generation circuit 4 is input to the frame memory 2 through the R/W control circuit 11. A signal indicating data stored in the video signal generating circuit 4 is sent to the display device 5 via the video signal generating circuit 4 and displayed.

At the same time, the timer 12 starts to measure time from the above time t2, and when the above-mentioned time X has elapsed, the R/
As is clear from the figure, the time from 0 time t4 to t, which is notified to the W control circuit 11 [time t4 in the figure], is as follows.
The time t, -'t, minus the time X, that is, the time required for erasure indicated by E, 2 = 1. -1. This is also equal to the time required to display the entire contents of the frame memory 2, that is, one screen of the display device 5.

Therefore, while displaying one screen starting from time t4,
After reading the contents of the specified address of the frame memory 2, the contents of that address are erased.

This operation can be performed using a mode called read-write mode or read-modify-write mode. This is the row address (Raw) for the frame memory.
) and digit address (Column
This can be carried out by specifying an address (Address), reading the data at that address, and then writing erase data to the same address at the fall of the signal {circle around (2)} which makes this frame memory ready for writing.

Therefore, during the period from t4 to t (period indicated by R/E in the same figure), after reading the data from the frame memory 2, erase data is written to the same address.

This operation is performed by outputting erase data from the R/W control circuit 11.

As described above, the contents of the frame memory 2 are all erased while displaying the last one screen in the display mode from t2 to t.

Time 1. When writing to the frame memory 2' is completed, the memory selection circuit 13 specifies the write mode and the display mode for the frame memories 2 and 2, respectively. At this point, the contents of frame memory 2 for which write mode has been specified have already been erased, so
Writing begins immediately.

On the other hand, the contents of frame memory 2° are read out and displayed, but at this time the time required for writing, X, and the time, Z, required for erasing are compared, and in this case, as mentioned above, Therefore, the difference Y=X-Z is set in the timer 12. The timer 12 starts timing operation at time t. The contents of the frame memory 2° are read out from time t and displayed on the display device 5, but when the above-mentioned time Z passes and reaches time t, from then on, as described above,
Erasing data is written to erase the contents, and erasing is performed at the same time as reading.

In this way, in this third cycle, the mode can be changed at the same time as writing of data to the frame memory 2 is completed. That is, the writing is completed in only a net writing time of X, and data erasing in the frame memory 2° is also completed during that time. Therefore, from now on, frame memory 2, 2
This state is repeated as long as there is no change in the amount of data written to the frame memory 2, and the switching period between the frame memories 2 and 2 degrees is shortened.

The amount of data to be written is smaller than the above case, and as a result of comparing the time X required for writing W and the time Z required for erasing, in the case of X=Z and in the case of X<Z, as shown in FIG.
b), set the above-mentioned time Y to 0, as seen in (C). In addition, as X, in the case of X-Z, the time required for writing is cents, and if X<Z, that is, the erasing time is longer, in the third and subsequent cycles, the time required for reading and erasing is Time (period indicated by R/- in the same figure)
(replace X with Z).

In this way, if X>Z does not hold, the two memories can be switched in the time it takes to read data for one screen.

As described above, in this embodiment, the cycle time for switching between the two memories can be shortened, and the graphic cursor can therefore follow faster.

〔Effect of the invention〕

As described above, according to the present invention, the cycle time for double buffer switching can be shortened, and as a result, the graph ink cursor is displayed at new positions one after another, resulting in faster tracking.

[Brief explanation of the drawing]

Fig. 1 is a detailed explanatory diagram of the present invention, Fig. 2 is an explanatory diagram of the configuration side of the erase control means, Fig. 3 is a timing diagram of an embodiment of the present invention, and Fig. 4 is an explanatory diagram of the main part configuration of a conventional example. , FIG. 5 is a timing diagram of a conventional example. In the figure, 1 is a graphic processing unit, 2.2 is a frame memory, 3 is an erase control means, 5 is a display device, 8 is a pick device, 11 is an R/W control circuit, 12 is a timer, 1
3 indicates a memory selection circuit. Detailed explanatory diagram of the present invention Fig. 1 Explanatory diagram of the erase control means configuration side Fig. 2 L6 tl i2 t2L4 15L
6 If LqL@LgX>Z, cl) If X■2, cl If X<Z Timing diagram of an embodiment of the present invention Fig. 3

Claims (1)

[Scope of Claims] A display device and two frame memories for storing image data corresponding to the screens of the display device are provided, and one of the two frame memories is in a write mode in which image data to be displayed is written. , the other frame memory is put into a display mode for displaying its contents on the display device, and after the writing to the one frame memory is completed, the second frame memory
In a frame memory control method that repeats the operation of reversing the mode of each frame memory, at the same time as the display of one screen immediately before the mode switching operation is started, the contents of the frame memory of the display mode at that time are A graphics display device configured to initiate erasure.