JPH0735817A - Integrated circuit - Google Patents

Abstract

PURPOSE:To realize a boundary scanning function without deteriorating housing property and increasing the chip area significant CONSTITUTION:An integrated circuit 1 is made up of an internal cell area 2, an I/O(input/output) and a buffer area 3. A shift operable flipflop is built into the I/O buffer area 3. The flipflop has signal lines 103-106 as connected to a scan data external input terminal 4, a hold control external input terminal 5, a scan control external input terminal 6, a scan clock external input terminal 7 and a scan data external output terminal 8 respectively. The shift operation of the flipflop is performed by a signal inputted or outputted via the signal lines 103-106.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit, and more particularly to a test facilitation technique using boundary scan in the integrated circuit.

[0002]

2. Description of the Related Art Conventionally, as a test facilitation technique of this kind, there is a technique for realizing a boundary scan function for improving observability between integrated circuits by forming a logic circuit in an internal cell region of the integrated circuit. .

Further, a flip-flop group forming a boundary scan is formed outside the chip area of the integrated circuit, and the boundary scan function is realized by connecting the flip-flop group and the input signal pad in the chip area with a lead wiring. There are also technologies that can be realized. This technique is described in detail in JP-A-2-229448.

[0004]

In the conventional test facilitation technique described above, in the case of a technique for realizing a boundary scan function by configuring a logic circuit in the internal cell area of an integrated circuit, the number of logic circuits in the internal cell area increases. Therefore, there is a drawback that the accommodation of the integrated circuit is deteriorated.

Further, in the case of the technique for realizing the boundary scan function by connecting the flip-flop group formed outside the chip area of the integrated circuit and the input signal pad within the chip area with the lead wiring, the flip-flop outside the chip area is used. Since a region for forming a group of chips is required, the chip area becomes large and the number of chips that can be formed on one wafer is reduced.

Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks and to provide an integrated circuit capable of realizing a boundary scan function without deteriorating the accommodation capacity and significantly increasing the chip area. is there.

[0007]

An integrated circuit according to the present invention is an integrated circuit including an input / output buffer area for transmitting and receiving a signal between an external terminal and an internal cell, wherein the state value of the external terminal is set. And a control signal line for controlling each of the plurality of holding means to perform a shift operation in the input / output buffer area.

[0008]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of an embodiment of the present invention.
In the figure, an integrated circuit 1 comprises an internal cell area 2 and an I / O (input / output) buffer area 3. This I /
The O-buffer area 3 has a built-in flip-flop (not shown) capable of shifting.

A signal line 103 connected to the scan data external input terminal 4, the hold control external input terminal 5, the scan control external input terminal 6, the scan clock external input terminal 7 and the scan data external output terminal 8 is connected to the flip-flop. To 106 are connected, and the signal line 103
The shift operation of the flip-flop is performed by the signal input / output via ~ 106.

FIG. 2 is a diagram showing an input buffer forming the I / O buffer area 3 of FIG. In the figure, a buffer 12 and a flip-flop (hereinafter referred to as F / F) 13 are arranged in the input buffer 11.

The data signal 101 from the data input terminal 21 is input to the buffer 12, and the buffer signal 102 is input from the buffer 12 to the data terminal (D) of the F / F 13.
ATA) and the data output terminal 26. This data signal is taken into the internal cell region 2 from the data output terminal 26.

The scan data signal sent through the signal line 103 connected to the scan data external input terminal 4 of the integrated circuit 1 is input to the scan-in terminal (SIN) of the F / F 13 through the scan-data input terminal 22. It

External input terminal 5 for hold control of integrated circuit 1
The hold control signal sent through the signal line 106 connected to the
13 is input to the hold control terminal (SDH) and the hold control output terminal 30. Also, the hold control signal is output from the hold output terminal 30 to the input buffer of the next stage.

Scan control external input terminal 6 of integrated circuit 1
The scan control signal sent through the signal line 105 connected to the
It is input to the scan control terminal (SMC) 13 and the scan control output terminal 29. The scan control signal is output from the scan control output terminal 29 to the input buffer of the next stage.

The scan clock signal sent through the signal line 104 connected to the scan clock external input terminal 7 of the integrated circuit 1 passes through the scan clock input terminal 23 and the scan clock terminal (SCK) of the F / F 13 and the scan clock signal. It is input to the output terminal 28. Also,
The scan clock signal is the scan clock output terminal 28.
Is output from the next stage to the input buffer.

The flip-flop output signal 107 output from the output terminal (Q) of the F / F 13 is output to the scan data output terminal 27. Scan data output terminal 27
The scan data signal output from is sent to the input buffer of the next stage or the scan data external output terminal 8.

A plurality of the above-mentioned input buffers 11 are arranged in the I / O buffer area 3, and each input buffer 1
One F / F 13 is connected to each other via signal lines 103 to 106.

FIG. 3 is a diagram showing a boundary scan operation in one embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.

When a rising signal is applied to the scan clock external input terminal 7 of the integrated circuit 1, the scan clock input terminal 23 of the input buffer 11 in the I / O buffer area 3 is supplied.
The rising signal is propagated to.

At this time, if the scan control signal input to the scan control external input terminal 6 is "1", "1" is propagated to the scan control input terminal 24 of the input buffer 11.

As a result, each of the input buffers 11-1 to 11-1
The F / Fs 13-1 to 13-N of the 11-N perform the scanning operation, and the values held by the F / Fs 13-1 to 13-N are output to the next stage. This scan operation causes F / F13-
The values held by each of 1 to 13-N are shifted for each scan clock and output from the scan data external output terminal 8 to the outside.

Further, when the scan control signal to the scan control external input terminal 6 is "0" and the hold control signal to the hold control external input terminal 5 is "0" in the rising state of the scan clock signal described above. , The data signal 1 input from the data input terminal 21 of the input buffer 11
01 is input to the F / F 13 via the buffer 12.
By this data input operation, the state value of each external terminal at that time can be held in the F / F 13.

Further, in the rising state of the scan clock signal described above, the scan control signal to the scan control external input terminal 6 is "0" and the hold control external input terminal 5 is
If the hold control signal to the F / F13 is "1", the F / F13
Holds the input data. By this hold operation, data can be held in the F / F 13 regardless of changes in the state value of each external terminal.

Although the input buffer 11 of the I / O buffer area 3 has been described above, it is obvious that the present invention is also applicable to the output buffer arranged in the I / O buffer area 3.
Further, the F / F 13 is provided only in the input / output buffer corresponding to the external terminal (signal) to be tested of the integrated circuit 1, and the other input / output buffers pass the signal for the shift operation of the F / F 13. It is also possible to do so.

As described above, each input buffer 11 arranged in the I / O buffer area 3 of the integrated circuit 1 has a built-in F / F 13 capable of shift operation, and a scan clock signal for the shift operation of this F / F 13. By connecting the scan control signal, the hold control signal, and the scan data signal to the I / O buffer region 3, the boundary scan can be performed without deteriorating the accommodation capacity of the integrated circuit 1 and significantly increasing the chip area. It becomes possible to realize the function.

[0027]

As described above, according to the present invention, the state value of the external terminal is held in the input / output buffer area of the integrated circuit for exchanging signals between the external terminal and the internal cell. By providing a plurality of holding means connected to each other and a control signal line for controlling each of the plurality of holding means to perform a shift operation, the chip area can be significantly increased without deteriorating the accommodation property. There is an effect that the boundary scan function can be realized without increasing the number.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of the present invention.

FIG. 2 is a diagram showing an input buffer forming the I / O buffer area of FIG.

FIG. 3 is a diagram showing a boundary scan operation according to an embodiment of the present invention.

[Explanation of symbols]

 1 integrated circuit 2 internal cell area 3 I / O buffer area 4 scan data external input terminal 5 hold control external input terminal 6 scan control external input terminal 7 scan clock external input terminal 8 scan data external output terminal 11 input buffer 12 buffer 13 flip-flop The

Claims (1)

[Claims] 1. An integrated circuit including an input / output buffer area for transmitting / receiving a signal between an external terminal and an internal cell, the integrated circuit holding a state value of the external terminal and subordinately connected to each other. An integrated circuit having holding means and a control signal line for controlling each of the plurality of holding means to perform a shift operation in the input / output buffer area.