JPH073431A - Production of thin ferroelectric film - Google Patents
Production of thin ferroelectric filmInfo
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- JPH073431A JPH073431A JP17362693A JP17362693A JPH073431A JP H073431 A JPH073431 A JP H073431A JP 17362693 A JP17362693 A JP 17362693A JP 17362693 A JP17362693 A JP 17362693A JP H073431 A JPH073431 A JP H073431A
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- thin film
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- ferroelectric
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- Formation Of Insulating Films (AREA)
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- Physical Vapour Deposition (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は強誘電体薄膜を作製する
方法に関し、特にＰｂ1（ＺｒxＴｉ1-x）Ｏ3あるいは
（Ｐｂ1-yＬａy）（ＺｒxＴｉ1-x）Ｏ3で表される強誘
電体（以下、前者をＰＺＴ、後者をＰＬＺＴと略す。）
の薄膜を作製する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a ferroelectric thin film, and more particularly to Pb 1 (Zr x Ti 1-x ) O 3 or (Pb 1-y La y ) (Zr x Ti 1-x ). A ferroelectric represented by O 3 (hereinafter, the former is abbreviated as PZT and the latter is abbreviated as PLZT).
The present invention relates to a method for producing a thin film.
【０００２】[0002]
【従来の技術】半導体素子の一種であるＤＲＡＭでは高
集積化が進み、１セル当りの最小蓄積電荷量を３０ｆＦ
程度に維持することが求められているが、このような小
さな容量にするには、信頼性の高いＳｉＯ2膜を薄くし
ていくだけではもはや対応できなくなっている。また、
トレンチ形やスタック形などの立体構造のキャパシタが
試みられているが、このようにすると形状が非常に複雑
になって加工が難しくなる。そこで、高誘電率を有する
誘電体の研究が盛んになってきており、特にＰＺＴ及び
ＰＬＺＴは、その高誘電率と高残留分極ゆえに、不揮発
性メモリ用のキャパシタの材質として注目されている。2. Description of the Related Art In a DRAM, which is a kind of semiconductor device, the degree of integration has been increased, and the minimum accumulated charge amount per cell is 30 fF.
Although it is required to maintain the capacity to such an extent, it is no longer possible to achieve such a small capacity simply by thinning the highly reliable SiO 2 film. Also,
A three-dimensional capacitor such as a trench type or a stack type has been attempted, but this makes the shape extremely complicated and difficult to process. Therefore, research on a dielectric having a high dielectric constant has been actively conducted, and in particular, PZT and PLZT are attracting attention as a material for a capacitor for a nonvolatile memory because of their high dielectric constant and high remanent polarization.
【０００３】Ｓｉ半導体のメモリ用キャパシタとしてこ
れらの強誘電体薄膜を用いる場合、下部電極としては酸
化物に対して安定なＰｔが用いられ、このＰｔは、デバ
イス形成のプロセスを考慮して、ＳｉＯ2上に形成され
るのが一般的である。しかし、ＰｔはＳｉＯ2との密着
性が悪くて剥離してしまうため、Ｐｔ層とＳｉＯ2の間
にバインダとしてＴｉ層が形成される。従来、これらの
Ｐｔ層及びＴｉ層は蒸着法あるいはスパッタリング法で
低温成膜により形成される。またＰＺＴ及びＰＬＺＴの
堆積方法としては、一般に、ゾル・ゲル法、スパッタリ
ング法及びＭＯＣＶＤ法が用いられる。When these ferroelectric thin films are used as Si semiconductor memory capacitors, Pt, which is stable to oxide, is used as the lower electrode, and this Pt is SiO in consideration of the device forming process. It is generally formed on two . However, since Pt has poor adhesion to SiO 2 and peels off, a Ti layer is formed as a binder between the Pt layer and SiO 2 . Conventionally, these Pt layer and Ti layer are formed by low temperature film formation by vapor deposition or sputtering. Further, as a method of depositing PZT and PLZT, a sol-gel method, a sputtering method and a MOCVD method are generally used.
【０００４】ゾル・ゲル法では、原料を基板に塗布した
後、前記強誘電体の結晶化温度（ＰＺＴ、ＰＬＺＴのど
ちらも実質的に６００℃程度）以上に基板を加熱するこ
とにより強誘電体薄膜を形成している。In the sol-gel method, the ferroelectric material is applied by heating the substrate to a temperature above the crystallization temperature of the ferroelectric material (both PZT and PLZT are substantially 600 ° C.) after coating the material on the substrate. Forming a thin film.
【０００５】スパッタリング法では二つの方法がある。
第１の方法は、低い基板温度で強誘電体薄膜を成膜し、
その後、強誘電体の結晶化温度以上で熱処理を行なって
強誘電体薄膜を作製するものである。第２の方法は、基
板を強誘電体の結晶化温度以上にあらかじめ加熱して、
成膜と同時に膜を結晶化させて強誘電体薄膜を形成する
ものである。There are two sputtering methods.
The first method is to form a ferroelectric thin film at a low substrate temperature,
After that, heat treatment is performed at a temperature equal to or higher than the crystallization temperature of the ferroelectric to produce a ferroelectric thin film. The second method is to preheat the substrate above the crystallization temperature of the ferroelectric substance,
At the same time as the film formation, the film is crystallized to form a ferroelectric thin film.
【０００６】ＭＯＣＶＤ法では、基板を強誘電体の結晶
化温度以上に加熱してから原料ガスを供給し、成膜と同
時に膜を結晶化させることにより強誘電体薄膜を形成し
ている。In the MOCVD method, a ferroelectric thin film is formed by heating a substrate to a crystallization temperature of a ferroelectric substance or higher and then supplying a source gas to crystallize the film simultaneously with film formation.
【０００７】[0007]
【発明が解決しようとする課題】ところで、強誘電体を
作製する際の下部電極であるＰｔ層と、ＳｉＯ2とＰｔ
層とのバインダであるＴｉ層とは、一般に、ＳｉＯ2上
に低温で形成されている。そして、この上に強誘電体の
薄膜を作製する場合には、上述のいずれの従来方法にお
いても、どこかの段階で強誘電体の結晶化温度以上に基
板を加熱する必要がある。その結果、下地のＰｔ層とＴ
ｉ層は合金化し、結晶粒が形成される。By the way, a Pt layer, which is a lower electrode when manufacturing a ferroelectric, and SiO 2 and Pt.
The Ti layer, which is a binder for the layer, is generally formed on SiO 2 at a low temperature. When a ferroelectric thin film is formed on this, it is necessary to heat the substrate above the crystallization temperature of the ferroelectric at some stage in any of the conventional methods described above. As a result, the underlying Pt layer and T
The i layer is alloyed and crystal grains are formed.
【０００８】図３はＰＺＴ薄膜を形成する前の基板の断
面の模式図である。Ｓｉウェーハ１０の上にＳｉＯ2層
１２が形成されており、その上にＴｉ層１４とＰｔ層１
６が順に積層されている。このＴｉ層１４とＰｔ層１６
は低温で形成されていて、表面は平滑であるが膜の密度
は低い。FIG. 3 is a schematic view of a cross section of the substrate before forming the PZT thin film. A SiO 2 layer 12 is formed on a Si wafer 10, and a Ti layer 14 and a Pt layer 1 are formed on the SiO 2 layer 12.
6 are sequentially stacked. This Ti layer 14 and Pt layer 16
Is formed at a low temperature, the surface is smooth, but the density of the film is low.
【０００９】図４（Ａ）は図３に示す基板上にＰＺＴ薄
膜を堆積した後の断面を示す模式図であり、図４（Ｂ）
はその表面の模式図である。ＰＺＴ薄膜を形成するには
いずれかの段階で基板を結晶化温度以上に加熱すること
になるが、これにより、下地のＴｉ層とＰｔ層が合金化
してＰｔ−Ｔｉ合金層１８ができ、また、加熱によって
この合金層１８の密度が高くなる。その結果、Ｐｔ−Ｔ
ｉ合金層１８の結晶粒間に隙間ができてしまう。このよ
うな下地上にＰＺＴ薄膜２０を形成すると、下地のＰｔ
−Ｔｉ合金層１８の影響を受けて、結晶粒間の密着性の
悪いＰＺＴ薄膜となってしまう。このようなＰＺＴ薄膜
２０ではリ−ク電流が多く、良好な強誘電特性が得られ
ないといった問題点があった。FIG. 4A is a schematic view showing a cross section after the PZT thin film is deposited on the substrate shown in FIG. 3, and FIG.
Is a schematic view of the surface. In order to form the PZT thin film, the substrate is heated to the crystallization temperature or higher at any stage, but by this, the underlying Ti layer and the Pt layer are alloyed to form the Pt—Ti alloy layer 18, and The density of the alloy layer 18 is increased by heating. As a result, Pt-T
A gap is formed between the crystal grains of the i alloy layer 18. When the PZT thin film 20 is formed on such an underlayer, the underlying Pt
Due to the influence of the —Ti alloy layer 18, a PZT thin film having poor adhesion between crystal grains ends up being formed. Such a PZT thin film 20 has a problem that a large leak current cannot be obtained and good ferroelectric characteristics cannot be obtained.
【００１０】以上のような問題点はＰＬＺＴ薄膜を作製
する場合にも全く同様である。The above-mentioned problems are exactly the same when manufacturing a PLZT thin film.
【００１１】[0011]
【発明の目的】本発明の目的は、リ−ク電流の少ない良
好な強誘電体特性を有する強誘電体薄膜、特にＰＺＴ薄
膜またはＰＬＺＴ薄膜、を作製できる方法を提供するこ
とにある。OBJECT OF THE INVENTION It is an object of the present invention to provide a method for producing a ferroelectric thin film, especially a PZT thin film or a PLZT thin film, which has good ferroelectric properties with a small leak current.
【００１２】[0012]
【課題を解決するための手段】本発明の強誘電体薄膜作
製方法は、強誘電体の結晶化温度以上で下地層を形成す
るものである。より具体的には、ＳｉＯ2上にＴｉとＰ
ｔの薄膜を順に積層して、その上にＰＺＴまたはＰＬＺ
Ｔ強誘電体薄膜を作製する場合に、強誘電体の結晶化温
度以上でＴｉとＰｔの薄膜をＳｉＯ2上に堆積するもの
である。結晶化温度以上の好ましい温度範囲は６００〜
７００℃である。According to the method of manufacturing a ferroelectric thin film of the present invention, an underlayer is formed at a crystallization temperature of the ferroelectric or higher. More specifically, Ti and P are deposited on SiO 2.
t thin films are sequentially stacked, and PZT or PLZ is formed on top of them.
When a T ferroelectric thin film is produced, a thin film of Ti and Pt is deposited on SiO 2 at a crystallization temperature of the ferroelectric or higher. The preferred temperature range above the crystallization temperature is 600-
It is 700 ° C.
【００１３】[0013]
【作用】本発明では、下地層を強誘電体の結晶化温度以
上で形成してあるので、強誘電体を作製するときに基板
を結晶化温度以上に加熱しても、下地層の結晶粒間に隙
間が生じることがなく、良好な特性の強誘電体薄膜を作
製できる。これを、より具体的な構成で説明すると、下
部電極となるＰｔ層と、ＳｉＯ2とＰｔ層とのバインダ
となるＴｉ層とについて、これらを、ＰＺＴまたはＰＬ
ＺＴ薄膜の結晶化温度以上で堆積することにより、ＰＺ
ＴまたはＰＬＺＴ薄膜を形成する以前の段階で、ＳｉＯ
2上に、結晶粒間に隙間のない緻密なＰｔ−Ｔｉ合金層
を形成することができる。したがって、ＰＺＴまたはＰ
ＬＺＴ薄膜を形成するためにその結晶化温度以上に基板
を加熱しても、Ｐｔ−Ｔｉ合金層の結晶粒間に隙間が生
じない。その結果、その上に形成されるＰＺＴまたはＰ
ＬＺＴ薄膜も、結晶粒間の密着性の良好な緻密な膜とな
り、リ−ク電流の少ない良好な強誘電特性が得られる。In the present invention, since the underlayer is formed at the crystallization temperature of the ferroelectric substance or higher, even if the substrate is heated to the crystallization temperature or higher when the ferroelectric substance is manufactured, the crystal grains of the underlayer are formed. It is possible to produce a ferroelectric thin film having good characteristics without a gap between them. This will be described with a more specific configuration. For the Pt layer that will be the lower electrode and the Ti layer that will be the binder for the SiO 2 and Pt layers, these will be described as PZT or PL.
By depositing above the crystallization temperature of the ZT thin film, PZ
Before forming the T or PLZT thin film,
A dense Pt-Ti alloy layer having no gap between crystal grains can be formed on the second layer. Therefore, PZT or P
Even if the substrate is heated above the crystallization temperature to form the LZT thin film, no gap is generated between the crystal grains of the Pt—Ti alloy layer. As a result, PZT or P formed on it
The LZT thin film also becomes a dense film with good adhesion between crystal grains, and good ferroelectric characteristics with a small leak current can be obtained.
【００１４】[0014]
【実施例】図１（Ａ）は、本発明の一実施例において、
ＰＺＴ薄膜を形成する以前の基板の断面を示す模式図で
あり、図１（Ｂ）はその表面の模式図である。まず、Ｓ
ｉウェーハ２２上にＳｉＯ2層２４を形成し、これらを
６５０℃に加熱してから、Ｔｉ層を厚さ３０ｎｍ、Ｐｔ
層を厚さ３００ｎｍだけ、スパッタリング法により順に
堆積した。その結果、厚さが約３３０ｎｍのＰｔ−Ｔｉ
合金層２６が形成された。すなわち、ＰＺＴ薄膜を形成
する以前の段階で、ＳｉＯ2層２４上に、結晶粒間に隙
間のない緻密なＰｔ−Ｔｉ合金層２６が得られた。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1A shows an embodiment of the present invention.
FIG. 1B is a schematic diagram showing a cross section of the substrate before forming the PZT thin film, and FIG. 1B is a schematic diagram of the surface thereof. First, S
A SiO 2 layer 24 is formed on the i-wafer 22, these are heated to 650 ° C., and then a Ti layer is formed to a thickness of 30 nm and Pt.
The layers were sequentially deposited by sputtering, with a thickness of 300 nm. As a result, Pt-Ti with a thickness of about 330 nm
The alloy layer 26 was formed. That is, in the stage before the PZT thin film was formed, the dense Pt—Ti alloy layer 26 having no gap between crystal grains was obtained on the SiO 2 layer 24.
【００１５】図２（Ａ）は図１に示した基板上にＰＺＴ
薄膜を堆積した状態の断面を示す模式図であり、図２
（Ｂ）はその表面の模式図である。上述のようにして形
成されたＰｔ−Ｔｉ層２６上に、スパッタリング法によ
り基板温度６５０℃で厚さ１０００ｎｍのＰＺＴ薄膜２
８を作製した。図２（Ａ）に示すように、ＰＺＴ薄膜２
８は、下地のＰｔ−Ｔｉ合金層２６の結晶性を反映し
て、結晶粒間の密着性の良好な緻密な膜となる。FIG. 2A shows the PZT on the substrate shown in FIG.
2 is a schematic diagram showing a cross section of a state in which a thin film is deposited, and FIG.
(B) is a schematic view of the surface. On the Pt—Ti layer 26 formed as described above, a PZT thin film 2 having a thickness of 1000 nm was formed at a substrate temperature of 650 ° C. by a sputtering method.
8 was produced. As shown in FIG. 2A, the PZT thin film 2
No. 8 reflects the crystallinity of the underlying Pt—Ti alloy layer 26 and becomes a dense film with good adhesion between crystal grains.
【００１６】次に、従来方法との比較結果を示す。従来
方法では、スパッタリング法によりＴｉ層とＰｔ層を特
に基板加熱をしないで形成し、その後、基板を６５０℃
に加熱して、スパッタリング法により１０００ｎｍのＰ
ＺＴ薄膜を形成した。また、本発明の実施例の方法で
は、図１及び図２で説明したような方法でＰＺＴ薄膜を
作製した。両者のＰＺＴ薄膜について３００ｋＶ／ｃｍ
の電界を印加したときのリーク電流を測定したしたとこ
ろ、従来方法によるＰＺＴ薄膜ではリーク電流が１０-7
Ａ／ｃｍ2オーダーであったが、本発明の実施例では１
０-8Ａ／ｃｍ2オーダーとなり、リーク電流が１桁少な
くなった。Next, the result of comparison with the conventional method is shown. In the conventional method, a Ti layer and a Pt layer are formed by a sputtering method without heating the substrate, and then the substrate is heated to 650 ° C.
To 1000 nm P by heating to
A ZT thin film was formed. Further, in the method of the example of the present invention, the PZT thin film was manufactured by the method described with reference to FIGS. 300 kV / cm for both PZT thin films
When the leak current when an electric field of 10 is applied was measured, it was found that the leak current of the conventional PZT thin film was 10 −7.
Although it was on the order of A / cm 2 , it was 1 in the embodiment of the present invention.
It was on the order of 0 -8 A / cm 2 , and the leak current was reduced by one digit.
【００１７】本発明は上述の実施例に限定されず次のよ
うな変更が可能である。 （１）本発明は、ＰＬＺＴ薄膜の作製についても、上述
のＰＺＴ薄膜の作製と全く同様に実施できて、同様な効
果が得られる。The present invention is not limited to the above-mentioned embodiment, but the following modifications are possible. (1) The present invention can be applied to the production of a PLZT thin film in exactly the same manner as the production of the above-described PZT thin film, and the same effect can be obtained.
【００１８】（２）上述の実施例では、Ｔｉ層及びＰｔ
層の膜厚が各々３０ｎｍ及び３００ｎｍであったが、こ
れらの膜厚は、強誘電体薄膜の下部電極として機能でき
れば、これ以外の値でもよい。ただし、Ｐｔ層に対する
Ｔｉ層の膜厚が厚くなりすぎると、Ｐｔ−Ｔｉ合金層と
強誘電体薄膜との界面反応が問題となってくるため、Ｔ
ｉ層は薄いほうがよい。(2) In the above embodiment, the Ti layer and Pt are
The film thicknesses of the layers were 30 nm and 300 nm, respectively, but these film thicknesses may have other values as long as they can function as the lower electrode of the ferroelectric thin film. However, if the thickness of the Ti layer with respect to the Pt layer becomes too thick, the interface reaction between the Pt-Ti alloy layer and the ferroelectric thin film becomes a problem, so T
The i-layer should be thin.
【００１９】（３）上述の実施例ではＴｉ層とＰｔ層の
形成温度及びＰＺＴ薄膜の形成温度はいずれも６５０℃
であったが、この温度は、ＰＺＴまたはＰＬＺＴ強誘電
体相の結晶化温度以上であれば、これ以外の値であって
もよい。ただし、Ｐｔ−Ｔｉ合金層と強誘電体薄膜との
界面反応を抑制するためには、ＰＺＴまたはＰＬＺＴ強
誘電体薄膜を形成するときの温度は、結晶化温度以上
で、かつ、できるだけ低温にするのが好ましい。また、
Ｐｂの欠損を抑制するためにも、ＰＺＴまたはＰＬＺＴ
強誘電体薄膜を形成するときの温度はあまり高温にしな
い方がよい。(3) In the above embodiment, the formation temperature of the Ti layer and Pt layer and the formation temperature of the PZT thin film are both 650 ° C.
However, this temperature may be any other value as long as it is equal to or higher than the crystallization temperature of the PZT or PLZT ferroelectric phase. However, in order to suppress the interfacial reaction between the Pt-Ti alloy layer and the ferroelectric thin film, the temperature at which the PZT or PLZT ferroelectric thin film is formed should be equal to or higher than the crystallization temperature and as low as possible. Is preferred. Also,
In order to suppress the loss of Pb, PZT or PLZT
The temperature when forming the ferroelectric thin film should not be too high.
【００２０】（４）上述の実施例ではＴｉ層、Ｐｔ層及
びＰＺＴ薄膜の作製はいずれもスパッタリング法で行な
ったが、Ｔｉ層及びＰｔ層の形成は蒸着法でもよく、ま
たＰＺＴまたはＰＬＺＴ強誘電体薄膜の形成もスパッタ
リング法以外の方法でもよい。(4) In the above embodiments, the Ti layer, the Pt layer and the PZT thin film were all formed by the sputtering method, but the Ti layer and the Pt layer may be formed by the vapor deposition method, and the PZT or PLZT ferroelectric layer may be formed. The body thin film may be formed by a method other than the sputtering method.
【００２１】（５）上述のＴｉの代わりにＴｉＮを、Ｐ
ｔの代わりにＲｕＯ2を使用することもできる。(5) Instead of Ti described above, TiN is added to P
It is also possible to use RuO 2 instead of t.
【００２２】[0022]
【発明の効果】本発明によれば、下地層を強誘電体の結
晶化温度以上で形成してあるので、強誘電体を作製する
ときに基板を結晶化温度以上に加熱しても、下地層の結
晶粒間に隙間が生じることがなく、良好な特性の強誘電
体薄膜を作製できる。より具体的には、下地となるＰｔ
層とＴｉ層とをＰＺＴまたはＰＬＺＴ薄膜の結晶化温度
以上で堆積することにより、ＰＺＴまたはＰＬＺＴ薄膜
を形成する以前の段階で、ＳｉＯ2上に、結晶粒間に隙
間のない緻密なＰｔ−Ｔｉ合金層を形成することができ
る。したがって、以後、ＰＺＴまたはＰＬＺＴ薄膜を形
成する段階でその結晶化温度以上に基板を加熱しても、
Ｐｔ−Ｔｉ合金層の結晶粒間に隙間が生じることがな
い。その結果、その上に形成されるＰＺＴまたはＰＬＺ
Ｔ薄膜も、結晶粒間の密着性が良好な緻密な膜となり、
リ−ク電流の少ない良好な強誘電特性が得られる。According to the present invention, since the underlayer is formed at the crystallization temperature of the ferroelectric substance or more, even if the substrate is heated to the crystallization temperature or more when manufacturing the ferroelectric substance, It is possible to produce a ferroelectric thin film having good characteristics without forming a gap between crystal grains of the formation. More specifically, Pt as the base
By depositing the PZT or PLZT thin film at a temperature equal to or higher than the crystallization temperature of the PZT or PLZT thin film, a Pt-Ti dense Pt-Ti layer having no gaps between crystal grains is formed on SiO 2 before the PZT or PLZT thin film is formed. An alloy layer can be formed. Therefore, even if the substrate is heated above its crystallization temperature at the stage of forming the PZT or PLZT thin film,
No gap is formed between the crystal grains of the Pt-Ti alloy layer. As a result, PZT or PLZ formed on it
The T thin film also becomes a dense film with good adhesion between crystal grains,
Good ferroelectric characteristics with less leak current can be obtained.
【図１】本発明の一実施例において、ＰＺＴ薄膜を形成
する以前の基板の断面とその表面を示す模式図である。FIG. 1 is a schematic view showing a cross section and a surface of a substrate before forming a PZT thin film in one embodiment of the present invention.
【図２】図１に示した基板上にＰＺＴ薄膜を堆積した状
態の断面とその表面を示す模式図である。FIG. 2 is a schematic diagram showing a cross section and a surface of a PZT thin film deposited on the substrate shown in FIG.
【図３】従来方法において、ＰＺＴ薄膜を形成する前の
基板の断面を示す模式図である。FIG. 3 is a schematic view showing a cross section of a substrate before forming a PZT thin film in a conventional method.
【図４】図３に示す基板上にＰＺＴ薄膜を堆積した状態
の断面とその表面を示す模式図である。FIG. 4 is a schematic view showing a cross section and a surface of a PZT thin film deposited on the substrate shown in FIG.
２２…Ｓｉウェーハ ２４…ＳｉＯ2層 ２６…Ｐｔ−Ｔｉ合金層 ２８…ＰＺＴ薄膜22 ... Si wafer 24 ... SiO 2 layer 26 ... Pt-Ti alloy layer 28 ... PZT thin film
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成５年７月２３日[Submission date] July 23, 1993
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００２[Name of item to be corrected] 0002
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００２】[0002]
【従来の技術】半導体素子の一種であるＤＲＡＭでは高
集積化が進み、メモリ機能の信頼性のため１セル当りの
最小蓄積電荷量を３０ｆＦ程度に維持することが求めら
れているが、信頼性の高いＳｉＯ2膜を薄くしていくだ
けではもはや対応できなくなっている。また、トレンチ
形やスタック形などの立体構造のキャパシタが試みられ
ているが、このようにすると形状が非常に複雑になって
加工が難しくなる。そこで、高誘電率を有する誘電体の
研究が盛んになってきており、特にＰＺＴ及びＰＬＺＴ
は、その高誘電率と高残留分極ゆえに、不揮発性メモリ
用のキャパシタの材質として注目されている。In the DRAM is a type of semiconductor element proceeds is highly integrated, but it is required to maintain a minimum amount of stored charge per cell for reliability of memory function to about 30 fF, trust It can no longer be dealt with simply by thinning the highly resistant SiO 2 film. In addition, a three-dimensional capacitor such as a trench type or a stack type has been tried, but if this is done, the shape becomes very complicated and processing becomes difficult. Therefore, research on dielectrics having a high dielectric constant has been actively conducted, and particularly PZT and PLZT are being researched.
Due to its high dielectric constant and high remanent polarization, it has attracted attention as a material for capacitors for nonvolatile memories.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｂ 19/00 ３２１ 4232−5Ｇ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01B 19/00 321 4232-5G
Claims (3)
体の薄膜を作製する方法において、前記強誘電体の結晶
化温度以上で前記下地層を形成することを特徴とする強
誘電体薄膜作製方法。1. A method of forming an underlayer on a substrate and forming a ferroelectric thin film thereon, wherein the underlayer is formed at a crystallization temperature of the ferroelectric or higher. Body thin film manufacturing method.
層して、その上に一般式 【化１】Ｐｂ1（ＺｒxＴｉ1-x）Ｏ3、 １＞ｘ＞０ または 【化２】（Ｐｂ1-yＬａy）（ＺｒxＴｉ1-x）Ｏ3、 １
＞ｘ＞０、 １＞ｙ＞０ で表される強誘電体の薄膜を作製する方法において、 前記強誘電体の結晶化温度以上でＴｉとＰｔの薄膜をＳ
ｉＯ2上に堆積することを特徴とする強誘電体薄膜作製
方法。 2. A thin film of Ti and Pt is sequentially laminated on SiO 2 , and a general formula: Pb 1 (Zr x Ti 1-x ) O 3 , 1>x> 0 or 2) (Pb 1-y La y ) (Zr x Ti 1-x ) O 3 , 1,
>X> 0, 1>y> 0, a thin film of Ti and Pt is formed at a temperature equal to or higher than the crystallization temperature of the ferroelectric.
A method for producing a ferroelectric thin film, which comprises depositing it on iO 2 .
Ｐｔの薄膜をＳｉＯ2上に堆積することを特徴とする請
求項２記載の強誘電体薄膜作製方法。3. The method for producing a ferroelectric thin film according to claim 2 , wherein a thin film of Ti and Pt is deposited on SiO 2 within a temperature range of 600 to 700 ° C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17362693A JP3381969B2 (en) | 1993-06-22 | 1993-06-22 | Ferroelectric thin film fabrication method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17362693A JP3381969B2 (en) | 1993-06-22 | 1993-06-22 | Ferroelectric thin film fabrication method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH073431A true JPH073431A (en) | 1995-01-06 |
| JP3381969B2 JP3381969B2 (en) | 2003-03-04 |
Family
ID=15964104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17362693A Expired - Fee Related JP3381969B2 (en) | 1993-06-22 | 1993-06-22 | Ferroelectric thin film fabrication method |
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| Country | Link |
|---|---|
| JP (1) | JP3381969B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6238934B1 (en) | 1998-12-30 | 2001-05-29 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating ferroelectric capacitor with improved interface surface characteristic |
| US6610402B2 (en) | 1996-08-22 | 2003-08-26 | Clemson University Research Foundation | Bundles of fibers useful for moving liquids at high fluxes and acquisition/distribution structures that use the bundles |
| JP2004146749A (en) * | 2002-08-30 | 2004-05-20 | Tokyo Inst Of Technol | Electronic device and its manufacturing method |
| US7033001B2 (en) | 2001-12-18 | 2006-04-25 | Matsushita Electric Industrial Co., Ltd. | Piezoelectric element, ink jet head, angular velocity sensor, manufacturing method thereof, and ink jet type recording apparatus |
| JP2007184623A (en) * | 2007-01-22 | 2007-07-19 | Rohm Co Ltd | Dielectric capacitor |
| US8227893B2 (en) | 2004-06-23 | 2012-07-24 | Nec Corporation | Semiconductor device with capacitor element |
| JPWO2015064341A1 (en) * | 2013-10-29 | 2017-03-09 | コニカミノルタ株式会社 | Piezoelectric element, inkjet head, inkjet printer, and method of manufacturing piezoelectric element |
-
1993
- 1993-06-22 JP JP17362693A patent/JP3381969B2/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6610402B2 (en) | 1996-08-22 | 2003-08-26 | Clemson University Research Foundation | Bundles of fibers useful for moving liquids at high fluxes and acquisition/distribution structures that use the bundles |
| US6238934B1 (en) | 1998-12-30 | 2001-05-29 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating ferroelectric capacitor with improved interface surface characteristic |
| US7033001B2 (en) | 2001-12-18 | 2006-04-25 | Matsushita Electric Industrial Co., Ltd. | Piezoelectric element, ink jet head, angular velocity sensor, manufacturing method thereof, and ink jet type recording apparatus |
| US7478558B2 (en) | 2001-12-18 | 2009-01-20 | Panasonic Corporation | Piezoelectric element, ink jet head, angular velocity sensor, method for manufacturing the same, and ink jet recording apparatus |
| JP2004146749A (en) * | 2002-08-30 | 2004-05-20 | Tokyo Inst Of Technol | Electronic device and its manufacturing method |
| US8227893B2 (en) | 2004-06-23 | 2012-07-24 | Nec Corporation | Semiconductor device with capacitor element |
| JP2007184623A (en) * | 2007-01-22 | 2007-07-19 | Rohm Co Ltd | Dielectric capacitor |
| JPWO2015064341A1 (en) * | 2013-10-29 | 2017-03-09 | コニカミノルタ株式会社 | Piezoelectric element, inkjet head, inkjet printer, and method of manufacturing piezoelectric element |
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| Publication number | Publication date |
|---|---|
| JP3381969B2 (en) | 2003-03-04 |
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