JPH1012833A - Ferroelectric film covered base and its usage - Google Patents
Ferroelectric film covered base and its usageInfo
- Publication number
- JPH1012833A JPH1012833A JP8185548A JP18554896A JPH1012833A JP H1012833 A JPH1012833 A JP H1012833A JP 8185548 A JP8185548 A JP 8185548A JP 18554896 A JP18554896 A JP 18554896A JP H1012833 A JPH1012833 A JP H1012833A
- Authority
- JP
- Japan
- Prior art keywords
- film
- ferroelectric film
- ferroelectric
- buffer layer
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims abstract description 12
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 39
- 239000010936 titanium Substances 0.000 claims description 38
- 239000003990 capacitor Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 13
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical group 0.000 claims description 2
- 239000013078 crystal Substances 0.000 abstract description 8
- 238000004544 sputter deposition Methods 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 128
- 239000010410 layer Substances 0.000 description 38
- 238000000034 method Methods 0.000 description 21
- 239000002994 raw material Substances 0.000 description 13
- 230000010287 polarization Effects 0.000 description 12
- 230000000052 comparative effect Effects 0.000 description 11
- 239000010409 thin film Substances 0.000 description 11
- 230000015654 memory Effects 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 8
- 229910052797 bismuth Inorganic materials 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 230000002269 spontaneous effect Effects 0.000 description 6
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000002441 X-ray diffraction Methods 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 238000003980 solgel method Methods 0.000 description 4
- VXUYXOFXAQZZMF-UHFFFAOYSA-N titanium(IV) isopropoxide Chemical compound CC(C)O[Ti](OC(C)C)(OC(C)C)OC(C)C VXUYXOFXAQZZMF-UHFFFAOYSA-N 0.000 description 4
- -1 Bi 4 Ti 5 O 18 Chemical class 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910001882 dioxygen Inorganic materials 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000010574 gas phase reaction Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 125000002524 organometallic group Chemical group 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910013641 LiNbO 3 Inorganic materials 0.000 description 1
- 229910019899 RuO Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 229910000416 bismuth oxide Inorganic materials 0.000 description 1
- 229910002115 bismuth titanate Inorganic materials 0.000 description 1
- YHWCPXVTRSHPNY-UHFFFAOYSA-N butan-1-olate;titanium(4+) Chemical compound [Ti+4].CCCC[O-].CCCC[O-].CCCC[O-].CCCC[O-] YHWCPXVTRSHPNY-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011362 coarse particle Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- TYIXMATWDRGMPF-UHFFFAOYSA-N dibismuth;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Bi+3].[Bi+3] TYIXMATWDRGMPF-UHFFFAOYSA-N 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910000484 niobium oxide Inorganic materials 0.000 description 1
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- GZXOHHPYODFEGO-UHFFFAOYSA-N triglycine sulfate Chemical compound NCC(O)=O.NCC(O)=O.NCC(O)=O.OS(O)(=O)=O GZXOHHPYODFEGO-UHFFFAOYSA-N 0.000 description 1
- ZHXAZZQXWJJBHA-UHFFFAOYSA-N triphenylbismuthane Chemical compound C1=CC=CC=C1[Bi](C=1C=CC=CC=1)C1=CC=CC=C1 ZHXAZZQXWJJBHA-UHFFFAOYSA-N 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 229910052845 zircon Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、強誘電体膜被覆基
体及びその用途に関する。更に詳しくは、本発明は、強
誘電体メモリ素子、焦電センサ素子、圧電素子等に使用
できる強誘電体膜被覆基体に関する。The present invention relates to a ferroelectric film-coated substrate and its use. More specifically, the present invention relates to a ferroelectric film-coated substrate that can be used for a ferroelectric memory element, a pyroelectric sensor element, a piezoelectric element, and the like.
【0002】[0002]
【従来の技術】強誘電体は自発分極、高誘電率、電気光
学効果、圧電効果及び焦電効果等の多くの機能をもつこ
とから、コンデンサ、発振器、光変調器又は赤外線セン
サー等の広範なデバイス開発に応用されている。しか
し、従来これらの用途には、単結晶かセラミックスのも
のが使用されてきた。2. Description of the Related Art Ferroelectric materials have many functions such as spontaneous polarization, high dielectric constant, electro-optic effect, piezoelectric effect and pyroelectric effect, and are therefore widely used in capacitors, oscillators, optical modulators or infrared sensors. Used in device development. However, in the past, single crystals or ceramics have been used for these applications.
【0003】一方、薄膜形成技術の進展に伴って、高品
質の強誘電体膜が得られるようになり、従来なかった応
用が期待されている。特に、最近DRAM等の半導体メ
モリと組み合わせることで、高密度でかつ高速に動作に
する強誘電体メモリ(FRAM)の開発が行われてい
る。強誘電体メモリは、強誘電体の強誘電特性(自発分
極効果)を利用したバックアップ電源不要な不揮発性メ
モリである。このようなメモリの開発には残留分極(P
r)が大きく、かつ抗電界(Ec)が小さく、低リーク
電流であり、分極反転の繰り返し耐性に優れる等の特性
を持つ強誘電体材料が必要である。更には動作電圧の低
減と半導体微細加工プロセスに適合させるため、膜厚2
00nm以下の薄膜で上記の特性を実現することが望ま
れている。On the other hand, with the development of thin film forming technology, high-quality ferroelectric films have been obtained, and applications that have not existed in the past are expected. In particular, recently, a ferroelectric memory (FRAM) that operates at high density and at high speed by being combined with a semiconductor memory such as a DRAM has been developed. A ferroelectric memory is a non-volatile memory that does not require a backup power supply and uses a ferroelectric characteristic (spontaneous polarization effect) of a ferroelectric. The development of such memories requires remanent polarization (P
It is necessary to use a ferroelectric material having characteristics such as a large r), a small coercive electric field (Ec), a low leakage current, and an excellent resistance to repetition of domain inversion. Further, to reduce the operating voltage and adapt to the semiconductor fine processing process,
It is desired to realize the above characteristics with a thin film having a thickness of 00 nm or less.
【0004】現在FRAM等への応用を目的としてPb
TiO3 、PZT、PLZT等のペロブスカイト構造を
有する酸化物強誘電体の薄膜化が、スパッタリング法、
蒸着法、ゾル−ゲル法、有機金属分解(MOD)法、有
機金属化学気相成長(MOCVD)法等の薄膜形成方法
により試みられている。上記の強誘電体材料のうち、P
ZTは現在もっとも集中的に研究されているのであり、
例えば残留分極Prが10μC/cm2 から26μC/
cm2 と大きな値を持つものも得られている。しかしな
がら、蒸気圧の高いPbを含むため成膜時や熱処理等で
の膜組成変化が起こりやすいことや、ピンホールの発
生、耐酸化性の下地電極PtとPbの反応による低誘電
率層の発生等の結果、膜厚の低減に伴いリーク電流や分
極反転繰り返し耐性の劣化が起こるという問題点があ
る。このため、強誘電特性、分極反転耐性に優れた材料
の開発が望まれている。また、集積デバイスへの応用を
考えた場合、微細加工に対応できるような薄膜の緻密
性、平面平滑性も必要となる。At present, Pb is used for application to FRAM and the like.
An oxide ferroelectric having a perovskite structure such as TiO 3 , PZT, or PLZT is formed into a thin film by a sputtering method.
Attempts have been made by a thin film forming method such as a vapor deposition method, a sol-gel method, an organometallic decomposition (MOD) method, and an organometallic chemical vapor deposition (MOCVD) method. Of the above ferroelectric materials, P
ZT is currently the most intensively researched,
For example, the residual polarization Pr is 10 μC / cm 2 to 26 μC /
Some have values as large as cm 2 . However, since Pb having a high vapor pressure is contained, a change in the film composition is likely to occur during film formation or heat treatment, etc., generation of pinholes, generation of a low dielectric constant layer due to the reaction between the oxidation-resistant base electrode Pt and Pb. As a result, there is a problem in that the leakage current and the polarization inversion repetition resistance deteriorate as the film thickness decreases. Therefore, development of a material having excellent ferroelectric properties and polarization reversal resistance has been desired. In addition, in consideration of application to an integrated device, the thin film must have denseness and planar smoothness that can cope with fine processing.
【0005】他方、リーク電流や分極反転耐性に悪影響
を及ぼすPbを含まない酸化物強誘電体として、層状ペ
ロブスカイト構造を有するチタン酸ビスマスBi4 Ti
3 O12がある。その強誘電性は、a軸方向に残留自発分
極Pr=50μC/cm2 、抗電界Ec=50kV/c
m、c軸方向に残留自発分極Pr=4μC/cm2 、抗
電界Ec=4kV/cmと、優れた特性を示すものであ
る。On the other hand, as an oxide ferroelectric containing no Pb that adversely affects leakage current and polarization inversion resistance, bismuth titanate Bi 4 Ti having a layered perovskite structure is used.
There is 3 O 12 . The ferroelectric properties are as follows: residual spontaneous polarization Pr = 50 μC / cm 2 in the a-axis direction, coercive electric field Ec = 50 kV / c
The spontaneous polarization Pr = 4 μC / cm 2 and the coercive electric field Ec = 4 kV / cm in the m and c axis directions show excellent characteristics.
【0006】従って、このBi4 Ti3 O12のもつ大き
な自発分極を強誘電体不揮発性メモリ等に応用するため
には、基体に垂直方向に結晶のa軸成分を多く持つよう
にすることが望ましい。Bi4 Ti3 O12の薄膜化は、
これまでもMOCVD法やゾル−ゲル法により試みられ
ているが、それらのほとんどが自発分極が小さいc軸配
向膜であり、a軸配向膜は、ほとんど得られていないの
が現状である また、従来のゾル−ゲル法では、良好な強誘電特性を得
るために650℃以上の熱処理が必要であり、更に膜表
面モフォロジーは0.5μm程度の結晶粒からなるので
微細加工を必要とする高集積デバイスに適用するのは困
難である。一方、MOCVD法によりc軸配向のBi4
Ti3 O12薄膜が基板温度600℃以上でPt/SiO
2 /Si基体上に作製されているが、これらの基体は、
そのまま実際のデバイス構造に適用できるものではな
い。すなわち、Pt/Ti/SiO2 /Si基体のよう
に、Pt電極層とその下のSiO2 との接着強度を確保
するためのTi膜等の接着層が必要である。ところが、
このような接着層を設けた基体上にBi4 Ti3 O12薄
膜をMOCVD法により作製した場合、その表面モフォ
ロジーは0.5μm程度の粗大結晶粒からなるととも
に、常誘電性のパイロクロア相(Bi2 Ti2 O7 )が
発生しやすくなることが報告されている(Jpn.J.
Appl.Phys.,32,1993,pp.408
6及びJ.Ceramic Soc.Japan,10
2,1994,pp.512参照)。膜表面モフォロジ
ーが、粗大結晶粒からなると、微細加工を必要とする高
集積デバイスには応用できないばかりか薄い膜厚ではピ
ンホールの原因となり、リーク電流の発生をもたらすこ
とになる。そこで、薄い膜厚で良好な強誘電特性を有す
る強誘電体膜を実現するため、基体と強誘電体膜の間に
バッファ層を挿入することにより、強誘電体膜の緻密化
と表面平滑化が可能となることが報告されている(Jp
n.J.Appl.Phys.,32,1993,p
p.4086)。Therefore, in order to apply the large spontaneous polarization of Bi 4 Ti 3 O 12 to a ferroelectric nonvolatile memory or the like, it is necessary to have many a-axis components of the crystal in the direction perpendicular to the substrate. desirable. The thinning of Bi 4 Ti 3 O 12
Until now, attempts have been made by MOCVD or sol-gel methods, but most of them are c-axis oriented films with small spontaneous polarization, and at present, almost no a-axis oriented films have been obtained. In the conventional sol-gel method, a heat treatment at 650 ° C. or more is required to obtain good ferroelectric properties, and the film surface morphology is composed of crystal grains of about 0.5 μm, so high integration requiring fine processing is required. Difficult to apply to devices. On the other hand, Bi 4
Ti 3 O 12 thin film is made of Pt / SiO
2 / Made on Si substrates, these substrates are:
It cannot be directly applied to an actual device structure. That is, like a Pt / Ti / SiO 2 / Si substrate, an adhesive layer such as a Ti film for securing the adhesive strength between the Pt electrode layer and the underlying SiO 2 is required. However,
When a Bi 4 Ti 3 O 12 thin film is formed by MOCVD on a substrate provided with such an adhesive layer, the surface morphology is composed of coarse crystal grains of about 0.5 μm and the paraelectric pyrochlore phase (Bi 2 Ti 2 O 7 ) has been reported to occur easily (Jpn.
Appl. Phys. , 32,1993, pp. 408
6 and J.I. Ceramic Soc. Japan, 10
2, 1994, p. 512). If the film surface morphology is composed of coarse crystal grains, it cannot be applied to a highly integrated device requiring fine processing, and if the film thickness is small, it causes a pinhole and causes a leakage current. Therefore, in order to realize a ferroelectric film having good ferroelectric properties with a thin film thickness, a buffer layer is inserted between the base and the ferroelectric film to make the ferroelectric film dense and smooth. Is reported to be possible (Jp
n. J. Appl. Phys. , 32, 1993, p
p. 4086).
【0007】[0007]
【発明が解決しようとする課題】しかし、上記の強誘電
体薄膜の上下を同種の電極で挟んだキャパシタにおい
て、下部電極と強誘電体薄膜層との間にバッファ層を挿
入することにより、上下の電極と接する材料が異なるこ
とに起因するヒステリシスループの非対称性が発生しや
すくなる。このような現象はバッファ層を用いない場合
にも上下の電極材料が異なると発生する。However, in a capacitor having the above-mentioned ferroelectric thin film sandwiched between upper and lower electrodes by the same kind of electrode, a buffer layer is inserted between the lower electrode and the ferroelectric thin film layer, thereby making the upper and lower layers thin. , The asymmetry of the hysteresis loop due to the difference in the material in contact with the electrode is likely to occur. Such a phenomenon occurs when upper and lower electrode materials are different even when the buffer layer is not used.
【0008】以上のように、従来のバッファ層を用いた
技術では強誘電体薄膜の緻密化、表面平滑化は可能であ
るが、膜の多層構造に起因する強誘電性ヒステリシスル
ープの非対称性の問題を有している。As described above, the technique using the conventional buffer layer allows the ferroelectric thin film to be densified and the surface to be smoothed, but the asymmetry of the ferroelectric hysteresis loop caused by the multilayer structure of the film is possible. Have a problem.
【0009】[0009]
【課題を解決するための手段】かくして本発明によれ
ば、第1強誘電体膜、中間緩衝層及び前記第1強誘電体
膜と同種の第2強誘電体膜をこの順で基体上に備えてな
ることを特徴とする強誘電体膜被覆基体が提供される。
また、本発明によれば、下部電極、第1強誘電体膜、中
間緩衝層、前記第1強誘電体膜と同種の第2強誘電体膜
及び前記同種の上部電極をこの順で基体上に備えてなる
ことを特徴とするキャパシタが提供される。Thus, according to the present invention, a first ferroelectric film, an intermediate buffer layer and a second ferroelectric film of the same type as the first ferroelectric film are formed on a substrate in this order. A ferroelectric film-coated substrate characterized by comprising:
According to the present invention, the lower electrode, the first ferroelectric film, the intermediate buffer layer, the second ferroelectric film of the same type as the first ferroelectric film, and the upper electrode of the same type are formed on the base in this order. Is provided.
【0010】[0010]
【発明の実施の形態】まず、本発明に使用できる基体に
は、シリコン基板、GaAs基板等や、それら基板上に
トランジスタ、層間絶縁膜等のように何らかの下地層が
形成されたものも含まれる。次に、基体上には、第1強
誘電体膜が形成される。第1強誘電体膜に使用できる材
料としては、Pbを含まないものであればいずれでもよ
い。具体的には、Bi4 Ti3 O12、SrBi2 Ta2
O9 、SrBi2 Nb2 O9 、SrBi4 Ti4 O15、
BaBi2 Ta2 O9 、BaBi2 Nb2 O9 、BaB
i4 Ti4 O15、Na0.5 Bi4.5 Ti4 O15、K0.5
Bi4.5 Ti4 O15、Sr2 Bi4 Ti5 O18、Ba2
Bi4 Ti5 O18等のBi系の層状化合物、硫酸グリシ
ン(TGS)、LiNbO3 、LiTaO3 、BaTi
O3 、SrTiO3 等が挙げられる。この内、Bi4 T
i3 O12が好ましい。また、膜厚は10〜200nmで
あることが好ましい。この第1強誘電体膜の形成方法
は、特に限定されず公知の方法をいずれも使用すること
ができる。例えばスパッタリング、蒸着、CVD、MO
CVD、ゾル−ゲル法等が挙げられる。この内、MOC
VD法が好ましい。DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a substrate usable in the present invention includes a silicon substrate, a GaAs substrate and the like, and a substrate on which any underlayer such as a transistor and an interlayer insulating film is formed. . Next, a first ferroelectric film is formed on the base. As a material that can be used for the first ferroelectric film, any material that does not contain Pb may be used. Specifically, Bi 4 Ti 3 O 12 , SrBi 2 Ta 2
O 9 , SrBi 2 Nb 2 O 9 , SrBi 4 Ti 4 O 15 ,
BaBi 2 Ta 2 O 9 , BaBi 2 Nb 2 O 9 , BaB
i 4 Ti 4 O 15 , Na 0.5 Bi 4.5 Ti 4 O 15 , K 0.5
Bi 4.5 Ti 4 O 15 , Sr 2 Bi 4 Ti 5 O 18 , Ba 2
Bi-based layered compounds such as Bi 4 Ti 5 O 18 , glycine sulfate (TGS), LiNbO 3 , LiTaO 3 , BaTi
O 3 and SrTiO 3 are exemplified. Among them, Bi 4 T
i 3 O 12 is preferred. The thickness is preferably 10 to 200 nm. The method for forming the first ferroelectric film is not particularly limited, and any known method can be used. For example, sputtering, vapor deposition, CVD, MO
CVD, a sol-gel method, etc. are mentioned. Of these, MOC
The VD method is preferred.
【0011】MOCVD法により成膜する場合、基板温
度は450〜650℃であることが好ましい。450℃
より低くすると、強誘電体膜が十分な結晶性を得られな
いので好ましくなく、650℃より高くすると強誘電体
膜を構成する結晶が粗大化するので好ましくない。例え
ば、Bi4 Ti3 O12を形成する場合のMOCVD法に
使用できるビスマス原料としては、トリオルトトリルビ
スマス、トリフェニルビスマス等が挙げられ、一方、チ
タン原料としては、チタンイソプロポキサイド、チタン
テトラブトキシド等が挙げられる。実際には、ビスマス
原料、チタン原料及び酸素ガスを、不活性ガス(例え
ば、アルゴン、窒素等)をキャリアガスとして成膜装置
内に供給することにより成膜が行われる。なお、成膜装
置内の圧力は、2〜10Torrであることが好まし
い。10Torrより高い場合、気相反応が起こりやす
くなるので好ましくなく、2Torrより低い場合、成
膜速度が遅くなるので好ましくない。When forming a film by the MOCVD method, the substrate temperature is preferably 450 to 650 ° C. 450 ° C
If the temperature is lower, the ferroelectric film cannot obtain sufficient crystallinity, which is not preferable. If the temperature is higher than 650 ° C., the crystal constituting the ferroelectric film is undesirably coarse. For example, as a bismuth raw material that can be used in the MOCVD method for forming Bi 4 Ti 3 O 12 , triortho tolyl bismuth, triphenyl bismuth, and the like can be mentioned. On the other hand, as titanium raw materials, titanium isopropoxide, titanium tetra Butoxide and the like. Actually, a film is formed by supplying a bismuth raw material, a titanium raw material and an oxygen gas into a film forming apparatus by using an inert gas (eg, argon, nitrogen or the like) as a carrier gas. Note that the pressure in the film forming apparatus is preferably 2 to 10 Torr. If the pressure is higher than 10 Torr, a gas phase reaction is likely to occur, and if the pressure is lower than 2 Torr, the film forming rate is undesirably reduced.
【0012】次いで、第1強誘電体膜上には、中間緩衝
層が形成される。中間緩衝層に使用できる材料として
は、酸化チタン、酸化タンタル、酸化ニオブ、チタン酸
ストロンチウム、チタン酸バリウム、酸化ジルコン、酸
化アルミニウム、酸化ビスマス、酸化イットリウム、酸
化ハフニウム等の金属酸化物が挙げられる。この内、酸
化チタンが好ましい。また、膜厚は2〜7nmの範囲が
好ましい。膜厚が2nmより薄いと第1強誘電体膜の全
面を覆うことができないので好ましくなく、7nmより
厚いと印加された電圧が第1強誘電体膜にかかりにくい
ので好ましくない。中間緩衝層の形成方法は、特に限定
されず公知の方法をいずれも使用することができる。例
えばスパッタリング、蒸着、CVD、MOCVD法等が
挙げられる。この内、MOCVD法が好ましく、例えば
上記第1強誘電体膜の製法と同様の条件下で、ビスマス
原料を供給しないことを除いて同じように操作すること
により形成することができる。Next, an intermediate buffer layer is formed on the first ferroelectric film. Materials that can be used for the intermediate buffer layer include metal oxides such as titanium oxide, tantalum oxide, niobium oxide, strontium titanate, barium titanate, zircon oxide, aluminum oxide, bismuth oxide, yttrium oxide, and hafnium oxide. Of these, titanium oxide is preferred. The thickness is preferably in the range of 2 to 7 nm. If the film thickness is smaller than 2 nm, it is not preferable because the entire surface of the first ferroelectric film cannot be covered, and if it is larger than 7 nm, the applied voltage is less likely to be applied to the first ferroelectric film. The method for forming the intermediate buffer layer is not particularly limited, and any known method can be used. For example, sputtering, vapor deposition, CVD, MOCVD and the like can be mentioned. Of these, the MOCVD method is preferable. For example, the film can be formed by performing the same operation under the same conditions as in the above-described method of manufacturing the first ferroelectric film except that no bismuth raw material is supplied.
【0013】上記中間緩衝層上に更に第2強誘電体膜を
形成することにより本発明の強誘電体膜被覆基体を形成
することができる。ここで第2強誘電体膜は、第1強誘
電体膜と同種の材料からなる。また、膜厚は50〜30
0nmであることが好ましい。また、基体と第1強誘電
体膜との間に以下で説明する下部電極、基体と下部電極
との間に絶縁膜、絶縁膜と下部電極との間に密着層を設
けてもよい。絶縁膜は、膜厚50〜300nmの酸化シ
リコン、窒化シリコン又はそれらの積層膜からなり、熱
酸化法、CVD法、スパッタリング法等で形成すること
ができる。密着層としては、Ti、Ta等が挙げられ
る。The ferroelectric film-coated substrate of the present invention can be formed by further forming a second ferroelectric film on the intermediate buffer layer. Here, the second ferroelectric film is made of the same material as the first ferroelectric film. The film thickness is 50-30.
It is preferably 0 nm. Further, a lower electrode described below may be provided between the base and the first ferroelectric film, an insulating film may be provided between the base and the lower electrode, and an adhesion layer may be provided between the insulating film and the lower electrode. The insulating film is made of silicon oxide, silicon nitride, or a stacked film thereof having a thickness of 50 to 300 nm, and can be formed by a thermal oxidation method, a CVD method, a sputtering method, or the like. Examples of the adhesion layer include Ti, Ta, and the like.
【0014】本発明の強誘電体膜被覆基体は、強誘電効
果、圧電効果、焦電効果、電気光学効果等を利用するも
のであればどのような装置にも利用することができる。
そのような装置として、半導体装置、光変調器、超音波
センサー、赤外線リニアアレイセンサー等が挙げられ
る。更に本発明によれば、下部電極、第1強誘電体膜、
中間緩衝層、前記第1強誘電体膜と同種の第2強誘電体
膜及び前記同種の上部電極をこの順で基体上に備えてな
ることを特徴とするキャパシタが提供される。The substrate coated with a ferroelectric film of the present invention can be used for any device utilizing a ferroelectric effect, a piezoelectric effect, a pyroelectric effect, an electro-optical effect and the like.
Examples of such a device include a semiconductor device, an optical modulator, an ultrasonic sensor, and an infrared linear array sensor. Further, according to the present invention, the lower electrode, the first ferroelectric film,
A capacitor is provided, comprising an intermediate buffer layer, a second ferroelectric film of the same type as the first ferroelectric film, and an upper electrode of the same type on a base in this order.
【0015】基体には、上記強誘電体膜被覆基体と同じ
基体が使用できる。下部電極に使用できる材料として
は、Pt、Al、Cu、RuO2 、Ir、IrO2 等が
挙げられる。この内、Ptが好ましい。また、膜厚は5
0〜300nmであることが好ましい。この下部電極の
形成方法は、特に限定されず公知の方法をいずれも使用
することができる。例えばスパッタリング、蒸着、MO
CVD法等が挙げられる。As the substrate, the same substrate as the ferroelectric film-coated substrate can be used. Materials that can be used for the lower electrode include Pt, Al, Cu, RuO 2 , Ir, IrO 2 and the like. Of these, Pt is preferred. The film thickness is 5
It is preferably from 0 to 300 nm. The method for forming the lower electrode is not particularly limited, and any known method can be used. For example, sputtering, evaporation, MO
CVD method and the like can be mentioned.
【0016】次に、第1強誘電体膜、中間緩衝層及び第
2強誘電体膜が下部電極上にこの順で形成される。使用
しうる原料、膜厚及び形成方法等は上記強誘電体膜被覆
基体で説明した内容と同様である。更に、第2強誘電体
膜上に上部電極を形成することにより本発明のキャパシ
タを形成することができる。ここで上部電極は、下部電
極と同種の材料からなる。また、膜厚は50〜300n
mであることが好ましい。なお、形成方法は、下部電極
と同様の方法を使用できる。Next, a first ferroelectric film, an intermediate buffer layer and a second ferroelectric film are formed on the lower electrode in this order. The raw materials, film thicknesses, forming methods, and the like that can be used are the same as those described for the ferroelectric film-coated substrate. Furthermore, the capacitor of the present invention can be formed by forming an upper electrode on the second ferroelectric film. Here, the upper electrode is made of the same material as the lower electrode. The film thickness is 50 to 300 n.
m is preferable. Note that the same method as that for forming the lower electrode can be used.
【0017】なお、基体と下部電極の間に、それらの密
着性を向上させるためのTi、Ta等からなる密着層を
設けてもよい。上記キャパシタの使用例としては、例え
ば図1の如き不揮発性メモリが挙げられる。このメモリ
は、基板の表面層に設けられたビットライン1間の基板
上にワードライン2からなるトランジスタ3が設けら
れ、ワードライン2上に絶縁膜4を介して下部電極5、
強誘電体膜6及び上部電極7からなるキャパシタ8が配
置されている(この図では中間緩衝層は省略されてい
る)。キャパシタは、配線層9によって一方のビットラ
イン1と接続されてなる構造を有している。なお、この
図において、基体とは下部電極5より下に位置する絶縁
膜4、トランジスタ3及び基板1から構成されることと
なる。Incidentally, an adhesion layer made of Ti, Ta or the like for improving the adhesion may be provided between the base and the lower electrode. As an example of the use of the capacitor, there is a nonvolatile memory as shown in FIG. 1, for example. In this memory, a transistor 3 comprising a word line 2 is provided on a substrate between bit lines 1 provided on a surface layer of the substrate, and a lower electrode 5 is provided on the word line 2 via an insulating film 4.
A capacitor 8 including a ferroelectric film 6 and an upper electrode 7 is arranged (an intermediate buffer layer is omitted in this figure). The capacitor has a structure connected to one bit line 1 by a wiring layer 9. In this figure, the base is composed of the insulating film 4 located below the lower electrode 5, the transistor 3, and the substrate 1.
【0018】上記のように、強誘電体膜の間に中間緩衝
層を配置することにより、従来の基体と強誘電体膜の間
にバッファ層を配置した場合の構造の非対称性に起因す
るヒステリシスループの非対称性を防ぐことができる。
更に、強誘電体膜の表面を緻密化、平坦化でき、強誘電
体膜のモフォロジーに起因するリーク電流の発生を防ぐ
ことができる。As described above, by disposing the intermediate buffer layer between the ferroelectric films, the hysteresis caused by the asymmetry of the structure when the buffer layer is disposed between the conventional substrate and the ferroelectric film. Loop asymmetry can be prevented.
Further, the surface of the ferroelectric film can be densified and flattened, and the generation of a leak current due to the morphology of the ferroelectric film can be prevented.
【0019】[0019]
実施例1 以下の工程により図2に示す如きキャパシタを製造し
た。まず、シリコン単結晶ウエハ(基板)11の表面に
膜厚200nmの熱酸化膜(酸化シリコン層)12を形
成し、その上に膜厚30nmのTa層(接着層)13と
200nmのPt電極(下部電極)14をこの順でスパ
ッタリング法により形成し、Pt/Ta/SiO2 /S
iからなる基体を作製した。Example 1 A capacitor as shown in FIG. 2 was manufactured by the following steps. First, a thermal oxide film (silicon oxide layer) 12 having a thickness of 200 nm is formed on the surface of a silicon single crystal wafer (substrate) 11, and a Ta layer (adhesive layer) 13 having a thickness of 30 nm and a Pt electrode (200 nm) are formed thereon. A lower electrode 14 is formed in this order by a sputtering method, and Pt / Ta / SiO 2 / S
A substrate made of i was prepared.
【0020】次に、Pt電極14上に、20nmのBi
4 Ti3 O12膜(第1強誘電体膜)15をMOCVD法
により成膜した。成膜条件は、基板温度600℃、成膜
時間10分とした。続いて、上記Bi4 Ti3 O12膜1
5上に、基板温度400℃、成膜時間2分で5nmの酸
化チタン(中間緩衝層)16を成膜した。Next, on the Pt electrode 14, a 20 nm Bi
A 4 Ti 3 O 12 film (first ferroelectric film) 15 was formed by MOCVD. The film forming conditions were a substrate temperature of 600 ° C. and a film forming time of 10 minutes. Subsequently, the above Bi 4 Ti 3 O 12 film 1
On 5, a titanium oxide (intermediate buffer layer) 16 of 5 nm was formed at a substrate temperature of 400 ° C. and a film formation time of 2 minutes.
【0021】更に、上記酸化チタン16上に、基板温度
600℃、成膜時間40分で、80nmのBi4 Ti3
O12膜(第2強誘電体膜)17を形成することにより、
全厚105nmの3層膜からなる強誘電体膜被覆基体を
形成した。なお、Bi4 Ti3 O12膜及び酸化チタンの
他の成膜条件は、表1に示した。Further, on the titanium oxide 16, a substrate temperature of 600 ° C., a film formation time of 40 minutes, and a thickness of 80 nm of Bi 4 Ti 3
By forming the O 12 film (second ferroelectric film) 17,
A ferroelectric film-coated substrate consisting of a three-layer film having a total thickness of 105 nm was formed. Table 1 shows other film forming conditions of the Bi 4 Ti 3 O 12 film and the titanium oxide.
【0022】[0022]
【表1】 Bi4 Ti3 O12膜の成膜は、上記表1に示すように、
ビスマス原料としてトリオルトトリルビスマス(Bi
(o−C7 H7 )3 )を、チタン原料としてチタンイソ
プロポキサイド(Ti(i−OC3 H7 )4 )をそれぞ
れ用いた。更に、これら原料を表1に示す温度でそれぞ
れ加熱気化し(ビスマス原料160℃、チタン原料50
℃)、キャリアガスとしてアルゴン(Ar)ガスと反応
ガスである酸素(O2 )ガスと共に加熱保持した基板上
に供給した。ここで、アルゴンガス流量は、ビスマス原
料に対して200sccm、チタン原料に対して50s
ccmとし、酸素ガス流量は1000sccmとした。
なお、上記成膜工程において成膜室内圧力は、10To
rr以上であると気相反応が起こりやすくなるので5T
orrとした。[Table 1] The Bi 4 Ti 3 O 12 film was formed as shown in Table 1 above.
Triortho tolyl bismuth (Bi)
(O-C 7 H 7) 3 a), it was used as the titanium isopropoxide (Ti (i-OC 3 H 7) 4) as a titanium raw material. Further, these raw materials were heated and vaporized at the temperatures shown in Table 1 (bismuth raw material 160 ° C., titanium raw material 50
° C), and supplied onto a substrate heated and held together with an argon (Ar) gas as a carrier gas and an oxygen (O 2 ) gas as a reaction gas. Here, the argon gas flow rate was 200 sccm for the bismuth raw material and 50 s for the titanium raw material.
ccm and the oxygen gas flow rate was 1000 sccm.
Note that the pressure in the film forming chamber in the film forming step was 10 To
If it is more than rr, a gas phase reaction is likely to occur.
orr.
【0023】なお、酸化チタンについては、チタン原料
と酸素ガスのみを供給した。上記のように形成したBi
4 Ti3 O12膜(第2強誘電体膜)の表面モフォロジー
について、SEM(走査型電子顕微鏡)により観察した
結果を図3に示した。図3から判るように、本実施例の
膜は、粒径約0.15μmのグレインからなり、緻密で
表面が平滑であることが判った。これは、Bi4 Ti3
O12膜(第1強誘電体膜)は、下部電極との間にバッフ
ァ層がないため粒径が大きくなるが、酸化チタン(中間
緩衝層)を形成することにより、Bi4 Ti3 O12膜
(第2強誘電体膜)の粒径が小さくなり、その結果とし
て、Bi4 Ti3 O12膜(第2強誘電体膜)の表面の緻
密化及び平坦化が実現できたものと考えられる。As for titanium oxide, only a titanium raw material and oxygen gas were supplied. Bi formed as above
FIG. 3 shows the result of observing the surface morphology of the 4 Ti 3 O 12 film (second ferroelectric film) by SEM (scanning electron microscope). As can be seen from FIG. 3, the film of this example was made of grains having a particle size of about 0.15 μm, and was found to be dense and had a smooth surface. This is Bi 4 Ti 3
The O 12 film (first ferroelectric film) has a large particle size because there is no buffer layer between the O 12 film and the lower electrode. However, by forming titanium oxide (intermediate buffer layer), Bi 4 Ti 3 O 12 It is thought that the particle diameter of the film (second ferroelectric film) was reduced, and as a result, the surface of the Bi 4 Ti 3 O 12 film (second ferroelectric film) could be densified and flattened. Can be
【0024】また、このBi4 Ti3 O12膜(第2強誘
電体膜)の結晶性をX線回折法により評価した結果を図
4に示した。得られた膜は、ランダム配向のBi4 Ti
3 O12であることが示されている。次に、上記Bi4 T
i3 O12膜(第2強誘電体膜)17上に上部電極として
Pt電極(100μmφ)18を真空蒸着により積層し
キャパシタを形成した。図5に、このキャパシタの電流
電圧特性を示す。図5では、印加電圧5Vのとき、Il
(リーク電流密度)=1×10-8A/cm2 の値を得る
ことができた。更に、図6に、このキャパシタのヒステ
リシスループを示した。上下対称性の良好なヒステリシ
スループを得ることができ、かつ従来のc軸配向膜と比
較してa軸成分を多く含むため、印加電圧5Vのとき、
残留分極Pr=14μC/cm2 、抗電界Ec=130
kV/cmとc軸配向の強誘電体膜より大きい値を得る
ことができた。FIG. 4 shows the result of evaluating the crystallinity of the Bi 4 Ti 3 O 12 film (second ferroelectric film) by the X-ray diffraction method. The obtained film is made of Bi 4 Ti having random orientation.
It is shown to be 3 O 12 . Next, the above Bi 4 T
A Pt electrode (100 μmφ) 18 as an upper electrode was laminated on the i 3 O 12 film (second ferroelectric film) 17 by vacuum evaporation to form a capacitor. FIG. 5 shows current-voltage characteristics of this capacitor. In FIG. 5, when the applied voltage is 5 V, Il
A value of (leak current density) = 1 × 10 −8 A / cm 2 was obtained. FIG. 6 shows a hysteresis loop of this capacitor. Since a hysteresis loop with good vertical symmetry can be obtained and contains more a-axis components than the conventional c-axis alignment film, when the applied voltage is 5 V,
Remanent polarization Pr = 14 μC / cm 2 , coercive electric field Ec = 130
It was possible to obtain a value of kV / cm higher than that of the ferroelectric film having the c-axis orientation.
【0025】比較例1 中間緩衝層を形成せず、強誘電体膜を2層に分けること
なく105nmの強誘電体膜を600℃、60分間かけ
て形成すること以外は、実施例1と同様にしてキャパシ
タを形成した。このキャパシタはリーク電流値が大きす
ぎて、ヒステリシスループを測定することができなかっ
た。また、上部電極形成前の強誘電体膜の表面をSEM
により観察した結果を図7に示した。図7からわかるよ
うに、この比較例の膜は粗大粒子からなる表面凹凸の激
しい膜であり、リーク電流の増加は、この表面のモフォ
ロジーに起因していることが判った。Comparative Example 1 Same as Example 1 except that the intermediate buffer layer was not formed, and the ferroelectric film of 105 nm was formed at 600 ° C. for 60 minutes without dividing the ferroelectric film into two layers. To form a capacitor. This capacitor had too large a leak current value to measure a hysteresis loop. Also, the surface of the ferroelectric film before forming the upper electrode was SEM
FIG. 7 shows the results of the observation. As can be seen from FIG. 7, the film of this comparative example is a film composed of coarse particles and having severe surface irregularities, and it was found that the increase in leak current was caused by the morphology of this surface.
【0026】比較例2 強誘電体膜と下部電極間にバッファ層を設けること以外
は、比較例1と同様にしてキャパシタを形成した。但
し、強誘電体膜の厚さは100nmとした。また、バッ
ファ層は、膜厚5nmの酸化チタンとし、400℃、2
分間MOCVD法により形成した。Comparative Example 2 A capacitor was formed in the same manner as in Comparative Example 1, except that a buffer layer was provided between the ferroelectric film and the lower electrode. However, the thickness of the ferroelectric film was 100 nm. The buffer layer is made of titanium oxide having a thickness of 5 nm,
Formed by MOCVD for one minute.
【0027】また、上部電極形成前の強誘電体膜の表面
をSEMにより観察した結果を図8に示した。図8から
わかるように、この比較例の膜は粒径約0.1μmのグ
レインからなり、表面が緻密で平滑なものであることが
判った。更に、この強誘電体膜の結晶性をX線回折法に
より評価した結果を図9に示した。得られた膜は、ラン
ダム配向のBi4 Ti3 O12であることが示されてい
る。FIG. 8 shows the result of SEM observation of the surface of the ferroelectric film before the formation of the upper electrode. As can be seen from FIG. 8, the film of this comparative example was made of grains having a particle size of about 0.1 μm, and the surface was dense and smooth. FIG. 9 shows the result of evaluating the crystallinity of the ferroelectric film by the X-ray diffraction method. The resulting film is shown to be Bi 4 Ti 3 O 12 with random orientation.
【0028】図10に、このキャパシタの電流電圧特性
を示す。図10では、印加電圧5Vのとき、Il=1×
10-7A/cm2 の値を得ることができた。更に、図1
1に、このキャパシタのヒステリシスループを示した。
上下に非対称なヒステリシスループが得られた。これら
の結果より、この比較例の強誘電体膜被覆基体は表面モ
フォロジーが緻密及び平滑であるため、表面モフォロジ
ーに起因するリーク電流は小さい。しかしながら、上部
及び下部電極を接する材料が異なることに起因するヒス
テリシスループの非対称性が発生していることがわか
る。FIG. 10 shows the current-voltage characteristics of this capacitor. In FIG. 10, when the applied voltage is 5 V, Il = 1 ×
A value of 10 -7 A / cm 2 could be obtained. Further, FIG.
FIG. 1 shows a hysteresis loop of this capacitor.
A vertically asymmetric hysteresis loop was obtained. From these results, since the surface morphology of the ferroelectric film-coated substrate of this comparative example is dense and smooth, the leakage current due to the surface morphology is small. However, it can be seen that the asymmetry of the hysteresis loop occurs due to the different materials that contact the upper and lower electrodes.
【0029】[0029]
【発明の効果】本発明によれば、強誘電体膜の間に中間
緩衝層を配置することにより、従来の基体と強誘電体膜
の間にバッファ層を配置した場合の構造の非対称性に起
因するヒステリシスループの非対称性を防ぐことができ
る。更に、強誘電体膜を緻密化、表面平坦化でき、強誘
電体膜のモフォロジーに起因するリーク電流の発生を防
ぐことができる。According to the present invention, by disposing the intermediate buffer layer between the ferroelectric films, it is possible to reduce the asymmetry of the structure when the buffer layer is disposed between the conventional substrate and the ferroelectric film. The resulting asymmetry of the hysteresis loop can be prevented. Further, the ferroelectric film can be densified and its surface can be flattened, and the generation of a leak current due to the morphology of the ferroelectric film can be prevented.
【図1】本発明のキャパシタの適用例の概略断面図であ
る。FIG. 1 is a schematic sectional view of an application example of a capacitor of the present invention.
【図2】実施例1のキャパシタの概略断面図である。FIG. 2 is a schematic sectional view of a capacitor according to the first embodiment.
【図3】実施例1の第2強誘電体膜の表面のSEM写真
である。FIG. 3 is an SEM photograph of the surface of a second ferroelectric film of Example 1.
【図4】実施例1の第2強誘電体膜のX線回折パターン
である。FIG. 4 is an X-ray diffraction pattern of a second ferroelectric film of Example 1.
【図5】実施例1のキャパシタのリーク電流密度の印加
電圧依存性を示す図である。FIG. 5 is a diagram showing the applied voltage dependence of the leakage current density of the capacitor of Example 1.
【図6】実施例1のキャパシタのヒステリシス曲線を示
す図である。FIG. 6 is a diagram illustrating a hysteresis curve of the capacitor according to the first embodiment.
【図7】比較例1の第2強誘電体膜の表面のSEM写真
である。FIG. 7 is an SEM photograph of the surface of a second ferroelectric film of Comparative Example 1.
【図8】比較例2の第2強誘電体膜の表面のSEM写真
である。FIG. 8 is an SEM photograph of the surface of a second ferroelectric film of Comparative Example 2.
【図9】比較例2の第2強誘電体膜のX線回折パターン
である。FIG. 9 is an X-ray diffraction pattern of a second ferroelectric film of Comparative Example 2.
【図10】比較例2のキャパシタのリーク電流密度の印
加電圧依存性を示す図である。FIG. 10 is a diagram showing the applied voltage dependence of the leak current density of the capacitor of Comparative Example 2.
【図11】比較例2のキャパシタのヒステリシス曲線を
示す図である。FIG. 11 is a diagram showing a hysteresis curve of the capacitor of Comparative Example 2.
1 ビットライン 2 ワードライン 3 トランジスタ 4 絶縁膜 5 下部電極 6 強誘電体膜 7 上部電極 8 キャパシタ 9 配線層 11 シリコン基板 12 酸化シリコン層 13 接着層 14 下部電極 15 第1強誘電体膜 16 中間緩衝層 17 第2強誘電体膜 18 上部電極 Reference Signs List 1 bit line 2 word line 3 transistor 4 insulating film 5 lower electrode 6 ferroelectric film 7 upper electrode 8 capacitor 9 wiring layer 11 silicon substrate 12 silicon oxide layer 13 adhesive layer 14 lower electrode 15 first ferroelectric film 16 intermediate buffer Layer 17 Second ferroelectric film 18 Upper electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/8247 29/788 29/792 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 Identification number Agency reference number FI Technical indication location H01L 21/8247 29/788 29/792
Claims (4)
1強誘電体膜と同種の第2強誘電体膜をこの順で基体上
に備えてなることを特徴とする強誘電体膜被覆基体。1. A ferroelectric material comprising: a first ferroelectric film, an intermediate buffer layer, and a second ferroelectric film of the same type as the first ferroelectric film on a substrate in this order. Film-coated substrate.
1の基体。2. The substrate according to claim 1, wherein the intermediate buffer layer is a metal oxide.
び第2強誘電体膜がBi4 Ti3 O12である請求項1又
は2の基体。3. The substrate according to claim 1, wherein the intermediate buffer layer is titanium oxide, and the first and second ferroelectric films are Bi 4 Ti 3 O 12 .
層、前記第1強誘電体膜と同種の第2強誘電体膜及び前
記同種の上部電極をこの順で基体上に備えてなることを
特徴とするキャパシタ。4. A substrate comprising a lower electrode, a first ferroelectric film, an intermediate buffer layer, a second ferroelectric film of the same type as the first ferroelectric film, and an upper electrode of the same type in this order. A capacitor, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8185548A JPH1012833A (en) | 1996-06-25 | 1996-06-25 | Ferroelectric film covered base and its usage |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8185548A JPH1012833A (en) | 1996-06-25 | 1996-06-25 | Ferroelectric film covered base and its usage |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH1012833A true JPH1012833A (en) | 1998-01-16 |
Family
ID=16172742
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8185548A Pending JPH1012833A (en) | 1996-06-25 | 1996-06-25 | Ferroelectric film covered base and its usage |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH1012833A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000008680A1 (en) * | 1998-08-03 | 2000-02-17 | Nec Corporation | Vapor growth method for metal oxide dielectric film and vapor growth device for metal oxide dielectric material |
KR20000042450A (en) * | 1998-12-24 | 2000-07-15 | 김영환 | Method for fabricating capacitor which can prevent characteristics deterioration of bottom electrode |
JP2005340428A (en) * | 2004-05-26 | 2005-12-08 | Seiko Epson Corp | Piezoelectric element and its manufacturing method |
US7825569B2 (en) | 2001-06-13 | 2010-11-02 | Seiko Epson Corporation | Ceramic and method of manufacturing the same, dielectric capacitor, semiconductor device, and element |
-
1996
- 1996-06-25 JP JP8185548A patent/JPH1012833A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000008680A1 (en) * | 1998-08-03 | 2000-02-17 | Nec Corporation | Vapor growth method for metal oxide dielectric film and vapor growth device for metal oxide dielectric material |
KR20000042450A (en) * | 1998-12-24 | 2000-07-15 | 김영환 | Method for fabricating capacitor which can prevent characteristics deterioration of bottom electrode |
US7825569B2 (en) | 2001-06-13 | 2010-11-02 | Seiko Epson Corporation | Ceramic and method of manufacturing the same, dielectric capacitor, semiconductor device, and element |
US7956519B2 (en) | 2001-06-13 | 2011-06-07 | Seiko Epson Corporation | Piezoelectric device having a ferroelectric film including a solid solution |
US7960901B2 (en) | 2001-06-13 | 2011-06-14 | Seiko Epson Corporation | Piezoelectric device having a ferroelectric film including a ferroelectric material |
JP2005340428A (en) * | 2004-05-26 | 2005-12-08 | Seiko Epson Corp | Piezoelectric element and its manufacturing method |
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