JPH07336702A - Display device - Google Patents

Abstract

PURPOSE:To make a polarization circuit small and to reduce power consumption by allowing a video signal processing side to correct image distortion. CONSTITUTION:A digital video signal received by a video processing circuit 1 is once stored in a digital I/F 101 and written in a frame memory 2 as video data. When a data control circuit 105 reads written data, an arithmetic circuit 3 makes calculation between data read and properly decided under the control of the control circuit 105. Then the shape of image data are corrected so that an image displayed on a cathode ray tube 4 has an image without distortion. Video data generated by the arithmetic circuit 103 are converted into an analog video signal in a D/A converter circuit 104 and the converted signal is outputted to a video circuit. Thus, the scale of a deflection circuit 3 is reduced and the power consumption in the operation is decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as a computer terminal and a video display device such as a television receiver, and more particularly to a display device for simplifying a deflection circuit and reducing operating power.

[0002]

2. Description of the Related Art At present, a display device or a television receiver using a cathode ray tube requires various correction circuits in its deflection circuit in order to display an image on the cathode ray tube without distortion. As such an example, Japanese Patent Laid-Open No. 1957/1993
There are left and right pincushion distortion correction circuits disclosed in Japanese Patent Laid-Open No. 3-38165 and Japanese Patent Laid-Open No. 3-38165. FIG. 21 shows its simple configuration. The configuration shown in FIG.
A power supply modulation circuit 211 and a horizontal output circuit 212. The correction waveform output circuit 210 reads out the correction waveform corresponding to the video signal input to the display device having the pincushion distortion correction circuit, and the readout control is performed by a control circuit such as a microcomputer. The read correction waveform is input to the power supply modulation circuit 211 and modulates the power supply voltage supplied to the horizontal output circuit 212. By the above operation, the horizontal output transistor in the horizontal output circuit 212 drives the horizontal deflection coil by the deflection current modulated by the correction waveform. In the conventional technique, the left and right pincushion distortions are corrected in the above-described manner to obtain the correction accuracy.

Therefore, in the conventional technique, a modulation circuit for modulating a voltage of about 120 V is required, but since this part handles high voltage and large current, it is difficult to miniaturize the IC, especially IC. The deflection current flowing through the horizontal deflection coil is about 10 A, but the amount of current required for the above correction is about 5%, which results in a loss of about 5 W. As described above, in order to correct various screen distortions that occur when an image is displayed on the cathode ray tube on the side of the deflection circuit, control by the high voltage circuit becomes essential, so that the circuit scale and the circuit loss increase.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device which reduces the deflection circuit scale and power consumption during operation.

[0005]

In order to solve the above problems, a video processing means for receiving a video signal and performing signal processing on the video signal, and a video amplification means for amplifying the output of the processing means. A display device is constituted by a video display means for displaying the output of the amplifying means and a deflecting means for driving the video display means based on the synchronizing signal output by the video processing means.

[0006]

The video processing means receives a video signal input to the display device, performs signal processing on the video signal, and corrects image distortion, brightness, color, etc. of the video displayed on the display device. Give. Further, the deflecting means operates simply to drive the image display means. The other means operate similarly to those provided in the conventional display device.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a display device of the present invention. In the figure, the display device includes a video processing circuit 1 for inputting a digital video signal and outputting an analog video signal and a synchronizing signal, a video circuit 2, and a deflection circuit 3 from which various distortion correction circuits are removed.
And a cathode ray tube 4.

In the display device of the first embodiment shown in FIG. 1, the portion constituted by the video circuit 2 and the cathode ray tube 4 has the same structure as the conventional display device, but the deflection circuit 3 has a pincushion distortion. Various correction circuits provided in the conventional deflection circuit such as correction and linearity correction are omitted. The video processing circuit 1 is a circuit for converting a digital signal input into an analog video signal which can be handled by the video circuit 2, corresponding to a future digital video signal. Therefore, in the display device of the present invention, the raster (scanning line) displayed on the cathode ray tube 4 becomes a distorted figure like the conceptual diagram showing the display state of FIG. 2A shows a state of a display image when the display device does not perform correction at all, and FIG. 2B shows a case of the display device of the present invention. It shows a case where distortion correction is performed by video processing when converting a signal to analog. In the present invention, the image processing circuit 1 corrects the image by the image processing so that the image can be correctly displayed on the distorted raster. Furthermore, the video processing circuit 1 is provided with a communication port, and adjustment signals can be exchanged with an adjustment device such as an external computer. The embodiment of the present invention described above has the effect of simplifying the configuration of the deflection circuit unit, which conventionally required a complicated circuit, and reducing power consumption. Further, since the distortion correction processing is performed by the digital signal processing of the video processing circuit 1, the circuit scale can be greatly reduced and the power can be reduced by making this portion an LSI.

FIG. 3 is a block diagram showing details of the video processing circuit 1 of the display device of FIG. 1 according to the present invention.
In the figure, a video processing circuit 1 includes a digital interface circuit 101 (hereinafter, digital I / F) to which a digital video signal is input and a frame memory circuit 102 (hereinafter,
FM), an arithmetic circuit 103 that performs arithmetic processing of data read from the FM 102, a digital / analog conversion circuit (hereinafter, D / A) 104, a control circuit 105 that generates various timing signals and control signals, and a clock signal. And a PLL circuit 106 that generates The digital video signal input to the video signal processing circuit 1 is first stored in the digital I / F 101 and then FM1.
02 as video data. The written data is read out according to the instruction of the control circuit 105, undergoes the correction processing shown in FIG.
Is output to the video circuit 2 of FIG. 1 as an analog video signal. Here, the correction processing of the display screen shown in FIG.
The procedure is as follows. When the control circuit 105 reads out the video data held in the FM 102, the arithmetic circuit 10
3 performs arithmetic operations on appropriately determined data read out under the control of the control circuit 105 so that the image displayed on the cathode ray tube 4 of the display device of FIG. 1 becomes an image without distortion. Correct the shape of. Arithmetic circuit 103
The video data created in 1 is converted into an analog video signal by the D / A 104 and output to the video circuit 2 shown in FIG. As described above, it becomes possible to digitally correct the distortion of the displayed image. Further, in the display device of the embodiment of FIG. 1, since the raster is distorted as shown in FIG. 2, the scanning line intervals may be different between the peripheral portion and the central portion of the screen of the cathode ray tube 4, and the brightness of the displayed image may not be uniform. is there. Therefore, the arithmetic circuit 10 of the video processing circuit 1 shown in FIG.
It is possible to incorporate a brightness correction calculation function corresponding to the display position when performing the distortion correction calculation in 3. Therefore, in the video processing circuit 1 of FIG. 3, not only the geometric distortion of the display video but also the brightness non-uniformity and the balance of the RGB video signals can be controlled to correct the color non-uniformity.

Next, FIG. 4 shows a detailed block diagram of the control circuit 105 described in the video processing circuit 1 of FIG. In the figure, a control circuit 105 includes a look-up table circuit (hereinafter, LUT) 201 that refers to data, and a frame memory control circuit (hereinafter, FMC) 202 that controls the FM 102.
A synchronization generation circuit 203 for outputting a synchronization signal, and a CPU
A circuit 204, a ROM circuit 205, and a communication interface circuit (hereinafter referred to as communication I / F) 206 are included, and each of the above circuits is connected by a data bus 200. The operation of the control circuit 105 in FIG. 4 is as follows.

The ROM 205 stores initial setting values of each circuit connected to the data bus 200 and control software for controlling each circuit, and the CPU 204
LUT based on control software and default settings
For 201, a control data reference value of the arithmetic circuit 103 is generated. The LUT 201 is an F created by the FMC 202.
Control data for arithmetic processing is transferred to the arithmetic circuit 103 of FIG. 3 in accordance with the read address signal of the address signals of M102. Further, the synchronization generation circuit 203 creates a synchronization signal to be supplied to the deflection circuit 3 and outputs a control signal for determining the oscillation frequency of the PLL circuit 106 in FIG. Further, the communication I / F 206 is connected to a computer or an adjusting device outside the display device, transmits / receives an adjusting signal, and writes the received data received as an initial setting value in the ROM 205. Here, the ROM 205
For example, a writable and erasable EEPROM or the like may be used. In the above embodiment, the CPU 204 is the LU
Since the reference value of T201 is managed, even when the resolution of the image to be displayed on the display device of the present invention is changed, it can be easily dealt with by recalculating the reference value by the CPU 204.

Next, FIG. 5 shows a second embodiment of the display device according to the present invention. The display device of FIG. 5 includes a video processing circuit 11 for processing a video signal, a video circuit 2, a deflection circuit 3, and a cathode ray tube 4, and the same reference numerals as those in FIG. 1 have the same functions. .

In addition to the configuration shown in FIG. 1, FIG. 5 further includes a video signal processing circuit 11 corresponding to an analog video signal which has been conventionally used as a video signal input of a display device.

FIG. 6 is a block diagram showing details of the video processing circuit 11. The configuration shown in the figure has an A / D conversion circuit 601 and a second PL in addition to the video processing circuit 1 shown in FIG.
An L circuit 602 and a control circuit 603 different from that of FIG. 3 are provided. The operation and the effect when a digital video signal is input to the video processing circuit 11 are the same as those in FIG.
On the other hand, the conventional analog video signal input to the A / D 601 is sampled (sampled) by the oscillation clock signal of the second PLL circuit 602 and written in the FM 102 as a digital video signal. Second PL circuit 20
Reference numeral 2 generates a clock signal which is synchronized with the horizontal and vertical sync signals input along with the analog video signal. FM1
The write control to 02 is performed by the control circuit 603 which creates a write control signal synchronized with the horizontal and vertical sync signals.
This signal is used. As described above, the display device of the present invention can be applied to the conventional analog video signal.

FIG. 7 shows a video processing circuit portion of a display device showing a third embodiment according to the present invention. The overall configuration of the display device is the same as that shown in FIG. 1. In this embodiment, when distortion correction by the deflection circuit is performed by video processing, processing for increasing the number of scanning lines in the vertical direction is performed in order to suppress image quality deterioration. Is going. The video processing circuit 1 of FIG. 7 is composed of a line memory circuit 301 and other circuits having the same functions as those of FIG. In FIG. 7, distortion correction processing is performed by the arithmetic circuit 103, and the number of vertical scanning lines is multiplied to increase the number of vertical scanning lines included in the video signal input to the video processing circuit 1. The line memory 301 operates as a buffer for holding the video data created by the arithmetic circuit 103 for one line and then outputting it to the D / A 104. The conceptual diagram of FIG. 8 shows an outline of the operation of the display device according to the present invention. In the same figure, conventionally, the surface of the cathode ray tube is scanned and displayed from left to right as shown by the solid line,
During the blanking period, the scanning position is returned from right to left as indicated by the dotted line, and the next scanning line is drawn again. In the present embodiment, the blanking period is reduced, the left and right scanning of the screen is performed within one conventional scanning period, and the number of vertical scanning lines is doubled by reading the image data for two scanning lines. Loss in the deflection circuit can be suppressed more than in the case where the number of scanning lines is simply increased by the conventional deflection method, and it is also effective in reducing unnecessary radiation. When the bidirectional scanning is performed as described above, when the line memory 301 is read out, one line sequentially reads the old data from the new data, and the next line reads the new data from the old data in the reverse order. Alternately control as you say. This control is performed by the control circuit 1
05 is going. As an alternative to the above, FM1
When the video data is read from 02, the read direction may be changed line by line as in the case of the line memory and input to the arithmetic circuit 103. At this time, the line memory 301 operates as a buffer that holds the image-processed image data for a line. Yet another method is
When writing video data to the FM 102, the write address is controlled, and writing is performed in a direction in which the address value increases in a certain line, and conversely in a direction in which the address value decreases in the next line. Next, when reading from the FM 102, no special control of the read address is performed, and if the data is read in the address order as it is, the result is as shown in b of FIG.

Next, FIG. 9 is a block diagram showing the principle of the horizontal deflection circuit of the display device for actually performing bidirectional scanning. The horizontal deflection circuit shown in the figure includes a horizontal synchronization signal input terminal 901 and a switching pulse generation circuit 902.
, Positive power input terminal, switch circuits 904, 905,
And 906, a negative power supply input terminal 907, and a horizontal deflection coil 908.

When the synchronizing signal shown in FIG. 10 is input to the horizontal deflection circuit of FIG. 9, a switching pulse generation circuit 902 is provided.
Outputs the pulses indicated by d, e, and f in FIG. 10 to perform on / off control of the switch circuits 904, 905, and 906, respectively. Then, the horizontal deflection current shown in FIG. 10C flows through the horizontal deflection coil 908, and bidirectional scanning becomes possible.

FIG. 11 shows an embodiment of a vertical deflection circuit for performing the bidirectional scanning shown in FIG. The vertical deflection circuit shown in the figure has a horizontal synchronizing signal input terminal 111, a vertical synchronizing signal input terminal 112, a counter circuit 113, and a D / D circuit.
A114, resistors 115 and 119, and amplifier circuit 11
6, a vertical deflection coil 117, a capacitor 118,
Composed of. The operation of the figure will be described below.

When the horizontal synchronizing signal is input to the horizontal synchronizing signal terminal 111, the counter circuit 113 counts it and sequentially increases the count value. When the vertical synchronizing signal is input to the vertical synchronizing signal input terminal 112, the counter circuit 113 resets the counting result. Therefore, the output obtained by digital-to-analog conversion of the count value of the counter circuit 113 by the D / A 114 becomes a staircase sawtooth wave. By inputting this staircase-shaped vertical sawtooth wave to the amplifier circuit 116 via the resistor 115, a staircase-shaped vertical deflection current as shown in FIG. 12C can be passed through the vertical deflection coil 117. Therefore, vertical scanning can be performed as shown in FIG.

FIG. 13 shows a video processing circuit portion of a display device showing a fourth embodiment for performing the scanning shown in FIG. 8b. The configuration of FIG.
Other circuits having the same reference numerals as those in FIG. 7 and having the same functions. In the figure, the control circuit 131 performs almost the same operation as in FIG. 7, but further creates staircase sawtooth wave data for vertical deflection. The sawtooth wave data created by the control circuit 131 is directly input to the vertical deflection circuit shown in FIG. The vertical deflection circuit of FIG. 14 performs the same operation as that shown in FIG. 11, but the counter circuit 113 of FIG. 11 is omitted because the control circuit 131 creates the stepwise sawtooth wave data.

FIG. 15 is an embodiment showing a video signal processing circuit of the display device shown in FIG. The configuration of the figure is
Second look-up table circuit (hereinafter, LUT) 15
1 and a second digital / analog conversion circuit (hereinafter referred to as D
/ A) 152 and other circuits having the same reference numerals as those in FIG. 3 and exhibiting the same functions. The operation of FIG.
/ F101, FM102, the video data processed through the arithmetic circuit 103 is converted into an analog video signal by the D / A104 and also input to the LUT 151, and the corner of the video displayed on the cathode ray tube 4 in FIG. Luminance correction data for the portion is created by the LUT 151. The brightness correction data becomes an analog correction signal in the second D / A 152,
It serves as a reference voltage input for the D / A 104. The output video signal of the D / A 104 is signal amplitude modulated by the correction signal,
It is possible to correct the brightness of a predetermined part of the display image. Therefore, FIG.
Even if an image is displayed on a distorted raster as shown in b), the difference in brightness between the corner and the center where the density of the scanning lines is different can be corrected, and the image quality is not impaired.

FIG. 16 shows an initial adjustment method for the display device shown in FIG. The configuration shown in FIG. 1 includes the display device shown in FIG. 1, a camera 5 used as an image receiving device, and an adjusting device. In FIG. 16, the adjusting device 6 outputs the adjusting digital video signal to the display device. When the display device processes the input digital video signal and displays it on the cathode ray tube 4, the camera 5 captures the displayed video and outputs it to the adjusting device 6. The adjustment device 6 processes the output of the camera 5, creates an adjustment signal for the image processing circuit 1 of the display device so as to reduce the screen distortion of the display device, and initializes the image processing circuit 1. As described above, the initial setting can be automatically performed, and the subsequent adjustment is unnecessary.

FIG. 17 shows the configuration of the adjustment device 6 shown in FIG. 16, which includes an adjusted video data generation circuit 171, a personal computer (hereinafter PC) 172, a camera interface (hereinafter camera I / F), It consists of. Figure 1
The image captured by the camera 5 in 7 is the camera I / F 1
Input to the PC 172 via 73. The PC 172 arithmetically creates a difference between the captured image and the ideal display state, and outputs an adjustment signal for correcting the image processing circuit 1 of the display device. Further, when the PC 172 sends a control signal to the adjusted video data generation circuit 171 which generates a video signal for adjustment, the adjusted video data generation circuit 171 outputs a digital video signal suitable for adjustment.

FIG. 18 is a block diagram showing another embodiment according to the present invention. The figure comprises a video processing circuit 181, a deflection current detection circuit 182, and other blocks having the same functions as those in FIG. 1 and having the same reference numerals. In the figure, the deflection current detection circuit 182 detects the deflection current flowing in the horizontal and vertical deflection coils, and creates information on the beam scanning position on the tube surface of the cathode ray tube 4. When the deflection current detection circuit 182 outputs this position information to the video processing circuit 181, the video processing circuit 181 performs video processing suitable for the display position and performs screen distortion correction processing and brightness correction.

FIG. 19 is an internal block diagram of the video processing circuit 181 of FIG. The configuration of FIG.
And other circuits having the same reference numerals as those in FIG. 3 and having the same functions. In FIG. 19, a control circuit 191 that receives the position information sent from the deflection current detection circuit 182 and controls so as to correspond to this position is provided. The other circuits operate in exactly the same way as in FIG.

FIG. 20 is a block diagram showing still another embodiment according to the present invention. In the figure, a video processing circuit 21
The cathode ray tube 22 and a circuit having the same functions as those of FIG. In FIG. 20, the cathode ray tube 22 is provided with a photodiode, a phototransistor, a light receiving element such as a solar cell, or an optical sensor along the tube surface. The light receiving element or the like on the cathode ray tube detects the scanning beam and passes the display position information on the tube surface to the video processing circuit 21. The operation of the video processing circuit 21 is the same as in the case of FIG. 18, and the video processing corresponding to the display position information is performed and the screen distortion correction processing is performed.

[0028]

According to the display device of the present invention,
By providing the screen distortion correction circuit with the deflection circuit and performing the distortion correction on the video signal processing side, the power consumption can be suppressed, and the circuit mainly composed of discrete components in the related art can be deleted. Further, since the image distortion is digitally corrected by the video signal processing, the I
The use of C makes it possible to reduce the circuit scale of the correction processing portion and automate the adjustment.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a conceptual diagram showing the operation of the present invention.

FIG. 3 is a block diagram showing a video processing circuit of the first embodiment.

FIG. 4 is a block diagram showing a control circuit of FIG.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a block diagram showing a video processing circuit of a second embodiment.

FIG. 7 is a block diagram showing a second embodiment of the video processing circuit of FIG.

FIG. 8 is a conceptual diagram showing an operation outline according to FIG.

FIG. 9 is a principle block diagram of a horizontal deflection circuit according to the present invention.

10 is a waveform chart showing the operation of FIG.

FIG. 11 is a block diagram of a vertical deflection circuit according to the present invention.

12 is a waveform chart showing the operation of FIG.

FIG. 13 is a block diagram showing a third embodiment of the video processing circuit of FIG.

FIG. 14 is a block diagram of another vertical deflection circuit according to the present invention.

15 is a block diagram showing a fourth embodiment of the video processing circuit of FIG.

FIG. 16 is a block diagram showing a third embodiment according to the present invention.

FIG. 17 is a block diagram showing the adjusting device of FIG. 16.

FIG. 18 is a block diagram showing a fourth embodiment according to the present invention.

19 is a block diagram showing the video processing circuit of FIG. 18. FIG.

FIG. 20 is a block diagram showing a fifth embodiment according to the present invention.

FIG. 21 is a block diagram showing a configuration of a pincushion distortion correction circuit of a conventional display device.

[Explanation of symbols]

1, 11, 181, 21 ... Image processing circuit, 2 ... Video circuit, 3 ... Deflection circuit without distortion correction means, 4, 22 ... Cathode ray tube, 5 ... Camera, 6 ... Adjusting device, 101 ... Digital interface, 102 ... frame memory, 103 ... arithmetic circuit, 104, 114, 152 ... digital / analog conversion circuit, 105, 603, 131, 191 ... control circuit, 106, 602 ... PLL circuit, 113 ... counter circuit, 116 ... amplification circuit, 117 ... Vertical deflection coil, 171 ... Adjusted video data generation circuit, 172 ... Personal computer, 173 ... Camera interface, 182 ... Deflection current detection circuit, 201, 151 ... Lookup table circuit, 202 ... Frame memory control circuit, 203 ... Synchronous generation Circuit, 204 ... CPU, 206 ... Communication interface Esu, 301 ... line memory, 601 ... analog / digital conversion circuit, 902 ... switching pulse generation circuit, 904 to 906 ... switching circuit, 908 ... horizontal deflection coils.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makoto Onozawa 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Stock Company, Hitachi Media Visual Media Research Institute (72) Inventor Michitaka Osawa 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Inside Hitachi Media Media Research Laboratories

Claims (15)

[Claims] 1. A display device for receiving a video signal and performing a display suitable for the video signal, wherein the display device displays image distortion, brightness, and color that occur when the video signal is displayed on a display output means. Video processing means for correcting non-uniformity by signal processing, video amplification means for amplifying the output of the video processing means, display output means for displaying the output of the video amplification means, and output from the video processing means. And a deflection means for driving the display output means on the basis of the synchronizing pulse. 2. A video processing means for receiving a video signal and appropriately displaying the video signal, a video amplifying means for amplifying an output of the video processing means, and an output of the amplifying means. A display device comprising display output means and deflection means for driving the display output means in synchronization with the video signal, wherein the deflection means does not have an image distortion correction function. 3. The display device according to claim 1, wherein the video processing means receives a digital video signal. 4. The display device according to claim 1, wherein the video processing means can receive an analog video signal simultaneously or individually in addition to a digital video signal. 5. The display device according to claim 1, wherein the video processing means performs arithmetic processing of the video signal so that the video displayed on the display output means has a predetermined shape. . 6. A video processing means for receiving a video signal and correcting image distortion and non-uniformity of brightness and color caused by displaying the video signal on a display output means, and the video processing means. A video amplifying means for amplifying the output of the video amplifying means, the display output means for displaying the output of the video amplifying means, and a deflecting means for driving the display output means on the basis of the synchronizing pulse output from the video processing means. In the display device, the video processing means performs processing for improving the image resolution of the video signal in order to improve the correction accuracy performed by the processing means, and the deflection means performs the display so as to correspond to the image resolution. A display device characterized by driving output means. 7. The video processing means according to claim 1, at least a video signal receiving means, a video signal holding means, an arithmetic processing means, a digital / analog converting means, a clock generating means, and a control means. A display device comprising. 8. The control means according to claim 7, wherein the control means includes a calculation coefficient reference means for setting a calculation coefficient to the calculation processing means.
Address control means for controlling the video signal holding means, synchronization pulse generation means for generating a synchronization pulse to be supplied to the deflection means, communication means for communicating with a control device arranged outside the display device, and A display device comprising: a memory means for holding a control procedure of the means and an initial value; and a main control means for controlling each of the means. 9. The display device according to claim 4, wherein the video processing circuit comprises a digital video signal receiving means, an analog / digital converting means for converting an analog video signal into a digital video signal, and a clock for the analog / digital converting means. First clock generating means for supplying a signal, video signal holding means for holding the digital video signal, arithmetic processing means for applying video signal processing to the output of the holding means, and output of the arithmetic processing means for analog video A digital-analog conversion means for converting into a signal, and a second means for supplying a clock signal to the digital-analog conversion means
And a control means for controlling each of the above means. 10. The video processing means according to claim 6, wherein the digital video signal receiving means, the video signal holding means for holding the output of the receiving means, and the arithmetic processing means for applying the video signal processing to the output of the holding means. A line holding means for holding the output of the arithmetic processing means in units of one scanning period; a digital / analog converting means for converting the output of the line holding means into an analog video signal; and a clock signal for the digital / analog converting means. And a control means for controlling each of the above means. 11. A display device according to claim 6, further comprising a horizontal deflecting means for performing left-right bidirectional scanning and a vertical deflecting means for performing staircase wave scanning. 12. The image processing means according to claim 1, further comprising: a receiving means for the digital image signal, an image holding means for holding an output of the receiving means, and an arithmetic processing means for performing an image signal processing by the output of the holding means. A first digital-analog conversion means for converting the output of the arithmetic processing means into an analog video signal; a correction signal reference means for outputting an appropriate correction signal by referring to the output of the arithmetic processing means; A clock signal is output to the second digital-analog converting means for converting the output into an analog voltage and generating the reference voltage of the first digital-analog converting means, and the first and second digital-analog converting means. A display device comprising a clock generating means and a control means for controlling each of the above means. 13. A video processing means for receiving a digital video signal and producing an analog video signal and a synchronizing signal, a video amplification means for amplifying an analog video signal output by the processing means, and an output of the video amplification means. In a display device comprising a video display means for displaying and a deflecting means for driving the display means based on a synchronization signal output from the processing means, a display state of the video display means is measured outside the display device. Arranging a video capturing means and an adjusting means for generating an adjustment signal of the display device from the output of the video capturing means, and outputting the adjustment video signal and the adjustment signal from the adjusting means to the video processing means. Then, the image processing means performs an initial adjustment of the display device. 14. A display device for receiving a video signal and performing a display suitable for the video signal, wherein the display device displays image distortion, brightness, and color that occur when the video signal is displayed on a display output means. Video processing means for correcting non-uniformity by signal processing, video amplification means for amplifying the output of the video processing means, display output means for displaying the output of the video amplification means, and output from the video processing means. A deflection means for driving the display output means on the basis of the synchronizing pulse, and a drive current for the deflection means, and position information corresponding to the display position of the image on the display output means is output to the image processing means. A display device comprising a deflection current detecting means. 15. A display device for receiving a video signal and performing a display suitable for the video signal, wherein the display device displays image distortion, brightness, and color that occur when the video signal is displayed on a display output means. Video processing means for correcting non-uniformity by signal processing, video amplification means for amplifying the output of the video processing means, display output means for displaying the output of the video amplification means, and output from the video processing means. And a deflection means for driving the display output means on the basis of the synchronizing pulse. The display output means outputs the display position information of the video on the detection means to the video processing means and detects the display position of the video. A display device comprising means.