JPH07335882A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a manufacturing method of a semiconductor device wherein MOS characteristics are compatible with high breakdown voltage characteristics. CONSTITUTION:This semiconductor device is provided with a gate electrode 39, S/D regions 40, 41, and an LDD region 34 on a semiconductor substrate 30. The concentration of substrate impurities 37 just under a gate and the impurity concentration 35 in a low concentration drain region or the substrate impurity concentration just under the low concentration drain region are independently controlled. For example, as follows. (1) In a substrate having a concentration suitable for characteristics of an MOS part, the substrate impurity concentration just under an LDD region is controlled, JFET transistor characteristics are controlled, the threshold value adjusting impurity concentration just under the gate electrode is controlled, and characteristics of MOS are controlled. (2) In a substrate having concentration suitable for the JFET part, the concentration of the LDD region is controlled, JFET characteristics are controlled, the impurity concentration of the threshold value adjusting region just under the gate and the concentration of substrate impurity just under the threshold value adjusting region are controlled, and characteristics of MOS are controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, the present invention provides an improved manufacturing method of a high voltage MOS semiconductor device.

[0002]

2. Description of the Related Art Conventionally, in a so-called high withstand voltage transistor, which requires a high voltage to be applied to the drain terminal of an n-channel MOSFET, for example, as shown in the schematic sectional view of FIG. Low concentration n
^- By providing the regions 14, reduces the voltage applied to the drain side end portion of the channel formed under the gate electrode,
It is known to suppress hot carrier generation. In FIG. 13, reference numeral 10 denotes a substrate (here, a P-type substrate),
Reference numeral 20 is a source region, and 21 is a drain region.

A high breakdown voltage transistor having such a structure is
In terms of an equivalent circuit, MOSFET and JF as shown in FIG.
It is represented by the serial connection of ETs. The MOS transistor portion controlled by the gate voltage V _G , and the Junct controlled by the junction characteristic between the n ⁻ region and the substrate P region, respectively.
ion field effect transistor part.

The potential of each part of the high voltage transistor is shown in FIG.
If the symbols V _D , V _D ′, etc. shown in FIG. 14 are used, the current-voltage characteristics are as shown in FIGS. 15 and 16 for MOSFET and JFET, respectively, and the results of the series connection of both are shown. The current-voltage characteristics of the entire high breakdown voltage transistor are expressed as shown in FIG.

As can be seen from these relationships, in order to sufficiently suppress the generation of hot carriers and obtain a high breakdown voltage, J
It is necessary to set the voltage at which the channel of the FET, that is, the n ⁻ region, is completely depleted (pinch off) relatively low. From this, parameters such as n ⁻ region concentration and substrate P region concentration that determine the pinch-off voltage are important design parameters.

However, in the case of the conventional method, the setting of the substrate P region concentration also affects the characteristics of the MOSFET portion, so that it was difficult to freely select a value in terms of design.

18 to 23 show an example of a conventional method of manufacturing a high breakdown voltage transistor. Figure 18
The pad oxide film 11 and the CVDSiN are formed on the P-type substrate 10.
After forming 12, the pattern is formed on the SiN 12.

Next, as shown in FIG. 19, a resist pattern 13 is formed, and using the SiN pattern 12 and this resist pattern 13 as a mask, an n ⁻ region 14 is formed by ion implantation or the like.

Next, FIG. 20 is a diagram after the oxide film 16 is selectively grown using the SiN pattern 12 as a mask.

Next, as shown in FIG. 21, a resist pattern 1
5 are formed and the threshold adjustment impurity region 3 is formed by ion implantation or the like.
Form 7.

Further, as shown in FIG. 22, after forming the gate insulating film (gate oxide film) 18, CVD of poly-Si, etc., the poly-Si gate electrode 19 is patterned.

Next, as shown in FIG. 23, the source region 2
The n ⁺ region of 0 and the drain region 21 is formed to obtain a high breakdown voltage transistor.

[0013]

SUMMARY OF THE INVENTION The present invention relates to a semiconductor device having a MOS transistor structure, and more particularly to a semiconductor device having a gate electrode, a source region and a drain region, and a low-concentration drain region on a semiconductor substrate. It is an object of the present invention to provide a method of manufacturing a semiconductor device that has both high breakdown voltage characteristics.

[0014]

According to the invention of claim 1 of the present application, in a method of manufacturing a semiconductor device having a gate electrode, a source region and a drain region, and a low-concentration drain region on a semiconductor substrate, the semiconductor device is directly under the gate. Of the substrate impurity concentration and the impurity concentration of the low-concentration drain region or the substrate impurity concentration directly under the low-concentration drain region are independently controlled, and the above object is achieved by the method. To do.

According to the invention of claim 2 of the present application, the JFET transistor characteristics are controlled by controlling the substrate impurity concentration immediately below the low-concentration drain region on a semiconductor substrate having a substrate concentration matched to the characteristics of the MOS transistor portion, and controlling the gate. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the characteristics of the MOS transistor are controlled by controlling the concentration of the threshold adjustment impurity region immediately below the electrode, which achieves the above object. Is.

According to the invention of claim 3 of the present application, the JF is controlled by controlling the impurity concentration of the low-concentration drain region in a semiconductor substrate having a substrate concentration matching the characteristics of the JFET transistor portion.
2. The semiconductor device according to claim 1, wherein the characteristics of the MOS transistor are controlled by controlling the characteristics of the ET transistor and by controlling the concentration of the threshold adjustment impurity region immediately below the gate electrode and the concentration of the substrate impurity immediately thereunder. A manufacturing method for achieving the above object.

[0017]

According to the present invention, since the substrate impurity concentration directly under the gate and the substrate impurity concentration under the low-concentration drain region or under the drain region are independently controlled, design parameters for increasing the withstand voltage can be set arbitrarily. This makes it possible to improve the high breakdown voltage while maintaining the MOS transistor characteristics.

[0018]

EXAMPLES The present invention will be described in detail below with reference to examples, but the present invention is not limited to the examples described below.

Embodiment 1 FIGS. 1 to 6 show a first example of a method for manufacturing a high breakdown voltage transistor according to the present invention.

The process of this embodiment will be briefly described. In this embodiment, a semiconductor substrate 30 as shown in FIG. 6 is provided with a gate electrode 39, a source region 40 and a drain region 41, and a low concentration drain region 34. In the method of manufacturing a semiconductor device, the concentration of the substrate impurity 37 immediately below the gate electrode 39 and the concentration of the substrate impurity 35 immediately below the low-concentration drain region 34 are independently controlled. That is, in the process of FIG. 2, the concentration of the substrate impurity (P region) 35 immediately below the low concentration drain region 34 is controlled. Further, in the process of FIG. 4, the concentration of the substrate impurity 37 immediately below the gate is controlled.

The process of this embodiment will be described in more detail below. FIG. 1 shows a state in which a pad oxide film 31 and a CVDSiN 32 are formed on a P-type substrate 30 having a substrate concentration matching the characteristics of the MOS transistor portion, and then a pattern is formed on the SiN 32.

Next, as shown in FIG. 2, a resist pattern 33 is formed, and the SiN pattern 32 and the resist pattern 33 are used as a mask to ion-implant the n ⁻ region 34 and the P region 35 deeper than the n ⁻ region 34. Form. The n ⁻ region 34 and the P region 35 are formed by JFE.
It is a parameter for designing the T characteristic.

Next, FIG. 3 is a diagram after the oxide film 36 is selectively grown using the SiN pattern 32 as a mask.

Further, as shown in FIG. 4, impurity implantation for adjusting the threshold value of the MOS transistor is performed. Thereby, the MOS transistor characteristics can be designed by setting the concentration of the P-type substrate 30 and the concentration of the threshold adjustment impurity region 37.

FIG. 5 shows the gate insulating film 38, poly-SiCV.
It is a figure after patterning the gate electrode 39 after D etc.

Next, as shown in FIG. 6, the source region 40
Then, the n ⁺ region of the drain region 41 is formed to obtain a high breakdown voltage transistor.

According to this embodiment, the substrate concentration of the JFET portion and MOSFET portion of the high breakdown voltage transistor structure can be set independently.

Regarding the substrate concentration, as a way of designing the MOSFET portion, it is preferable to make the concentration low from the viewpoint of the subthreshold characteristic, the substrate bias effect, etc., while avoiding problems such as punch through. On the other hand, JF
As a design concept of the ET section, it is desirable to lower the pinch-off voltage, and it is necessary to make the n ⁻ region easily depleted.

Now, assuming that the junction formed by the n ⁻ region of the JFET portion and the P substrate has a stepwise concentration distribution,
When the n ⁻ region concentration is N _D , the P substrate concentration is N _A, and the potentials applied to them are V _D and V _B , the extension width dn of the depletion layer to the n ⁻ region is expressed as follows.

[Equation 1] Therefore, it can be seen that it is sufficient to increase N _{A in order} to increase dn while keeping N _D at a constant value. Therefore, in the case of the above-mentioned first example of the present invention, a relatively low-concentration P substrate is used in conformity with the MOSFET part, and in the JFET part, a relatively high-concentration P region is formed in the P substrate to reduce the pinch off voltage. It becomes possible to form a high breakdown voltage transistor which has a low resistance and is excellent in hot carrier resistance and the like.

Embodiment 2 FIGS. 7 to 12 show a second example of a method for manufacturing a high breakdown voltage transistor which is provided for the same purpose as described above.

FIG. 7 shows a pad oxide film 51, C on a P-type substrate 50 having a substrate concentration matching the characteristics of the JFET portion.
It is a figure which shows the state which performed pattern formation with respect to SiN52, after forming the VDSiN film 52. FIG.

Next, as shown in FIG. 8, using the SiN pattern 52 and the resist pattern 53 as a mask, n
^-The region 54 is formed by ion implantation or the like. These n ^-
The formation of the region 54 and the setting of the P-type substrate 50 are parameters for designing JFET characteristics.

FIG. 9 is a diagram after the oxide film 55 is selectively grown using the SiN pattern 52 shown in FIGS. 7 and 8 as a mask.

Next, as shown in FIG. 10, the oxide film 55 and the resist pattern 56 are used as masks to ion-implant the threshold adjusting impurity region 57 of the MOS transistor and the impurity region 58 for adjusting the impurity concentration deeper than the threshold adjusting impurity region 57. Form. As described in Example 1, JF
From the design of ET characteristics, assuming that a P-type substrate 50 having a relatively high concentration is used, the impurity region 58 can be made into a P-type low concentration region by performing donor type ion implantation. These are parameters for designing MOS transistor characteristics.

11 and 12 show the same steps as those in FIGS. 5 and 6 in the first embodiment. 5 in each figure
Reference numeral 9'denotes a gate insulating film, 59 a gate electrode, 60 a source region, and 61 a drain region.

This embodiment has the same effects as the first embodiment. Furthermore, in the case of the present embodiment, after the PFET substrate having a relatively high concentration is used to lower the pinch-off voltage of the JFET portion,
By introducing a donor impurity for compensating the P substrate acceptor impurity into the MOSFET portion, the effective substrate concentration can be lowered and the subthreshold characteristic substrate bias effect and the like can be improved.

[0037]

As described above, according to the present invention, the MO
Manufacture of a semiconductor device having an S-transistor structure, particularly a semiconductor device having a gate electrode, a source region and a drain region, and a low-concentration drain region on a semiconductor substrate, having both MOS transistor characteristics and high breakdown voltage characteristics. Could provide a way.

[Brief description of drawings]

1A to 1C are sectional views showing steps of Example 1 in order (1).

2A to 2C are sectional views showing the steps of Example 1 in order (2).

FIG. 3 is a sectional view showing the steps of Example 1 in order (3).

FIG. 4 is a sectional view showing the steps of Example 1 in order (4).

FIG. 5 is a sectional view showing the steps of Example 1 in order (5).

FIG. 6 is a sectional view showing the steps of Example 1 in order (6).

FIG. 7 is a sectional view showing the steps of Example 2 in order (1).

8A to 8C are sectional views showing the steps of Example 2 in order (2).

FIG. 9 is a sectional view showing the steps of Example 2 in order (3).

10A to 10C are sectional views showing the steps of Example 2 in order (4).

FIG. 11 is a sectional view showing the steps of Example 2 in order (5).

FIG. 12 is a sectional view showing the steps of Example 2 in order (6).

FIG. 13 is a diagram showing a conventional technique.

FIG. 14 is a diagram showing a conventional technique.

FIG. 15 is a diagram illustrating characteristics of a high breakdown voltage transistor.

FIG. 16 is a diagram illustrating characteristics of a high breakdown voltage transistor.

FIG. 17 is a diagram illustrating characteristics of a high breakdown voltage transistor.

FIG. 18 is a diagram illustrating characteristics of a high breakdown voltage transistor.

[Explanation of symbols]

30, 50 Semiconductor substrate 31, 51 Pad oxide film 32, 52 SiN pattern 33, 53 Resist pattern 34, 54 n ^- region (JFET characteristic setting parameter) 35 P region (JFET characteristic setting parameter) 36, 55 Oxide film 37, 57 Threshold adjustment impurity region (MOS transistor characteristic setting parameter) 58 Impurity region (MOS transistor characteristic setting parameter) 38, 59 'Gate insulating film 39, 59 Gate electrode 40, 60 Source region 41, 61 Drain region

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[Procedure amendment]

[Submission date] October 31, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

1A to 1C are sectional views showing steps of Example 1 in order (1).

2A to 2C are sectional views showing the steps of Example 1 in order (2).

FIG. 3 is a sectional view showing the steps of Example 1 in order (3).

FIG. 4 is a sectional view showing the steps of Example 1 in order (4).

FIG. 5 is a sectional view showing the steps of Example 1 in order (5).

FIG. 6 is a sectional view showing the steps of Example 1 in order (6).

FIG. 7 is a sectional view showing the steps of Example 2 in order (1).

8A to 8C are sectional views showing the steps of Example 2 in order (2).

FIG. 9 is a sectional view showing the steps of Example 2 in order (3).

10A to 10C are sectional views showing the steps of Example 2 in order (4).

FIG. 11 is a sectional view showing the steps of Example 2 in order (5).

FIG. 12 is a sectional view showing the step of the second embodiment in order (6).

FIG. 13 is a diagram showing a conventional technique.

FIG. 14 is a diagram showing a conventional technique.

FIG. 15 is a diagram illustrating characteristics of a high breakdown voltage transistor.

FIG. 16 is a diagram illustrating characteristics of a high breakdown voltage transistor.

FIG. 17 is a diagram illustrating characteristics of a high breakdown voltage transistor.

FIG. 18 is a sectional view showing the steps of the conventional example in order.
(1).

FIG. 19 is a sectional view showing the steps of the conventional example in order.
(2).

FIG. 20 is a sectional view showing the steps of the conventional example in order.
(3).

FIG. 21 is a sectional view showing the steps of the conventional example in order.
(4).

FIG. 22 is a sectional view showing the steps of the conventional example in order.
(5).

FIG. 23 is a sectional view showing the steps of the conventional example in order.
(6).

[Explanation of reference numerals] 30, 50 Semiconductor substrate 31, 51 Pad oxide film 32, 52 SiN pattern 33, 53 Resist pattern 34, 54 n-region (JFET characteristic setting parameter) 35 P region (JFET characteristic setting parameter) 36, 55 Oxide film 37, 57 Threshold adjustment impurity region (MOS transistor characteristic setting parameter) 58 Impurity region (MOS transistor characteristic setting parameter) 38, 59 'Gate insulating film 39, 59 Gate electrode 40, 60 Source region 41, 61 Drain region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/80 H01L 29/78 301 H 9171-4M 29/80 E 9171-4M

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device comprising a gate electrode, a source region and a drain region, and a low-concentration drain region on a semiconductor substrate, wherein the substrate impurity concentration immediately below the gate and the impurity concentration in the low-concentration drain region are A method of manufacturing a semiconductor device, characterized in that the substrate impurity concentration immediately below the low-concentration drain region is independently controlled. 2. A semiconductor substrate having a substrate concentration matching the characteristics of a MOS transistor portion, the substrate impurity concentration immediately below the low-concentration drain region is controlled to control the JFET transistor characteristics, and the threshold adjustment impurity immediately below the gate electrode. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the characteristics of the MOS transistor are controlled by controlling the concentration of the region. 3. A semiconductor substrate having a substrate concentration matching the characteristics of a JFET transistor portion, the impurity concentration of a low-concentration drain region is controlled to control the JFET transistor characteristics, and a threshold adjusting impurity region immediately below a gate electrode and 2. The method for manufacturing a semiconductor device according to claim 1, wherein the characteristics of the MOS transistor are controlled by controlling the concentration of the substrate impurity immediately below the substrate impurity.