KR100290874B1 - Method for manufacturing mosfet - Google Patents
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- KR100290874B1 KR100290874B1 KR1019930004107A KR930004107A KR100290874B1 KR 100290874 B1 KR100290874 B1 KR 100290874B1 KR 1019930004107 A KR1019930004107 A KR 1019930004107A KR 930004107 A KR930004107 A KR 930004107A KR 100290874 B1 KR100290874 B1 KR 100290874B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 2
- 239000010408 film Substances 0.000 claims 9
- 230000000873 masking effect Effects 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 150000004767 nitrides Chemical class 0.000 description 7
- 230000002265 prevention Effects 0.000 description 4
- 239000008186 active pharmaceutical agent Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
Abstract
Description
[발명의 명칭][Name of invention]
모스펫(MOSFET) 제조방법MOSFET manufacturing method
[도면의 간단한 설명][Brief Description of Drawings]
제 1 도는 종래의 MOSFET 구조단면도.1 is a cross-sectional view of a conventional MOSFET structure.
제 2 도는 종래의 MOSFET 공정단면도2 is a cross-sectional view of a conventional MOSFET process
제 3 도는 본 발명의 MOSFET 구조단면도.3 is a cross-sectional view of a MOSFET structure of the present invention.
제 4 도는 본 발명의 MOSFET 공정단면도.4 is a cross-sectional view of a MOSFET process of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 필드산화막 3 : 게이트 전극Reference Signs List 1 substrate 2 field oxide film 3 gate electrode
4,4a,4b : 게이트 산화막 5 : 소오스/드레인 영역4,4a, 4b: gate oxide film 5: source / drain region
5b : 드레인 영역 6 : 버퍼용 산화막 7 : 질화막5b Drain region 6: Oxide film for buffer 7: Nitride film
[발명의 상세한 설명]Detailed description of the invention
본 발명은 MOSFET(Metal Oxide Semiconductor Field Effect Transistor) 제조방법에 관한 것으로서, 특히 GIDL(Gate Induced Drain Leakage) 방지 구조에서의 트랜지스터 특성을 개선시키기 위한 MOSFET 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a metal oxide semiconductor field effect transistor (MOSFET), and more particularly to a method of manufacturing a MOSFET for improving transistor characteristics in a gate induced drain leakage (GIDL) prevention structure.
종래의 GIDL 방지 구조의 MOSFET 구조 및 제조방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, a MOSFET structure and a manufacturing method of a conventional GIDL prevention structure are as follows.
제 1 도는 종래의 GIDL 방지 구조의 MOSFET 구조단면도이고, 제 2 도는 제 1 도의 공정단면도로써, 종래의 GIDL 방지용 MOSFET의 구조를 실리콘 기판(1)에 필드 산화막(2)이 형성되고, 액티브영역에 실리콘 기판(1)과 격리되어 게이트 전극(3)이 형성되고, 게이트 전극(3)과 실리콘 기판(1) 사이의 게이트 절연막(4)이 게이트 전극(3)의 모서리부분이 더 두껍게 형성되고, 게이트 전극(3) 양측의 실리콘 기판(1)에 LDD구조의 소오스/드레인 영역(5)이 형성된 구조이다.FIG. 1 is a cross-sectional view of a MOSFET structure of a conventional GIDL prevention structure, and FIG. 2 is a cross-sectional view of the process structure of FIG. 1, in which a field oxide film 2 is formed on a silicon substrate 1 in a structure of a conventional GIDL prevention MOSFET. The gate electrode 3 is formed by isolation from the silicon substrate 1, the gate insulating film 4 between the gate electrode 3 and the silicon substrate 1 is formed to have a thicker edge portion of the gate electrode 3, The source / drain regions 5 of the LDD structure are formed in the silicon substrate 1 on both sides of the gate electrode 3.
이와 같은 구조의 종래의 MOSFET 제조방법은 제 2 도(a)와 같이, 실리콘 기판(1)에 필드 산화막(2)을 성정하고, 전면에 버퍼용 산화막(6)을 성장시킨 후 문턱전압 조절을 위한 이온을 주입한다.In the conventional MOSFET manufacturing method having such a structure, as shown in FIG. 2 (a), the field oxide film 2 is formed on the silicon substrate 1, the buffer oxide film 6 is grown on the entire surface, and then the threshold voltage is adjusted. Inject ions for
제 1 도(b)와 같이, 버퍼용 산화막(6)을 제거하고 질화막(7)으로 게이트가 형성될 부위에 마스크를 형성한다.As shown in FIG. 1 (b), the buffer oxide film 6 is removed and a mask is formed on the portion where the gate is to be formed by the nitride film 7.
그리고 제 1 도(c)와 같이, GIDL 방지용 제 1 게이트 산화막(4a)을 두껍게 성장시키고 질화막(7)을 제거한 후, 제 1 도(d)와 같이, 질화막(7)이 제거된 부위에 제 2 게이트 산화막(4b)을 얇게 성장시킨다.Then, as shown in FIG. 1 (c), the first gate oxide film 4a for preventing GIDL is grown thick and the nitride film 7 is removed, and as shown in FIG. The two-gate oxide film 4b is grown thin.
계속해서 제 1 도(e)와 같이, 실리콘을 증착하고 패터닝하여 모서리 부분이 두꺼운 제 1 게이트 산화막(4a)위가 되도록 게이트 전극(3)을 형성한 뒤 소오스/드레인 영역에 저농도 n형 이온주입을 하고 제 1 도(f)와 같이, 게이트 전극(3)에 측벽 산화막(8)을 형성하고 소오스/드레인 영역에 고농도 n형 이온주입하여 LDD구조의 소오스/드레인 영역(5)을 형성한다.Subsequently, as shown in FIG. 1 (e), silicon is deposited and patterned to form the gate electrode 3 so as to be on the first gate oxide film 4a having a thick edge portion, and then a low concentration n-type ion implantation into the source / drain regions. As shown in FIG. 1 (f), the sidewall oxide film 8 is formed in the gate electrode 3, and the high concentration n-type ion is implanted into the source / drain region to form the source / drain region 5 of the LDD structure.
그러나 이와 같은 종래의 GIDL 방지용 MOSFET 구조 및 제조방법에 있어서는 소오스영역에서도 드레인 영역과 마찬가지로 게이트 전극(3)의 모서리 부분 게이트 산화막이 두꺼워지므로 트랜스 콘덕턴스(Transconductance)가 감소하여 드레인-소오스간 전류(IDS)가 감소될 우려가 있으며 기판저항을 통한 전압강하(Rsub, Isub)가 FET에서 포지티브 백 바이어스(Positive Back Bias)로 작용하여 이 포지티브 백 바이어스가 소오스 전류(Is)를 증가시키고, 따라서 기판전류(Isub)도 증가한다.However, in the conventional GIDL-preventing MOSFET structure and manufacturing method, the edge region gate oxide film of the gate electrode 3 becomes thicker in the source region as in the drain region, so that the transconductance is reduced and the drain-to-source current I DS ) is likely to decrease and the voltage drop (R sub , I sub ) through the substrate resistance acts as a positive back bias in the FET, which increases the source current Is. The substrate current I sub also increases.
이 현상이 누적되어 소오스와 기판간 정션(Junction)이 턴온(Turn-on)되어서 소오스-기판-드레인으로 이어지는 바이폴라 트랜지스터가 턴온되어 드레인 전류가 급격히 증가하며 블랙다운(Breakdown)되는 스냅-백-블랙다운 전압(Snap-Back-Breakdown Voltage) 특성 등이 저하될 우려가 있다.This phenomenon accumulates and the junction between the source and the substrate is turned on and the bipolar transistor leading to the source-substrate-drain turns on, leading to a sharp increase in drain current and black-down snap-back-black. There may be a decrease in the characteristics of a snap-back-breakdown voltage.
본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로서 GIDL 발생을 억제함과 동시에 드레인-소오스간 전류(IDS)와 스냅-백 블랙다운 전압을 증가시키는 MOSFET의 제조방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a MOSFET which suppresses generation of GIDL and increases a drain-source current (I DS ) and a snap-back blackdown voltage. .
이와 같은 목적을 달성하기 위한 본 발명은 드레인 쪽의 게이트 산화막은 두껍게 하고 소오스 영역쪽의 게이트 산화막을 얇게 한 것으로 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다.The present invention for achieving the above object is to thicken the gate oxide film on the drain side and to thin the gate oxide film on the source region side in more detail with reference to the accompanying drawings as follows.
제 3 도는 본 발명의 MOSFET 구조단면도이고 제 4 도는 본 발명의 MOSFET 공정단면도로서, 본 발명의 MOSFET 구조는 실리콘 기판(1)에 필드 산화막(2)이 형성되고 활성영역 소정부위에 게이트 전극(3)이 형성되고 게이트 전극(3) 양측 실리콘 기판(1)에 LDD구조의 소오스 영역(5a)과 드레인 영역(5b)이 형성되고, 게이트 전극(3)과 실리콘 기판(1) 사이에 게이트 산화막(4)이 형성되고 게이트 전극(3) 양측에 측벽 산화막(8)이 형성된 구조이다.3 is a cross-sectional view of the MOSFET structure of the present invention and FIG. 4 is a cross-sectional view of the MOSFET process of the present invention, in which the MOSFET structure of the present invention is formed with a field oxide film 2 on the silicon substrate 1 and the gate electrode 3 at a predetermined portion of the active region. ), A source region 5a and a drain region 5b of the LDD structure are formed in the silicon substrate 1 on both sides of the gate electrode 3, and a gate oxide film () is formed between the gate electrode 3 and the silicon substrate 1. 4) is formed and the sidewall oxide film 8 is formed on both sides of the gate electrode 3.
여기서 게이트 산화막(4)은 드레인 영역(5b)쪽의 게이트 전극(3) 모서리 부분이 다른쪽보다 더 두껍게 형성된다.Here, the gate oxide film 4 is formed with a thicker edge portion of the gate electrode 3 on the drain region 5b side than the other side.
이와같은 구조의 본 발명의 MOSFET의 제조방법은 제 4 도(a)와 같이, 실리콘 기판(1)에 필드 산화막(2)을 성장하고 버퍼용 산화막(6)을 성장시킨 후 문턱전압 조절을 위한 이온주입을 실시한다.In the method of manufacturing the MOSFET of the present invention having the above structure, as shown in FIG. 4 (a), the field oxide film 2 is grown on the silicon substrate 1, the buffer oxide film 6 is grown, and then the threshold voltage is controlled. Ion implantation is performed.
제 4 도(b)와 같이, 버퍼용 산화막(6)을 제거한 후 질화막(7)을 1000~2000Å정도의 두께로 증착하고 드레인 영역의 질화막(7)을 제거하여 소오스 영역과 게이트 영역에 마스크를 형성한다.As shown in FIG. 4 (b), after the buffer oxide film 6 is removed, the nitride film 7 is deposited to a thickness of about 1000 to 2000 GPa, and the nitride film 7 in the drain region is removed to apply a mask to the source and gate regions. Form.
제 4 도(c)와 같이, 질화막(7)이 제거된 부분이 GIDL방지용 제 1 게이트 산화막(4a)을 두껍게 성장시키고 제 4 도(d)와 같이, 질화막(7)을 제거한 뒤 그 부분에 제 2 게이트 산화막(4b)을 얇게 성장시킨다.As shown in FIG. 4 (c), the portion where the nitride film 7 is removed grows thickly the first gate oxide film 4a for preventing GIDL, and as shown in FIG. 4 (d), after removing the nitride film 7, The second gate oxide film 4b is grown thin.
그리고 제 4도(e)와 같이, 게이트 폴리실리콘을 증착하고 패터닝하여 제 1 게이트산화막(4a)과 제 2 게이트 산화막(4b)의 계면이 드레인 영역쪽의 게이트 모서리에 오도록 게이트 전극(3)을 형성한 다음 소오스/드레인 영역에 저농도 n형 불순물을 이온주입하고, 제 4 도(f)와 같이, 게이트 전극(3)에 측벽산화막(8)을 형성하고 소오스/드레인 영역에 고농도 n형 불순물을 이온주입하여 LDD구조의 소오스 영역(5a)과 드레인 영역(5b)을 형성한다.As shown in FIG. 4E, the gate polysilicon is deposited and patterned to form the gate electrode 3 so that the interface between the first gate oxide film 4a and the second gate oxide film 4b is at the gate edge of the drain region. After forming, ion-implanted low-concentration n-type impurities into the source / drain regions, and as shown in FIG. 4 (f), a sidewall oxide film 8 is formed on the gate electrode 3 and high-concentration n-type impurities are formed in the source / drain regions. Ion implantation forms the source region 5a and the drain region 5b of the LDD structure.
이상에서 설명한 바와 같이 본 발명의 MOSFET의 제조방법에 있어서는 게이트 전극(3)과 드레인 영역(5b)이 겹치는 부분의 게이트 산화막 두께를 두껍게 형성함으로서 게이트 전극과 드레인이 겹치는 부분의 수직방향의 전계(Electric Field)를 감소시켜 기판과 드레인 사이의 밴드 벤딩(Band Bending)을 감소시키고, 따라서 밴드-투-밴드(Band-To-Band) 터널링(Tunneling)이 감소되어 GIDL을 방지하게 된다.As described above, in the method of manufacturing the MOSFET of the present invention, the gate oxide film thickness of the portion where the gate electrode 3 and the drain region 5b overlap is formed to be thick so that the electric field in the vertical direction of the portion where the gate electrode and the drain overlap. Field is reduced to reduce band bending between the substrate and the drain, and thus band-to-band tunneling is reduced to prevent GIDL.
동시에 게이트 전극과 소오스 영역이 겹치는 부분의 게이트 산화막 두께는 채널 중앙부와 같이 얇게 형성함으로서, 드레인 영역쪽의 두꺼운 게이트 산화막에 의해 트랜스 콘덕턴스가 감소하여 드레인-소오스 전류(IDS)가 저하되는 것을 방지한다.At the same time, the gate oxide film thickness of the portion where the gate electrode overlaps with the source region is formed to be as thin as the center portion of the channel, thereby preventing the transconductance from being reduced by the thick gate oxide film at the drain region, thereby preventing the drain-source current I DS from decreasing. do.
또한, 소오스 기판 사이의 저항을 감소시켜 소오스-기판간의 전압 드롭(Voltage Drop)을 감소시키므로 기생바이폴라 트랜지스터의 턴온을 늦추게 되어 스냅-백 블랙다운 전압 특성을 향상시킬 수 있는 등의 효과가 있다.In addition, since the resistance between the source substrates is reduced to reduce the voltage drop between the source and the substrate, the turn-on of the parasitic bipolar transistor can be delayed to improve the snap-back blackdown voltage characteristics.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930004107A KR100290874B1 (en) | 1993-03-17 | 1993-03-17 | Method for manufacturing mosfet |
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| KR1019930004107A KR100290874B1 (en) | 1993-03-17 | 1993-03-17 | Method for manufacturing mosfet |
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| KR940022919A KR940022919A (en) | 1994-10-22 |
| KR100290874B1 true KR100290874B1 (en) | 2001-10-24 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030044343A (en) * | 2001-11-29 | 2003-06-09 | 주식회사 하이닉스반도체 | Transistor in a semiconductor device and a method of manufacturing the same |
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| DE19926767A1 (en) * | 1999-06-11 | 2000-12-21 | Infineon Technologies Ag | Ferroelectric transistor and method for its production |
| JP2001358233A (en) * | 2000-06-15 | 2001-12-26 | Hitachi Ltd | Semiconductor integrated circuit device and its manufacturing method |
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| KR20030044343A (en) * | 2001-11-29 | 2003-06-09 | 주식회사 하이닉스반도체 | Transistor in a semiconductor device and a method of manufacturing the same |
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