JPH07335863A - Mos-controlled semiconductor device - Google Patents

Abstract

PURPOSE:To lower the ON voltage of a semiconductor device which is ON/OFF controlled with an insulated gate electrode, and reduce the resistance loss. CONSTITUTION:A first thyristor region and a second thyristor region are arranged in the same semiconductor substrate, so as to isolate the P base layers 162, 152 of each of the thyristors. The N emitter 161 of the first thyristor is connected with the cathode electrode via only the one out of channels of an MOSFET M1. Thereby the N emitters of the first thyristor and the second thyristor are connected together by an electrode 5 isolated from the cathode electrode. Since the first thyristor is connected with the cathode electrode via only one MOSFET, the amount of carrier in a semiconductor device can be increased, and the ON voltage can be lowered.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS control type semiconductor device, and more particularly, to an MO with a low on-voltage and a low loss.
The present invention relates to an S control type semiconductor device.

[0002]

2. Description of the Related Art As a conventional technique relating to a MOS control type semiconductor device, for example, an IGBT (Insulated Gate B) which is a voltage driving type switching element having an insulated gate electrode is used.
ipolarTransistor) etc. are known. This IGBT
Has a problem that the voltage drop during conduction is larger than that of a GTO thyristor.

Therefore, as a semiconductor device capable of reducing the voltage drop when conducting, it is a voltage drive type semiconductor device having an insulated gate electrode, and the voltage drop (ON voltage) when conducting is smaller than that of the IGBT. A semiconductor device that controls a thyristor with an insulated gate is possible, for example, by I.S.P.S.D. (1992).
256-260 (Proceedings of 1992 Inter na
tional Synposium onPower semiconductor Device & I
Cs, Tokyo, pp. 256-260) and the like.

FIG. 8 is a sectional view for explaining the structure of the above-mentioned conventional semiconductor device, and FIG. 9 is a view for explaining an equivalent circuit of the conventional semiconductor device.

The illustrated semiconductor device has a main surface 5 of a semiconductor substrate.
11 adjacent to the n − layer 500, an n layer 501 adjacent to the n − layer 500 and having a higher impurity concentration than that, a p 1 + layer 502 adjacent to the n layer 501 and the main surface 512 and having a higher impurity concentration than the n layer 501, P2 + layer 50 extending from main surface 511 into n- layer 500 and having a higher impurity concentration than n- layer 500
7. Adjacent to the p2 + layer 507 from the main surface 511 to the n- layer 50
P − layer 508 extending into 0 and having an impurity concentration between n − layer 500 and p 2 + layer 507, from main surface 511 to p 2 + layer 5
07 and p− layer 508, which has a higher impurity concentration than the p2 + layer 507, and extends from the main surface 511 into the p− layer 508 at a location remote from the n1 + layer 505 and the n1 + layer 505.
-N2 + layers 506, n having a higher impurity concentration than the layer 508
Cathode electrode 5 in contact with 1+ layer 505 and p2 + layer 507
09, the anode electrode 510 in contact with the p1 + layer 502, n
The p- layer 50 exposed between the 1+ layer 505 and the n2 + layer 506
Electrode 5 formed on the exposed surface of No. 8 via an insulating film 503
First insulated gate G1, n-layer 500 and n2 +
The second insulated gate G2 is composed of the electrode 504 formed on the exposed surface of the p − layer 508 exposed between the layer 506 and the insulating film 503.

This semiconductor device has a p1 + layer 502, an n- layer 500, and a p- layer 5 as shown in the equivalent circuit of FIG.
08 pnp transistor Q1 and n-layer 50
A thyristor composed of an npn transistor Q2 including 0, p − layer 508 and n 2+ layer 506 is built in a lower layer portion between the first and second insulated gate electrodes G1 and G2. In addition, this semiconductor device has the first insulated gate G1, the n1 + layer 505, the p− layer 508, and the n2 + layer 506.
N-channel MISFET M1 composed of the second insulated gate G2, n2 + layer 506, p- layer 508, and n- layer 500
And an n-channel MISFET M2 composed of the above are provided in a lower layer portion including the first and second insulated gate electrodes G1 and G2. Further, this semiconductor device uses n as a parasitic element.
The transistor Q4 including the 1+ layer 505, the p2 + layer 507, and the n− layer 500, and the p2 + layer 507, the n− layer 500, and the p1 + layer 5
A parasitic thyristor including a transistor Q3s of 0 is included in the lower layer portion of the cathode electrode 509.

The operation principle will be described below with reference to FIGS. 8 and 9.

In order to turn on the semiconductor device described above, first, a negative potential is applied to the cathode electrode K509 and a positive potential is applied to the anode electrode A510, and the cathode electrodes are applied to the first and second insulated gate electrodes G1 and G2. A potential larger than the potential of K509 is applied to the positive side. As a result, the p − layer 5 under the first and second insulated gate electrodes G1 and G2 is formed.
An inversion layer is formed on the surface of 08, and the n1 + layer 505 and the n2 + layer 506 and the n2 + layer 506 and the n− layer 500 are short-circuited, and the n channel MISFET M1 and the n channel MI are formed.
SFET M2 turns on.

As a result, from the cathode electrode K509 to the n-channel MISFET M1 and the n-channel MISFET.
The electrons (MIS current) injected through M2 are n-
After passing through the layer 500 and flowing into the p1 + layer 502, holes are injected from the p1 + layer 502 into the n− layer 500 through the n layer 501. This hole current is the p − layer 508.
And reaches the cathode electrode K509 through the lower part of the first insulated gate electrode G1, a lateral resistance r2 of the p − layer 508 causes a potential difference in the p − layer 508.

This potential difference is due to the p − layer 508 and the n 2+ layer 506.
When it exceeds the diffusion potential of (about 0.7 V for silicon),
Electrons are directly injected from the n2 + layer 506 into the n- layer, the thyristor including the transistors Q1 and Q2 is fired, and the semiconductor device is turned on. Note that the resistance r1
Has a sufficiently small resistance value because the p2 + layer 507 has a high impurity concentration. Therefore, the transistors Q3 and Q4 have
The parasitic thyristor consisting of is hard to turn on.

On the other hand, in order to turn off the semiconductor device, the potentials of the first and second insulated gate electrodes G1 and G2 are made equal to the potential of the cathode electrode K509, or
Alternatively, the potential is set to be more negative than the potential of the cathode electrode K509. As a result, the first and second insulated gate electrodes G
1 and G2, the inversion layer on the surface of the p − layer 508 disappears, and the injection of electrons from the n 2+ layer 506 is blocked.
The injection of holes from the p1 + layer 502 is also eliminated, and the semiconductor device is turned off.

In the semiconductor device according to the prior art as described above, by using the thyristor operation, electrons supplied from the cathode electrode K509 through the n-channel MISFET M1 spread in the lateral direction of the n2 + layer 506, so that they are in conduction. Voltage drop (resistance loss) of conventional IGB
It can be smaller than T. In addition, this semiconductor device has a feature that ON / OFF can be controlled by applying and removing a potential to the insulated gate electrode, and the gate circuit can be extremely simplified as in the conventional IGBT. is doing.

[0013]

However, the above-described semiconductor device according to the prior art has a problem that the on-voltage cannot be sufficiently reduced although the thyristor operation is used.

That is, the conventional semiconductor device is
p- layer 508 is connected to p2 + layer 507, and
Since the p2 + layer 507 has a high impurity concentration, the p2 + layer 507
The above-mentioned lateral resistance r1 has a low resistance value. Therefore, in the semiconductor device according to the conventional technique, in the vicinity of the p − layer 508 where the p 2+ layer 507 is connected,
Lateral resistance r of p − layer 508 when a hole current flows
The potential difference due to 2 does not rise to the diffusion potential (about 0.7 V in silicon) with the n2 + layer 506, so that it cannot be fired as a thyristor, and the thyristor operation can be performed only in the portion distant from the p2 + layer.

Therefore, in the above-described semiconductor device according to the prior art, the thyristor region in the vicinity of the p − layer 508 to which the p 2+ layer 507 is connected is wasted, and the entire semiconductor device cannot be used effectively. Therefore, there is a problem that the on-voltage cannot be made sufficiently small.

An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a MOS control type semiconductor device capable of reducing the on-resistance during conduction and the resistance loss during conduction. It is in.

[0017]

According to the present invention, the object is to provide an IGBT and a thyristor in the same semiconductor substrate.
The p-base layer of the GBT and the p-base layer of the thyristor are arranged so as to be separated from each other, and the n-emitter of the thyristor is separated by one M.
This is achieved by adopting a structure in which the cathode electrode is connected through the channel of the OSFET.

[0018]

In the present invention, the p-base layer of the thyristor is the IGBT.
Since it is configured separately from the p base layer of, the holes from the anode electrode do not flow from the p base layer of the thyristor to the cathode electrode, and it is possible to raise the potential of the p base layer in the thyristor region evenly. The entire thyristor area can be operated as a thyristor.
Further, according to the present invention, the n-emitter of the thyristor is configured to be connected to the cathode electrode via only the cathode electrode and one MOSFET of the IGBT, so that the electron current injected into the n-emitter of the thyristor is generated by the thyristor. Only one MOSFET MOSFET that turns on and off passes.

According to the present invention, as described above, the on-voltage is low,
That is, it is possible to realize a MOS control type semiconductor device having a small on-resistance when conducting and a small resistance loss.

[0020]

Embodiments of a MOS control type semiconductor device according to the present invention will be described below in detail with reference to the drawings. In each embodiment of the present invention described below, the first conductivity type semiconductor is p-type,
This is an example in which the second conductivity type semiconductor is an n-type, and in the description, reference numerals and the like are given and simply referred to as a p-layer and an n-layer.

FIG. 1 is a sectional view showing the structure of a semiconductor device according to the first embodiment of the present invention, FIG. 2 is a diagram for explaining an equivalent circuit of the semiconductor device according to the first embodiment of the present invention, and FIG. 1 is a plan view showing the configuration of a semiconductor device according to a first example of the invention. In FIG. 1, reference numeral 1 denotes an n-type semiconductor substrate, n-
It functions as the layer 171.

As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention includes an n layer 172 adjacent to the n − layer 171, having a higher impurity concentration than the n − layer 172, an n layer 172, and a semiconductor substrate 1. A p1 + layer 18 adjacent to the surface 12 and having a higher impurity concentration than the n layer 172, a p layer 131 extending from the main surface 11 of the semiconductor substrate 1 into the n- layer 171, and having a higher impurity concentration than the n- layer 171, the main surface 11 From the main surface 11 to the p layer 131 and the p 2+ layer 132 and having a higher impurity concentration than the p layer 131, and the p layer 13.
1 extending from the main surface 11 into the n-layer 1 adjacent to the n-layer 171
P1-layer 15 having an impurity concentration between the p-layer 131 and the p-layer 131
2. n − from a point distant from the main surface 11 into the p 1 − layer 152 at a position distant from the n 1 + layer 14 and having a higher impurity concentration than the p 1 − layer 152, the p layer 131 and a point distant from the p 1 − layer 152. P2-layer 162 extending into layer 171 and having an impurity concentration between n-layer 171 and p-layer 131, n3 + layer 161 extending from main surface 11 into p2-layer 162 and having a higher impurity concentration than p2-layer 162 Are formed and configured in the semiconductor substrate 1.

The cathode electrode K2 is provided so as to contact the n1 + layer 14 and the p2 + layer 132, and the p1 + layer 18 is formed.
And an anode electrode A3 is provided. Also, n1 +
The electrode 41 provided on the exposed surface of the p-layer 131 exposed between the layer 14 and the n2 + layer 151 with an insulating film between the first
An insulated gate electrode G1 is formed, and n2 + layers 151 and n3 + are formed.
P1-layer 152 and n-layer 171 exposed between the layers 161
A second insulated gate electrode G2 is formed by the electrode 42 provided on the exposed surface of the p2-layer 162 with an insulating film interposed therebetween. These first and second insulated gate electrodes G1 and G2
Are connected by wiring not shown to form a gate electrode G4. Further, 5 is an n <2+> layer 151 and an n <3+> layer 161 which are short-circuited to each other by an electrode 5 which is not connected to the cathode electrode 2.

Reference numeral 6 denotes an insulating film, and the semiconductor device having the above-described structure has the structure shown in FIG. 1 as a unit cell and is arranged in line symmetry around the right or left end of the drawing as a center. , Many are connected in parallel and used.

This semiconductor device has an n1 + layer 14 and a p2 + layer 1
32, p layer 131, first insulated gate electrode 41, n layer 1
7, the p1 + layer 18, an IGBT region formed in the lower part of the first insulated gate G1 and a part of the parasitic thyristor region adjacent to the first insulated gate G1, the n3 + layer 161, the p2− layer 162, the n layer 1
7, a first thyristor region consisting of p1 + layer 18, and n2 +
The second thyristor region including the layer 151, the p1− layer 152, the n layer 17, and the p1 + layer 18 is provided. The first and second thyristor regions are separated from each other by the presence of the n − layer 171 that has entered the lower portion of the second insulated gate electrode 42. In addition, the MOSFET including the first gate electrode 41 in the lower layer portion thereof
M1 is provided in each of the parts including the p1-layer 152 and the p2-layer 162 of the lower layer including the second gate electrode 42 with MOSF.
ET M2 and M3 are formed. An equivalent circuit of this is the circuit diagram shown in FIG.

The plan view shown in FIG. 3 is shown with a part of the aluminum of the cathode electrode removed for the sake of clarity, and the cross section taken along the line AA 'in FIG. 3 is the cross sectional view shown in FIG.

In the semiconductor device according to the first embodiment of the present invention, as shown in FIG. 3, the electrode 5 connecting the first thyristor region and the second thyristor region is formed on the n2 + layer 151 and the n3 + layer 161. It is configured to be connected to the semiconductor substrate 1 by the contact region provided in the. Then, the electrode 5 is designed to maximize the area of the cathode electrode.
Moreover, it is formed so as not to be connected to the cathode electrode 2. Further, the electrode 5 does not have to be made of aluminum, and can be replaced by another material having a function equivalent to that of aluminum.

Next, the operating principle of the semiconductor device according to the first embodiment of the present invention configured as described above will be described with reference to FIGS.

When the semiconductor device according to the first embodiment of the present invention shown in FIGS. 1 and 2 is turned on, the anode electrode 3 has a positive potential, the cathode electrode 2 has a negative potential, and the insulated gate electrode 4 has a positive potential. Is applied. As a result, an inversion layer is formed on the surfaces of the p layer 131 below the insulated gate electrode 41 and the p1 layer 152 and the p2 layer 162 below the insulated gate electrode 42, and the n-channel MOSFETs M1, M2, and M3 are turned on. Become.

As a result, the electron current from the cathode electrode 2 flows into the n-layer 171 through the n1 + layer 14, the n2 + layer 151 and the inversion layer, and the p2-layer 162 and the n-layer 1 are formed.
7, pnp transistors Q1 and p consisting of p1 + layer 18
The pnp transistor Q3 including the 1-layer 152, the n-layer 17, and the p1 + layer 18 is turned on, the hole current from the anode electrode A3 raises the potentials of the p1-layer 152 and the p2-layer 162, and the n3 + layer 161, p2-layer. 162, n composed of the n layer 17
pn transistor Q2 and n2 + layer 151, p1-layer 15
2, the npn transistor Q4 including the n layer 17 is turned on. In the illustrated semiconductor device, the first thyristor region made up of Q1 and Q2 and the second thyristor region made up of Q3 and Q4 are thereby ignited and turned on.

In the above-mentioned ON state, the first thyristor region is separated from the IGBT region via the n − layer 171, so that the thyristor operation can be performed in the entire region. The second thyristor region does not perform the thyristor operation in the vicinity where it is connected to the IGBT region,
The thyristor operation is performed only in the part away from the T region. Therefore, the second thyristor region is formed as fine as possible.

In addition, the n3 + layer 16 in the first thyristor region
Since the n3 + layer 161 is directly connected to the MOSFET M1 in the IGBT region and the n + emitter in the first thyristor region via the electrode 5,
MOSF in the IGBT region from the cathode electrode 2 without passing through the channels of the n-channel MOSFETs M2 and M3.
Can only flow through ETM1. For this reason,
Although the first thyristor region of the illustrated semiconductor device is separated from the IGBT region, it is connected to the cathode electrode 2 of the semiconductor device only via the MOSFET M1 of the IGBT region.

Therefore, in the semiconductor device according to the first embodiment of the present invention, by making the second thyristor region as fine as possible and enlarging the first thyristor region, the IG
Connected via only one of the MOSFETs in the BT region,
The floating first thyristor region separated from the IGBT region can be made to have a low on-voltage, whereby the whole semiconductor device can be made to have a low on-voltage.

When the semiconductor device according to the first embodiment of the present invention is turned off from the ON state as described above, the potential of the insulated gate electrode 4 is the same as the potential of the cathode electrode 2 or more negative than the potential of the cathode electrode 2. To the potential. As a result, the inversion layers formed on the surfaces of the p-layer 131 below the insulated gate electrode 41 and the p1-layer 152 and p2-layer 162 below the insulated gate electrode 42 disappear, and the n-channel MO
The SFETs M1, M2, M3 are turned off, and the injection of electrons from the n1 + layer 14 into the n2 + layer 151 and the n3 + layer 161 is stopped. Therefore, hole injection from the p1 + layer 18 is also eliminated, and the semiconductor device according to the first embodiment of the present invention is turned off.

FIG. 4 is a sectional view showing the structure of a semiconductor device according to the second embodiment of the present invention. The semiconductor device according to the second embodiment is arranged in line symmetry around the left or right end as a unit cell of FIG. 4 and is connected in parallel.

The feature of the illustrated semiconductor device is that in the first semiconductor device of the present invention described with reference to FIG.
, And instead, the n2 + layer 151 extends into the p layer 131, and the p3 + layer, which is a p-type semiconductor layer having a higher impurity concentration than the p layer 131, is adjacent to the n2 + layer 151 and extends into the p layer 131. This is the point where 19 is arranged. That is, the second embodiment of the present invention eliminates the second thyristor region of the semiconductor device of FIG. 1 and replaces this portion with the n2 + layer 151 and the p3 + layer 1
9, p layer 131, insulated gate electrode 42, n layer 17, p1 +
The IGBT region is formed of the layer 18, and the operation principle of turn-on and turn-off is the same as that of the first embodiment of the present invention described above.
This is the same as the case of the embodiment.

In the second embodiment of the present invention having such a structure, the lower layer of the n2 + layer is the p1-layer 1 in the first embodiment.
The p3 + layer 19 has an impurity concentration higher than that of 52, and this portion has a low resistance. The n2 + layer 151, the p3 + layer 19, and the p layer 1
Since the parasitic thyristor composed of 31, the n layer 17, and the p1 + layer 18 is hard to turn on, the semiconductor device of FIG. 1 is less likely to be latched up by the hole current at turn-off and the breakdown resistance at turn-off is large. .

FIG. 5 is a sectional view showing the structure of a semiconductor device according to the third embodiment of the present invention, and FIG. 6 is a plan view showing the structure of the third embodiment of the present invention, and the sectional view shown in FIG. FIG. 4 is a sectional view taken along line AA ′ and BB ′ of FIG. 3. The semiconductor device according to the second embodiment is arranged in line symmetry around the left or right end as a unit cell of FIG. 5 and is connected in parallel. Further, in FIG. 6, a part of the aluminum of the cathode electrode is removed for clarity.

The feature of this third embodiment of the present invention is that FIG.
The semiconductor device described in 1 above and the IGBT in which the channels of the MOSFETs are in series are arranged in a plane, and the turn-on and turn-off operation principles are the same as those of the first embodiment of the present invention. It is the same. The advantage of this semiconductor device is that it is easier to turn on than the semiconductor device described with reference to FIGS.

That is, in the semiconductor device according to the embodiment of the present invention described with reference to FIGS. 1 and 4, when turned on, electrons injected from the cathode electrode 2 are MOSFETs.
Although the two channels of M1 and M2, M3 must be passed, the semiconductor device according to the third embodiment of the present invention is such that, when turned on, electrons injected from the cathode electrode 2 have only one channel of the MOSFET M1. Just pass. Therefore, in the third embodiment of the present invention, the channel resistance at the time of turn-on becomes small, the electron current at the time of turn-on becomes large, and the hole current from the anode side can also become large. Becomes Also,
In the third embodiment of the present invention, since the gate electrodes 41 and 42 are short-circuited, the gate resistance of the semiconductor device is reduced and the time constant of the gate 4 can be reduced, so that it is easier to turn on. .

Therefore, according to the third embodiment of the present invention described above, the on-voltage can be lowered by separating the p base layer of the IGBT region and the p base of the thyristor, and the MOSFET can be The IGBT in series makes it easier to turn on.

FIG. 7 is an electric circuit diagram showing a configuration example of an inverter device for driving a motor, which is constructed by using the semiconductor device according to the embodiment of the present invention described above. In FIG. 7, T ₁ and T ₂ are a pair of DC terminals connected to a DC power source,
T ₃ , T ₄ , and T ₅ are the same number of AC terminals as the number of phases on the AC side connected to the three-phase induction motor, SW ₁₁ , SW ₁₂ , SW ₂₁ , and SW.
₂₂ , SW ₃₁ , and SW ₃₂ are semiconductor devices according to the embodiment of the present invention, in which two pieces are connected in series and three pieces are connected in parallel between a pair of DC terminals T ₁ and T ₂ . The series connection points of the two composite semiconductor devices are respectively connected to AC terminals T ₃ , T ₄ , T ₅ , D ₁₁ , D ₁₂ , D ₂₁ , D ₂₂ , D ₃₁ , D _32.
Are flywheel diodes SB ₁₁ , SB ₁₂ , SB ₂₁ , SB ₂₂ , S ₂₂ connected in antiparallel to the respective composite semiconductor devices.
B ₃₁ and SB ₃₂ are snubber circuits configured by connecting a capacitor in series to a parallel circuit of a diode and a resistor, and connected in parallel to each semiconductor device.

The semiconductor device according to the embodiment of the present invention used as a switching element in the inverter device shown in FIG. 7 can be easily turned on and off by applying and removing a potential from the insulated gate electrode. For example G
Unlike the TO thyristor, it is not necessary to flow or draw a large amount of current by the gate electrode, and the gate circuit for controlling the inverter can be configured extremely simply. Further, since the semiconductor device according to the embodiment of the present invention utilizes the saturation characteristic of the built-in MOSFET, it is possible to give a current limiting action even though it is a thyristor operation, and to make a large current a low on-voltage. Therefore, it is possible to control at high speed without destroying the element.

Therefore, in the inverter device shown in FIG. 7, for example, as compared with the case where a GTO thyristor is used, it is easy to increase the frequency and it is possible to control easily.
It is possible to achieve size reduction, weight reduction, loss reduction, noise reduction, etc. of the device, and, for example, increase the capacity and loss of the inverter device due to the low on-voltage compared to the case of using an IGBT. Etc. can be achieved.

[0045]

As described above, according to the present invention, the entire region of the second semiconductor region, which is the thyristor region, can be operated as a thyristor, and the n-emitter of the thyristor is the first electrode that is the cathode electrode. , MOSFET of the first semiconductor region which is an IGBT for turning on / off the thyristor
Since only one T1 is connected, the amount of carriers in the semiconductor device can be increased and a semiconductor device with a low on-voltage can be provided.

Further, by using the semiconductor device according to the present invention, it is possible to provide an inverter device which is compact, lightweight, low loss and low noise.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an equivalent circuit of the semiconductor device according to the first exemplary embodiment of the present invention.

FIG. 3 is a plan view showing the configuration of the semiconductor device according to the first example of the present invention.

FIG. 4 is a sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a plan view showing a configuration of a third exemplary embodiment of the present invention.

FIG. 7 is an electric circuit diagram showing a configuration example of an inverter device configured using the semiconductor device according to the present invention.

FIG. 8 is a cross-sectional view illustrating the configuration of the above-described conventional semiconductor device.

FIG. 9 is a diagram illustrating an equivalent circuit of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 semiconductor substrate 11, 12 main surface 13 p layer 14 n1 + layer 151 n2 + layer 152 p1-layer 161 n3 + layer 162 p2- layer 17 n layer 18 p1 + layer 2 cathode electrode 3 anode electrode 4 insulated gate electrode 5 conductive material 6 insulating film

Claims (8)

[Claims] 1. An M having an insulated gate and controlled thereby.
In an OS control type semiconductor device, a first conductivity type semiconductor base having a pair of electrodes, a second conductivity type first semiconductor layer adjacent to a first surface of the semiconductor base and having a higher impurity concentration than the semiconductor base, a semiconductor A second conductive type second semiconductor layer extending from the second surface of the base body into the semiconductor body and having a higher impurity concentration than the semiconductor base body, and extending from the second surface of the semiconductor base body into the second semiconductor layer and having a higher impurity concentration Forming a channel on the surface of the second semiconductor layer, which is formed on the exposed surface of the second semiconductor layer adjacent to the third semiconductor layer of the first conductive type third semiconductor layer, which is exposed on the second surface, A first semiconductor region having an insulated gate connecting a third semiconductor layer and a semiconductor layer adjacent to the second semiconductor layer, a first semiconductor layer, a second surface of the semiconductor substrate extending into the semiconductor substrate, and a semiconductor substrate. In the second semiconductor layer A second conductivity type fourth semiconductor layer having a high impurity concentration, and a first conductivity type fifth semiconductor layer extending from the second surface of the semiconductor substrate into the fourth semiconductor layer and having a higher impurity concentration. A second semiconductor region, a first electrode in contact with the second semiconductor layer and the third semiconductor layer, and a second electrode in contact with the first semiconductor layer, wherein the second semiconductor layer and the fourth semiconductor layer are semiconductor substrates. A MOS control type semiconductor device, characterized in that it is separated by a semiconductor layer, and a fifth semiconductor layer is connected to the first electrode via a second semiconductor layer below the insulated gate. 2. A semiconductor layer of the second conductivity type, which extends from the second surface of the semiconductor substrate into the second semiconductor layer, has a higher impurity concentration than the second semiconductor layer, and is adjacent to the third semiconductor layer. The MOS control type semiconductor device according to claim 1, wherein 3. A third semiconductor region, which has a semiconductor layer structure similar to that of the second semiconductor region, is adjacent to the first semiconductor region at a position apart from the second semiconductor region, and a fifth semiconductor layer of the third semiconductor region. 3. The MOS according to claim 2, further comprising an electrode connecting the fifth semiconductor layer in the second semiconductor region with the electrode.
Controlled semiconductor device. 4. A fourth semiconductor region having a semiconductor layer structure similar to that of the first semiconductor region and being adjacent to the first semiconductor region at a position apart from the second semiconductor region, and a third semiconductor layer of the fourth semiconductor region. 3. The MOS according to claim 2, further comprising an electrode connecting the fifth semiconductor layer in the second semiconductor region with the electrode.
Controlled semiconductor device. 5. The MOS control type semiconductor device according to claim 1, wherein the first electrode is connected to the semiconductor substrate through a channel below the insulated gate of the first semiconductor region. 6. An M having an insulated gate and controlled thereby.
In an OS control type semiconductor device, a first conductivity type first semiconductor having a higher impurity concentration than a semiconductor base (1) inside a first conductivity type semiconductor base (1) having a pair of electrodes. Layer (172), first
A second conductive type second semiconductor layer (18) adjacent to the semiconductor layer (172) and the first surface (12) of the semiconductor substrate (1) and having a higher impurity concentration than the first semiconductor layer (172), and a semiconductor substrate ( From the second surface (11) of 1) to the semiconductor substrate (1)
A third semiconductor layer (131) of the second conductivity type extending inwardly and having a higher impurity concentration than that, extending from the second surface (11) into the third semiconductor layer (131), and having a higher impurity concentration. The second conductivity type fourth semiconductor layer (132) extends from the second surface (11) into the third semiconductor layer (131) and the fourth semiconductor layer (132), and has a higher impurity concentration than the third semiconductor layer (131). A first conductivity type fifth semiconductor layer (14),
A second conductive material that is adjacent to the third semiconductor layer (131), extends from the second surface (11) into the semiconductor substrate (1), and has an impurity concentration between the semiconductor substrate (1) and the third semiconductor layer (131). Of the second conductivity type extending from the second surface (11) into the sixth semiconductor layer (152) at a position away from the sixth semiconductor layer (152) and the fifth semiconductor layer (14) and having a higher impurity concentration. The seventh semiconductor layer (151), the third semiconductor layer (131), and the sixth semiconductor layer (152) of the mold extending into the semiconductor substrate (1), and the semiconductor substrate (1) and the third semiconductor layer ( 131) second with an impurity concentration between
A conductive type eighth semiconductor layer (162), extending from the second surface (11) into the eighth semiconductor layer (162),
62) A first electrode (2) having a ninth semiconductor layer (161) of the first conductivity type having a higher impurity concentration and contacting the fifth semiconductor layer (14) and the fourth semiconductor layer (132), The second electrode (3) in contact with the second semiconductor layer (18) and the third semiconductor layer (131) exposed between the fifth semiconductor layer (14) and the seventh semiconductor layer (151).
A first insulated gate electrode (41) formed on the exposed surface of the substrate via an insulating film, and a sixth semiconductor layer (152) exposed between the seventh semiconductor layer (151) and the ninth semiconductor layer (161). And a second insulated gate electrode (42), a seventh semiconductor layer (151) and a ninth semiconductor layer (1) formed on the exposed surfaces of the semiconductor substrate (1) and the eighth semiconductor layer (162) via an insulating film.
61) A MOS control type semiconductor device comprising a third electrode (5) which is short-circuited and which is not connected to the first electrode (2). 7. An M having an insulated gate and controlled by the same.
In an OS control type semiconductor device, a first conductivity type first semiconductor having a higher impurity concentration than a semiconductor base (1) inside a first conductivity type semiconductor base (1) having a pair of electrodes. Layer (172), first
A second conductive type second semiconductor layer (18) adjacent to the semiconductor layer (172) and the first surface (12) of the semiconductor substrate (1) and having a higher impurity concentration than the first semiconductor layer (172), and a semiconductor substrate ( From the second surface (11) of 1) to the semiconductor substrate (1)
A third semiconductor layer (131) of the second conductivity type extending inwardly and having a higher impurity concentration than that, extending from the second surface (11) into the third semiconductor layer (131), and having a higher impurity concentration. Second conductivity type fourth semiconductor layer (132), second surface (11) at a location distant from the fourth semiconductor layer (132)
From the second conductivity type to the third semiconductor layer (131) and having a higher impurity concentration than the fifth semiconductor layer (19), the second surface (11) to the third semiconductor layer (131) and the fourth semiconductor. A sixth semiconductor layer (1) of the first conductivity type that extends into the layer (132) and has a higher impurity concentration than the third semiconductor layer (131).
4), a first semiconductor layer extending from the second surface (11) into the third semiconductor layer (131) and the fifth semiconductor layer (19) at a position apart from the sixth semiconductor layer (14) and having a higher impurity concentration. Impurities between the semiconductor base (1) and the third semiconductor layer (131) extending from the conductive type seventh semiconductor layer (151) and the third semiconductor layer (131) into the semiconductor base (1). An eighth semiconductor layer of the second conductivity type having a concentration (16
2) comprises a ninth semiconductor layer (161) of the first conductivity type, which extends from the second surface (11) into the eighth semiconductor layer (162) and has a higher impurity concentration than the sixth semiconductor layer (). 14) and the first electrode (2) in contact with the fourth semiconductor layer (132), the second electrode (3) in contact with the second semiconductor layer (18), the sixth semiconductor layer (14) and the seventh semiconductor layer ( 151) exposed to the third semiconductor layer (131)
A first insulated gate electrode (41) formed on the exposed surface of the substrate via an insulating film, and a third semiconductor layer (131) exposed between the seventh semiconductor layer (151) and the ninth semiconductor layer (161) And a second insulated gate electrode (42), a seventh semiconductor layer (151) and a ninth semiconductor layer (1) formed on the exposed surfaces of the semiconductor substrate (1) and the eighth semiconductor layer (162) via an insulating film.
61) A MOS control type semiconductor device comprising a third electrode (5) which is short-circuited and which is not connected to the first electrode (2). 8. A pair of direct current terminals, an alternating current terminal having the same number as the number of alternating current phases, and an arm having the same number as the number of alternating current phases by two switching elements connected in series between the pair of direct current terminals,
8. The power conversion device configured by connecting a connection point of two switching elements connected in series to an alternating current terminal, wherein the switching element is M according to claim 1.
A power conversion device, which is an OS-controlled semiconductor device.