JPH07335859A - Composite semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a composite semiconductor device capable of increasing the breakdown withstand voltage during interruption and the load short-circuit withstand amount during operation and reducing the resistance loss during on-state. [Structure] First and second base layers 2, 5 to 7 and first and second base layers
An IGBT region and a thyristor region are arranged adjacent to each other, having emitter layers 4 and 8 to 9, an anode electrode 10, a cathode electrode 11, and a gate electrode 12, and a MI in the IGBT region.
An SFET is formed, the first emitter layer 4 is connected to the anode electrode 10, the second emitter layer 8 and the second base layer 6 are connected to the cathode electrode 11, and the second emitter layer 8 is the MISFET.
In the composite semiconductor device coupled to the second emitter layer 9 via the second emitter layer 9, at least some of the second emitter layers 8 and 9 are replaced with the second base layers 6 and 7, respectively, and the second base layer 7 is passed through the replacement portion. A charged particle coupling passage extending from to the cathode electrode 11 via the second base layer 6 is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite semiconductor device, and more particularly, by increasing the breakdown resistance when turned off and reducing the internal resistance when turned on, a high breakdown voltage can be obtained and a large current can be processed. The present invention relates to a composite semiconductor device.

[0002]

2. Description of the Related Art Conventionally, in the field of power converters such as inverters, high-speed switching is possible for high voltage or large current in order to perform high-performance power conversion, and moreover, loss during switching is high. There has been a demand for the development of small semiconductor switching devices. By the way, as a known semiconductor switching device, an IGBT (insulated gate bipolar transistor) is known as a device having characteristics relatively close to the above demand. This IGBT
Has advantages such as a smaller internal voltage drop when turned on than a MISFET (metal insulator semiconductor field effect transistor), and a faster switching operation than a current control type device such as a GTO (gate turn off) thyristor. Since it has advantages such as simplification of the configuration of the gate control circuit and the like, in recent years, it has been widely used as a switching element of an inverter device having a relatively small power capacity. It was However, I
On the other hand, the GBT has the above-mentioned advantages, but if it is configured to have a high withstand voltage or a structure capable of handling a large current, the internal voltage drop at the time of turning on becomes extremely large.
The inverter device using the GBT naturally has a limit in the power capacity to be processed.

Therefore, in order to increase the limit of the power capacity as much as possible, a thyristor region and a parasitic thyristor region have recently been provided as a semiconductor switching device replacing the IGBT, and the thyristor is controlled by a control voltage applied to an insulated gate electrode. A composite semiconductor device in which a region is controlled, that is, a MIS (metal oxide semiconductor) gate type thyristor device has been developed, and such a composite semiconductor device (MI
S-gate type thyristor device) is, for example,
PS D (1992) Nos. 256-260
Page (Proceedings of 1992 Int
international Symposium on P
ower SemiconductorDevice
& ICs, Tokyo, pp. 256-260).

FIG. 11 is a sectional view showing an example of the configuration of the composite semiconductor device (MIS gate type thyristor device) according to the above disclosure.

As shown in FIG. 11, the MIS gate type thyristor device has a semiconductor substrate 60 and an anode electrode 70 (A) conductively connected to the first main surface 61 of the semiconductor substrate 60.
And a cathode electrode 71 (K) and first and second gate (insulated gate) electrodes 72-1 and 72-2 (G1, G2) that are conductively connected to the second main surface 62 of the semiconductor substrate 60. The semiconductor substrate 60 includes an n-type low impurity concentration first base layer (n − base layer) 63 and an n − base layer 63.
A buffer layer (n buffer layer) 64 having an n-type impurity concentration in contact with one surface, and a first emitter layer (p + 1 emitter layer) 65 having a high p-type impurity in contact with another surface of the n buffer layer 64. And a second base layer (p + 2 base layer) 66 of p-type high impurity concentration selectively formed on a part of the other surface of the n − base layer 63, and a part of the other surface of the n − base layer 63 as well. To p
A second base layer (p-base layer) 67 of p-type low impurity concentration selectively formed adjacent to the +2 base layer 66, and a part of each surface of the p + 2 base layer 66 and the p-base layer 67. N-type high impurity concentration second emitter layer (n + 1 emitter layer) 68 selectively formed, and n-type high impurity concentration second emitter layer selectively formed on part of the surface of the p- base layer 67. (N + 2 emitter layer) 69. Further, the anode electrode 70 is conductively connected to the exposed surface of the p + 1 emitter layer 65,
A cathode electrode 71 is disposed in contact with a part of the exposed surface of the p + 2 base layer 66 and the n + 1 emitter layer 68. p-base layer 67 between n + 1 emitter layer 68 and n + 2 emitter layer 69
To the exposed surface of the first gate electrode 72-1 through the insulating film 73.
Is disposed on the exposed surface of the p− base layer 67 and the n− base layer 63 at the end of the n + 2 emitter layer 69.
The second gate electrode 72-2 is arranged via the.

In this case, the anode electrode 70, p + 1 emitter layer 65, n buffer layer 64, n-base layer 63, p-
4 layers pnp consisting of base layer 67 and n + 2 emitter layer 69
The n-junction portion constitutes a thyristor region (inside the dotted line on the left side of FIG. 11), and includes the anode electrode 70, the p + 1 emitter layer 65, the n buffer layer 64, the n− base layer 63, and the p + 2 base layer. A four-layer pnpn junction portion composed of 66, n + 1 emitter layer 68, and cathode electrode 71 constitutes a parasitic thyristor region (inside the dotted line on the right side of FIG. 11). Also, the n + 1 emitter layer 68, the p− base layer 67, the n + 2 emitter layer 69,
The portion composed of the insulating film 73 and the first gate electrode 72-1 is
A first n-channel MISFET (M1) is formed, and n-
Base layer 63, p- base layer 67, n + 2 emitter layer 6
The portion composed of 9, the insulating film 73, and the second gate electrode 72-2 constitutes the second n-channel MISFET (M2).

Continuing, FIG. 12 shows the MI shown in FIG.
It is a circuit block diagram which shows the internal equivalent circuit of an S gate type thyristor device.

In FIG. 12, four layers p in the thyristor region are formed.
The npn junction is equivalently equivalent to the pnp transistors Q1 and n.
The four-layer pnpn junction in the parasitic thyristor region is equivalent to the pnp transistor Q2.
3 and an npn transistor Q4.

The MIS gate type thyristor device having the above structure operates as follows.

First, when the MIS gate type thyristor device is turned on, a positive high voltage is applied to the anode electrode 70 with reference to the voltage of the cathode electrode 71, and the first and second
A positive control voltage is applied to the gate electrodes 72-1 and 72-2. At this time, the first and second gate electrodes 72-1 and
N− on the surface side of the p− base layer 67 under 72-2.
A channel is formed, and an n + 1 emitter layer 68, an n + 2 emitter layer 69, and an n− base layer 63 are formed through these n channels.
Are conductively connected, and the first n-channel MISFET (M
1) and the second n-channel MISFET (M2) are turned on. At this time, electrons (MIS current) n − from the cathode electrode 71 through the first n-channel MISFET (M1) and the second n-channel MISFET (M2).
The holes (hole current) are injected into the base layer 63, and at the same time, holes (hole current) are injected from the p + 1 emitter layer 65 through the n buffer layer 64 into the n- base layer 63. Then, when a hole current flows from the n − base layer 63 to the cathode electrode 71 through the p − base layer 67, a lateral resistance r2 in the p − base layer 67 causes a potential difference in the p − base layer 67. When this potential difference exceeds the diffusion potential at the junction between the p- base layer 67 and the n + 2 emitter layer 69 (about 0.7 V at room temperature in silicon), electrons are directly emitted from the n + 2 emitter layer 69 to the n-. As a result, the pnp transistor Q1 and the npn transistor are turned on and the thyristor region is ignited.
The IS gate type thyristor device turns on. In this case, along with the lateral resistance r2 in the p- base layer 67,
A lateral resistance r1 also exists in the +2 base layer 66, but p
Since the +2 base layer 66 has a high impurity concentration, the lateral resistance r1 is sufficiently smaller than the lateral resistance r2 so that the pnp transistor Q3 and the npn transistor Q4 in the parasitic thyristor region do not turn on during the normal operation. Is designed to.

On the other hand, when the MIS gate type thyristor device is turned on, the first and second gate electrodes 72-1 and 72-1,
The same or negative control voltage as that of the cathode electrode 71 is applied to 72-2. At this time, the first and second gate electrodes 7
The n-channel formed on the surface side of the p − base layer 67 under 2-1 and 72-2 disappears, and the n +2 emitter layer 69
Since electrons are blocked from being injected from the n + 1 base layer 63 into the n @-base layer 63, the n + 1 layer is passed from the p + 1 emitter layer 65 to the n buffer layer 64.
-The injection of holes into the base layer 63 is also stopped. Then, some of the holes in the n- base layer 63 are recombined with the electrons and the rest are swept out to the cathode electrode 71, and the MIS gate type thyristor device is turned off.

This MIS gate type thyristor device utilizes the thyristor function, and electrons supplied from the cathode electrode 71 through the first n-channel MISFET (M1) spread laterally in the p-base layer 67. Since it flows, the on-voltage (resistance loss) at conduction is known to the IGB.
It can be smaller than T. In addition, this MIS thyristor device has the first and second gate electrodes 72-1 and
Since it can be turned on or off by applying or removing a control voltage to 72-2, the configuration of the gate control circuit is simplified as in the known IGBT.

[0013]

In the known MIS gate type thyristor, all of the hole current reaching the cathode electrode 71 side is formed in the p + 2 base layer 66 region below the n + 1 emitter layer 68. Flow, with lateral resistance r
When the hole current is excessively increased, the pnp transistor Q3 and the npn transistor Q4 in the parasitic thyristor region are turned on and the parasitic thyristor region is latched up due to the voltage drop due to the lateral resistance r1. . Then, this MIS gate type thyristor has the cathode electrode 7 at the time of its turn-off.
A large terminal voltage is generated between the anode electrode 70 and the anode electrode 70, but the value of the displacement current based on the voltage change amount (dv / dt) at this time is larger than the value of the steady-state hole current flowing at the time of on, so this large value. The parasitic thyristor region is latched up by the flow of the hole current. In this case, when the parasitic thyristor region is latched up, heat determined by the product of the current value at that time and the terminal voltage is generated in the parasitic thyristor region, and the MIS gate type thyristor is thermally destroyed. This MIS gate type thyristor
There is a problem that a large breakdown resistance cannot be obtained. Further, in the MIS gate type thyristor, even when an excessive thyristor current flows due to a short circuit of a load when turned on, the parasitic thyristor region similarly latches up, and the first and second gate electrodes 72-1 and 72-2. It becomes impossible to turn off by the control voltage of -2, that is,
This MIS gate type thyristor also has a problem that a large load short circuit withstand capability cannot be obtained.

Further, in the MIS gate type thyristor, when the occupied area of the thyristor region (the occupied area of the n + 2 emitter layer 69) is increased, a large hole current is p + 2 below the n + 1 emitter layer 68. Since the current flows through the lateral resistance r1 of the base layer 66, the tendency of latch-up in the parasitic thyristor region becomes remarkable. Therefore, the MI
The S-gate type thyristor must reduce the occupation area of the thyristor region through which the main thyristor current flows in order to prevent the breakdown withstand voltage and the load short circuit withstand voltage from being reduced, and as a result, the on-state resistance loss (ON There was also a problem that the voltage) increased.

On the other hand, in the semiconductor switching device, a means for suppressing the occurrence of latch-up that occurs when a large current flows has been developed, and one example thereof is a large current flowing in a conductivity modulation type MOSFET (IGBT) device. In that case, a means for preventing the MOSFET device from latching up due to the large current is disclosed in JP-A-60-254.
No. 658.

By the way, the means according to the above disclosure is based on a MOS
The n + source layer is periodically cut out along the longitudinal direction of the FET device to form a region in which the MOSFET does not operate, and n + in the main carrier injected from the drain side to the p base layer. The carrier component flowing in the p base layer in the lower part of the source layer is reduced, and the voltage drop due to the lateral resistance of the p base layer in the lower part of the n + source layer is reduced. The MOSFET device is designed to prevent the MOSFET device from latching up when it flows.

However, although the means disclosed above can prevent the occurrence of latch-up in the conductivity modulation type MOSFET, the electron current does not flow in the periodically cut n + source layer portion, so that the ON-state is generated. However, there is a problem that the resistance loss (ON voltage) increases. It should be noted that the means according to the above disclosure is a conductive modulation type MOSFET device, that is, an
It is intended for the T device, does not imply any application to other devices, for example, a MOS control type thyristor device, but merely provides a technique for preventing the occurrence of the latch-up of the IGBT. It is not too much.

The present invention eliminates the above problems.
It is an object of the present invention to provide a composite semiconductor device capable of increasing the breakdown withstand capability during interruption and the load short-circuit withstand capability during operation, and reducing the resistance loss during on.

[0019]

In order to achieve the above-mentioned object, the present invention provides at least a first base layer, a second base layer and a first base layer in a semiconductor substrate having first and second main surfaces, respectively.
An IGBT region composed of a second emitter layer and a thyristor region are arranged adjacent to each other, an anode electrode is provided on the first main surface, a cathode electrode and an insulated gate electrode are provided on the second main surface, respectively. 2, a MISFET is formed on the main surface side, the first emitter layer in the IGBT region and the thyristor region is conductively connected to the anode electrode, and the second emitter layer and the second base layer in the IGBT region are the cathode electrode. Conductively connected to the thyristor region, the second emitter layer in the thyristor region is connected to the M
In the composite semiconductor device, which is arranged to be coupled to the second emitter layer of the IGBT region via an ISFET,
At least a part of the second emitter layer in the GBT region is replaced with the second base layer, and a part of the second emitter layer in the thyristor region is replaced with the second base layer, and the thyristor region is replaced through the replacement part. From the second base layer to the second of the IGBT region
The first means is provided with a charged particle binding passageway through the base layer to the cathode electrode.

In order to achieve the above object, the present invention provides at least a first conductivity type first semiconductor layer, and a second conductivity type high impurity concentration first semiconductor layer disposed adjacent to one surface of the first semiconductor layer. A second semiconductor layer, a plurality of second-conductivity-type third semiconductor layers selectively formed on a part of the other surface of the first semiconductor layer, and a third semiconductor layer selectively formed on a part of each surface of the third semiconductor layer. A second conductivity type fourth semiconductor layer having a high impurity concentration, and a second conductivity type low impurity concentration selectively formed on a part of the other surface of the first semiconductor layer so as to be adjacent to one of the third semiconductor layers. The fifth
A semiconductor layer, a sixth semiconductor layer of a high impurity concentration of the first conductivity type selectively formed on a part of each surface of the fourth semiconductor layer, and a sixth semiconductor layer selectively formed on a part of the surface of the fifth semiconductor layer. Semiconductor bases each having a seventh semiconductor layer of one conductivity type and a high impurity concentration, a first main electrode conductively connected to the surface of the second semiconductor layer, and a conductive connection to the fourth semiconductor layer and the sixth semiconductor layer. And a second main electrode that is formed between the sixth semiconductor layer and the seventh semiconductor layer, and the third semiconductor layer, the first semiconductor layer, and the fifth semiconductor layer that are exposed between the sixth semiconductor layer and the seventh semiconductor layer. In a composite semiconductor device comprising a sixth semiconductor layer and a control electrode insulatingly arranged on the exposed third semiconductor layer between a sixth semiconductor layer, at least a part of the sixth semiconductor layer is replaced with the fourth semiconductor layer. The first substituted portion and the seventh Providing the second replacement portion where the portion of the conductor layer is replaced with the fifth semiconductor layer, respectively, said first
Forming a first charged particle coupling path from the fifth semiconductor layer to the second main electrode through the third semiconductor layer and the fourth semiconductor layer, respectively, and through the second replacement portion , Second means for forming a second charged particle coupling path from the fifth semiconductor layer to the second main electrode via the first semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer, respectively. .

[0021]

According to the first means, the second IGBT region
At least a part of the emitter layer is replaced with the second base layer, a part of the second emitter layer in the thyristor region is replaced with the second base layer, and the second base layer of the thyristor region and the IGBT region are passed through these replacement parts. Since the charged particle (hole) coupling passage is provided to reach the cathode electrode through the second base layer of
When injected from the emitter layer to the second base layer in the thyristor region through the first base layer, most of the hole current is
Since it flows through the hole coupling passage and stops flowing to the second base layer below the second emitter layer in the IGBT region, it may have some cause, for example, an overcurrent generated at turn-off of this composite semiconductor device, or this composite semiconductor. Even if an overcurrent generated by a load short circuit or the like flows during the operation of the device, the voltage drop in the second base layer due to the overcurrent is slight, and the parasitic thyristor in the IGBT region latches up. There is no such thing.

As described above, according to the first means, even if an overcurrent flows in the composite semiconductor device, the parasitic thyristor in the IGBT region does not latch up. It is possible not only to obtain a composite semiconductor device having a large load short circuit withstand capability,
Since it becomes possible to expand the area occupied by the thyristor region in which the main thyristor current flows, it is possible to obtain a composite semiconductor device with a small resistance loss (ON voltage) when turned on.

According to the second means, at least a part of the sixth semiconductor layer (n1 + layer) is formed in the fourth semiconductor layer (p1).
The first replacement portion replaced with the 2+ layer) and the second replacement portion obtained by replacing a part of the seventh semiconductor layer (n2 + layer) with the fifth semiconductor layer (p- layer) are provided. Through the replacement part,
From the fifth semiconductor layer (p- layer) to the third semiconductor layer (p layer) and the fourth semiconductor layer (p2 + layer), the second main electrode (K)
To the first semiconductor layer (p2 + layer) through the second replacement portion and the first charged particle (hole) coupling path to the
To the first semiconductor layer (n- layer) and the third semiconductor layer (p-
Layer) and the fourth semiconductor layer (p2 + layer) respectively, and the second charged particle (hole) coupling path to the second main electrode is provided, so that the holes are formed from the second semiconductor layer (p1 + layer) to the first semiconductor layer. When injected into the fifth semiconductor layer (p− layer) through the (n− layer), most of the hole current flows through the first and second hole coupling passages, and the sixth semiconductor layer (n1 + layer) Since the current does not flow to the lower fourth semiconductor layer (p2 + layer), even if an overcurrent flows in the composite semiconductor device, the voltage drop in the fourth semiconductor layer (p2 + layer) due to the overcurrent is small. Therefore, the composite semiconductor device does not latch up.

As described above, according to the second means, even if an overcurrent flows in the composite semiconductor device, latch-up does not occur, so that the breakdown withstand capability during interruption and the load short circuit withstand capability during operation are improved. A large composite semiconductor device can be obtained, respectively, and at the same time, the area occupied by the main current flowing region can be expanded to obtain a composite semiconductor device having a small resistance loss (ON voltage) when turned on.

[0025]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a constitutional view of a first embodiment of a composite semiconductor device according to the present invention, wherein (a) is a perspective view in which some of the constituent elements are partially removed, and (b) is a perspective view. Similarly, the top view which partially removed some components is shown.

In FIGS. 1 (a) and 1 (b), 1 is a semiconductor substrate, 1a is one main surface, 1b is the other main surface, and 2 is an n-type low impurity concentration first semiconductor layer (first base layer). , N-layer hereinafter), 3 is an n-type buffer layer (first base layer,
Hereinafter, referred to as an n buffer layer), 4 is a second semiconductor layer having high p-type impurity concentration (first emitter layer, hereinafter referred to as p1 + layer),
Is a p-type third semiconductor layer (second base layer, hereinafter referred to as p-layer), 6 is a fourth semiconductor layer having high p-type impurity concentration (second base layer, hereinafter referred to as p2 + layer), and 7 is p-type low impurity concentration Of the fifth semiconductor layer (second base layer, hereinafter referred to as p- layer), 8 is a sixth semiconductor layer having n-type high impurity concentration (second emitter layer, hereinafter referred to as n1 + layer), and 9 is n-type high impurity concentration. Seventh semiconductor layer (second emitter layer, hereafter referred to as n2 + layer), 10 is an anode electrode (first main electrode), 11 is a cathode electrode (second main electrode), 12-1 and 12-2 are first and second electrodes. 2 gate electrodes (control electrodes), 12-3 are transverse gate electrodes (control electrodes), and 13 and 14 are insulating films.

The semiconductor substrate 1 is composed of an n-layer 2, an n buffer layer 3, a p1 + layer 4, two p layers 5, two p2 + layers 6, a p- layer 7, an n1 + layer 8 and an n2 + layer 9. To be done. The n buffer layer 3 and the p 1+ layer 4 are formed on one surface of the n − layer 2.
Are sequentially stacked, and the semiconductor substrate 1 is formed on the exposed surface of the p1 + layer 4.
Anode electrode 10 is conductively connected to cover substantially the entire one main surface 1a. Two strip-shaped p layers 5 are selectively arranged along the longitudinal direction of the semiconductor substrate 1 on the other surface portion of the n − layer 2, and a p − layer 7 is formed adjacent to one p layer 5. Selectively placed. On the surface portions of the two p layers 5, strip-shaped p layers are formed along the longitudinal direction of the semiconductor substrate 1.
The 2+ layer 6 is selectively arranged. On the surface of the two p2 + layers 6,
The strip-shaped n1 + is regularly formed along the longitudinal direction of the semiconductor substrate 1.
A layer 8 is selectively arranged, and on the surface of the p- layer 7, similarly, a regular rectangular n 2+ is formed along the longitudinal direction of the semiconductor substrate 1.
Layer 9 is selectively placed. In this case, the arrangement location of the n1 + layer 8 and the arrangement location of the n2 + layer 9 in the longitudinal direction of the semiconductor substrate 1 are substantially coincident with each other, and the p2 + layer 6 of the location where the n1 + layer 8 is not disposed (non-arranged location). The surface is replaced by the p2 + layer 6 to a level substantially equal to the surface of the n1 + layer 8, and n
The surface of the p @-layer 7 at the non-arranged portion of the 2+ layer 9 is also replaced with the p @-layer 7 to the same level as the surface of the n @ 2 + layer 9. An insulating film 13 is provided above the portion between the exposed surface of the p layer 5 and the exposed surface of the n − layer 2 between the exposed surface of the p layer 5 and the exposed surface of the p − layer 7 between the n 1 + layer 8 and the n 2 + layer 9. And an elongated plate-shaped first gate electrode 12-1 is arranged, and similarly, the other n1 +
An elongated second gate electrode 12-2 is provided above the exposed surface of the p layer 5 between the layer 8 and the n 2+ layer 9 with an insulating film 13 interposed therebetween.
Are placed. First and second gate electrodes 12-1 and 12
-2 are arranged in parallel along the longitudinal direction of the semiconductor substrate 1 and are regularly arranged in the transverse gate electrodes 12-.
The bridge connection is made by 3. Here, these transverse gate electrodes 12-3 are installed at the locations corresponding to the undisposed locations of the n2 + layer 9 and the n1 + layer 8. Both ends of the cathode electrode 11 are conductively connected to the respective surfaces of the p2 + layer 6 and the n1 + layer 8, and the remaining portions are above the n2 + layer 9 and the first and second gate electrodes 12-1 and 12-2. Is disposed via the insulating film 14 so as to entirely cover the other main surface 1b of the semiconductor substrate 1 as a whole. It should be noted that the composite semiconductor device actually used usually has one unit cell having the configuration shown in FIG. 1A, and several hundred or more unit cells are continuously formed in one semiconductor substrate 1. Tens of thousands are integrated and they are connected in parallel to operate.

Next, FIG. 2A is a sectional view taken along the line AA 'in the plan view shown in FIG. 1B, and FIG. 2B is a sectional view taken along the line BB' in the plan view. FIG.

2 (a) and 2 (b), FIG.
The same components as those shown in (a) and (b) are designated by the same reference numerals.

As shown in FIG. 2A, the portion where the n1 + layer 8 and the n2 + layer 9 are arranged has a thyristor region and an IGBT region which are arranged adjacent to each other in the semiconductor substrate 1, and the thyristor region is The IGBT region is composed of a four-layer pnpn junction including an anode electrode 10, a p1 + layer 4, an n buffer layer 3, an n− layer 2, a p− layer 7, and an n2 + layer 9, and the IGBT region is composed of the anode electrode 10, the p1 + layer 4, and the n region. The buffer layer 3, the n− layer 2, the p layer 5, the p 2+ layer 6, and the n 1+ layer 8 are composed of a four-layer pnpn junction portion, the first gate electrode 12-1, and the insulating film 13. On the other hand, as shown in FIG.
The unplaced portions of the n1 + layers 8 and n2 + layers 9 are the n1 + layers 8 and n.
Since there is no 2+ layer 9, the four-layer pnpn junction is not formed, and neither the thyristor region nor the IGBT region is formed.

FIG. 3 is a circuit diagram showing an internal equivalent circuit of the composite semiconductor device shown in FIGS. 1 (a) and 1 (b).

In FIG. 3, the same components as those shown in FIGS. 1A and 1B are designated by the same reference numerals.

As shown in FIG. 3, the portion composed of the p1 + layer 4, the n− layer 2 and the p− layer 7 is composed of the first pnp transistor (Q1), the n− layer 2, the p− layer 7 and the n2 + layer 9. The portion constitutes the first npn transistor (Q2), and the portion composed of the p1 + layer 4, the n− layer 2 and the p2 + layer 6 is the portion composed of the second pnp transistor (Q3), the n− layer 2, the p2 + layer 6 and the n1 + layer 8. Form a second npn transistor (Q4). In addition, the first gate electrode 12-1, the insulating film 13, n1 +
The layer 8, the p layer 5, and the n − layer 2 are composed of the first n-channel MISFET (M1), the first gate electrode 12-1, the insulating film 13, the n − layer 2, the p − layer 7, and the n 2 + layer 9. The portion composed of the second n-channel MISFET (M2), the second gate electrode 12-2, the insulating film 13, the n2 + layer 9, the p layer 5, and the n1 + layer 8 constitutes the third n-channel MISFET (M3), respectively, and traverses. Gate electrode 12-3, p2 + layer 6, p
The layer 5 and the p-layer 7 are the normally-on p-channel MISFET (M4), the transverse gate electrode 12-3,
The portion consisting of the p- layer 9, the n- layer 2, the p layer 5, and the p2 + layer 6 constitutes a normally-off p-channel MISFET (M4). In addition, r1 is the lateral resistance in the p2 + layer 6 below the n1 + layer 8, r2 is the lateral resistance in the p− layer 7 below the n1 + layer 8, and R is the internal resistance of the n− layer 2. Is. In this case, the first pnp transistor (Q1) and the first npn transistor (Q2) form a thyristor region,
An IGBT region is constituted by the first n-channel MISFET (M1), the second pnp transistor (Q3) and the second npn transistor (Q4).

Here, by using the configuration diagrams of FIGS. 1A and 1B and FIGS. 2A and 2B together with the circuit diagram of FIG. 3, the composite semiconductor device of the first embodiment will be described. The operation will be described.

First, in order to turn on the composite semiconductor device, a positive high voltage is applied to the anode electrode 10 with reference to the voltage of the cathode electrode 11, and the first and second gate electrodes 12-1 and 12-2 are applied. Apply a positive control voltage. At this time, the surface portion of the p layer 5 below the first gate electrode 12-1, the surface portion of the p − layer 7 below the first gate electrode 12-1, and the second gate electrode 12-2 An n channel is formed in the surface portion of the lower p layer 5, and a first n channel MISFET (M1) and a second n channel MISFET are formed.
(M2) and the third n-channel MISFET (M3) are turned on. And the first n-channel MIS
When the FET (M1) is turned on, electrons (MIS current) flow from the cathode electrode 11 to the first n-channel MISFE.
It is implanted into the n @-layer 2 through T (M1), and subsequently into the p1 + layer 4. When an electron (MIS current) flows into the p1 + layer 4, the first pnp transistor (Q1) turns on, and a hole (hole current) from the p1 + layer 4 to n-.
It is injected into layer 2 and subsequently flows into p-layer 7. When holes (hole current) flow into p @-layer 7, an internal voltage drop occurs due to lateral resistance r2 in p @-layer 7, which raises the potential of p @-layer 7. When the potential of the p- layer 7 exceeds the pn junction diffusion potential of the p- layer 7 and the n2 + layer 8, the first npn transistor (Q2) turns on, and the n1 + layer 8 to the third n-channel MISFET (M3).
Electrons (thyristor current) flowing into the n2 + layer 7 through
Are injected into the n- layer 2 through the first npn transistor Q2, and at the same time, from the n1 + layer 8 to the first n-channel MISF.
Electrons (thyristor current) flowing into the n2 + layer 9 through the ET (M1) and the second n-channel MISFET (M2)
Also through the first npn transistor (Q2) to the n- layer 2
Is injected into. As a result, the amount of holes (hole current) reaching the p- layer 7 from the p1 + layer 4 through the n- layer 2 is further increased, and the thyristor region including the first pnp transistor (Q1) and the first npn transistor (Q2) is ignited. Then, the composite semiconductor device is turned on.

By the way, in the composite semiconductor device of the first embodiment, the portion where the transverse gate electrode 12-3 is arranged (the lower portion of the portion where the transverse gate electrode 12-3 is arranged and the extended portion of the lower portion). Are provided with non-arranged portions of the n1 + layer 8 and the n2 + layer 9, and the p2 + layer 6 and the p- layer 7 are replaced and arranged until reaching the surfaces of the n1 + layer 8 and the n2 + layer 9, respectively. . Then, the transverse gate electrode 12
-3, the lateral resistance r2 in the p- layer 7 in the lower part is much smaller than the lateral resistance in other parts in the p- layer 7, and the lateral resistance r2 in the lower part of the transverse gate electrode 12-3 is The lateral resistance r1 in the p2 + layer 6 in the extended portion is also considerably smaller than the lateral resistances in the other portions in the p2 + layer 6. Therefore, the holes (hole current) flowing into the p- layer 7 in the lower portion of the n2 + layer 9 pass through the p- layer 7 in the unlocated portion of the n2 + layer 9 as shown in FIG. 2 (b). After flowing in a concentrated manner, it also flows in a concentrated manner in the p2 + layer 6 in an unarranged portion of the n1 + layer 8 and reaches the cathode electrode 11, so that the p− layer 7
And a large internal voltage drop does not occur in the p2 + layer 6, and as a result, it is possible to prevent the latch-up of the parasitic thyristor including the second pnp transistor (Q3) and the second npn transistor (Q4) in the IGBT region. .

On the other hand, in order to turn on the composite semiconductor device, the first and second gate electrodes 12-1 and 12-2 have the same voltage as the voltage of the cathode electrode 11 or a negative control based on the voltage of the cathode electrode 11. Apply voltage. At this time, the surface portion of the p layer 5 below the first gate electrode 12-1, the surface portion of the p − layer 7 below the first gate electrode 12-1, and the second gate electrode 12-2 The n-channels formed on the surface of the lower p-layer 5 disappear,
First n-channel MISFET (M1), second n-channel MISFET (M2), third n-channel MISFET
(M3) are turned off. And the first n
Channel MISFET (M1), second n-channel MIS
FET (M2), third n-channel MISFET (M3)
By turning off, the electrons (MIS current) flowing from the n1 + layer 8 into the n− layer 2 and the electrons (thyristor current) flowing from the n1 + layer 8 into the n2 + layer 9 are cut off. As a result, injection of holes (hole current) from p1 + layer 4 through p @-layer 2 to p @-layer 7 is also eliminated, and the composite semiconductor device is turned off.

Even at the time of this turn-off, holes (hole current) remain at p2 + at unplaced portions of the n1 + layer 8 and the n2 + layer 9.
The flow will be concentrated in the layers 6 and p-layer 7. In particular, if the control voltage to be supplied to the first and second gate electrodes 12-1 and 12-2 is selected to be a negative voltage than the voltage of the cathode electrode 11, the p layer of the n2 + layer 9 which is not arranged is formed. 5
And a p-type high impurity concentration (p +) accumulation layer is formed on the surface of the p2 + layer 6, and an inversion layer of p-type high impurity concentration (p +) is formed on the surface of the n- layer 2, whereby a normally-formed layer is formed. Both the on-type p-channel MISFET (M4) and the normally-off p-channel MISFET (M4) are turned on, and the p- layer 7 and the cathode electrodes 11 on both sides thereof are conductively connected with low resistance. As a result, the n2 + layer 9
The holes (hole currents) flowing into the p- layer 7 in the lower part of the n 2 + layer 9 are more concentrated and flow in the p- layer 9 in the non-arranged portion of the n 2 + layer 9, and the second pnp transistor (Q3)
Therefore, the parasitic thyristor including the second npn transistor (Q4) does not latch up.

As described above, according to the composite semiconductor device of the first embodiment, when a large current flows through the composite semiconductor device due to a load short circuit or the like, or the composite semiconductor device is operated at high speed. Anode electrode 1 when turned off by
0 and a large potential change (dv
Even if a displacement current is generated due to / dt), the parasitic thyristor in the IGBT region does not latch up, and it is possible to prevent the occurrence of the uncontrolled state of the composite semiconductor device due to the latch-up, and the composite semiconductor device. It is also possible to prevent the occurrence of thermal destruction.

Further, according to the composite semiconductor device of the first embodiment, the occupying area of the thyristor region through which the main current flows (the occupying area of the n2 + layer 9) is larger than that of the known composite semiconductor device of this type. Therefore, it is possible to sufficiently reduce the resistance loss (ON voltage) at the time of turning on, and it is possible to obtain a composite semiconductor device in which high breakdown voltage or high current can be easily achieved.

In the first embodiment, the n buffer layer 3 having a higher impurity concentration than the n @-layer 2 is used, which is the first npn transistor (Q1) and the second npn transistor (Q1).
It is provided to suppress the hole injection efficiency in the npn transistor (Q3), reduce the latch-up of the parasitic thyristor, and reduce the loss due to the tail current at turn-off. Then, the impurity concentration and the layer thickness of the n buffer layer 3 are appropriately set according to the characteristics required in the composite semiconductor device. Further, in order to suppress the hole injection efficiency, other means may be used in place of the n buffer layer 3, for example, the one in which the n − layer 2 is partially short-circuited to the anode electrode 10 or the p 1 + layer. 4 may be arranged adjacent to the n-layer 2, and the n-layer 2 near the adjacent portion may be provided with a minority carrier lifetime reducing means.

Next, FIG. 4 is a block diagram of a second embodiment of the composite semiconductor device according to the present invention, in which (a) is a perspective view in which some of the components are partially removed, b) is a plan view in which some components are also partially removed.

In FIGS. 4A and 4B, the same components as those shown in FIG. 1 are designated by the same reference numerals.

The difference between the structures of the second embodiment and the first embodiment is that the first embodiment has one transverse gate electrode 12-3 and one transverse gate electrode 12-3. In the second embodiment, two transverse gate electrodes 12-3 are installed in one place, and in the first embodiment, the n1 + layer 8 and the n2 + layer 9 are not formed along the longitudinal direction of the semiconductor substrate 1. While the location is selected at a position substantially corresponding to the location of each transverse gate electrode 12-3, in the second embodiment, the n1 + layer 8 and the n2 + layer 9 are arranged along the longitudinal direction of the semiconductor substrate 1. The non-arranged portion is located at the position where the two transverse gate electrodes 12-3 are installed, and in the first embodiment, the n1 + layers 8 and n are formed.
In the second embodiment, the p2 + layer 6 and the p− layer 7 are replaced and arranged in the unplaced portions of the 2+ layer 9, respectively, whereas the p2 + layer 6 is replaced and arranged in the unplaced portions of the n1 + layer 8. With
Among the unplaced parts of the n2 + layer 9, the p layer 5 is replaced and arranged in the lower part of the transverse gate electrode 12-3, and the central portion is opened in a strip shape in the portion surrounded by the two transverse gate electrodes 12-3. The n1 + layer 8 thus formed is replaced and arranged, and p is formed in this opening.
There is no difference in structure between the second embodiment and the first embodiment except that the 2+ layer 6 is replaced.

Further, FIG. 5A is a sectional view taken along the line CC 'of the plan view shown in FIG. 4B, and FIG. 5B is a sectional view taken along the line DD' of the plan view. It is a figure. Although not shown, the cross-sectional view taken along the line AA ′ of the plan view is
It is the same as the cross-sectional view shown in FIG.

In FIGS. 5A and 5B, FIG.
The same components as those shown in (a) and (b) are designated by the same reference numerals.

As shown in FIG. 5A, the portion where the n1 + layer 8 and the n2 + layer 9 are arranged has a thyristor region and an IGBT region which are arranged adjacent to each other in the semiconductor substrate 1, and the thyristor region is the anode electrode. 4, a p1 + layer 4, an n buffer layer 3, an n− layer 2, a p− layer 7, and an n2 + layer 9, which are four layers pnp
The n-junction portion is formed, and the IGBT region is formed by the anode electrode 1.
0, p1 + layer 4, n buffer layer 3, n- layer 2, p layer 5, p
A four-layer pnpn junction composed of a 2+ layer 6 and an n1 + layer 8 and a first
The gate electrode 12-1 and the insulating film 13 are formed. On the other hand, as shown in FIG. 5B, since the n1 + layer 8 and the n2 + layer 9 are not arranged, the four-layer pnpn junction is not formed because the n1 + layer 8 and the n2 + layer 9 are not formed. Also, the IGBT region is not configured.

In the composite semiconductor device of the second embodiment, the internal equivalent circuit thereof is the first one shown in FIG.
Since it is the same as the internal equivalent circuit of the second embodiment and the operation is almost the same as that of the first embodiment, the detailed description of the operation of the second embodiment will be omitted.

Then, according to the second embodiment, as shown in FIG.
As shown in (b), the lower part of the transverse gate electrode 12-3 is the non-arranged portions of the n1 + layer 8 and the n2 + layer 9, and the p-layer 5 and the p2 + layer 6 are replaced at these non-arranged portions, respectively. Since they are arranged, the lateral resistances of the p layer 5 and the p2 + layer 6 corresponding to the non-arranged portions of the n1 + layer 8 and the n2 + layer 9 are small. Then, especially when the composite semiconductor device is turned off, the transverse gate electrode 12-3, the p2 + layer 6, p
Normally-on p-channel MISFET comprising layer 5
(M4), the transverse gate electrode 12-3, the p layer 5, n
-Normally-off type p consisting of layer 2, p layer 5 and p 2+ layer 6
Since the channel MISFETs (M4) are turned on, holes (hole current) flowing into the p- layer 7 under the n2 + layer 9 concentrate in the p layer 5 under the traverse gate electrode 12-3. Flow to reach the cathode electrodes 11 on both sides without passing through the lower part of the n1 + layer 8. Therefore, the first
In the same manner as in the embodiment of the above, the parasitic thyristor in the IGBT region formed by the second pnp transistor (Q3) and the second npn transistor (Q4) does not latch up, and compared with the known composite semiconductor device of this type, It is possible to increase the breakdown resistance and the load short-circuit resistance when turned on.

The composite semiconductor device of the second embodiment is
As shown in FIG. 5A, the transverse gate electrode 12-
3, the third n-channel MISFET (M3) composed of the n1 + layer 8, the p layer 5 and the n2 + layer 8 has an electron flow (thyristor current).
Since it is added as a current path of, there is an advantage that the ON voltage can be reduced as compared with the first embodiment. This point is
This is equivalent to the channel width of the third n-channel MISFET (M3) increased, and electrons flow from the cathode electrode 11 to the n2 + layer 9 in the thyristor region from four directions, so that an electron flow (thyristor current) Not only can be significantly increased, but also holes (hole current) flowing into the p- layer 7 in the lower portion of the n2 + layer 9 can be similarly extracted in four directions. Therefore, the second embodiment has an advantage that the parasitic thyristor in the IGBT region is less likely to latch up as compared with the first embodiment.

Next, FIG. 6 is a constitutional view of a third embodiment of the composite semiconductor device according to the present invention, in which (a) is a perspective view in which some of the constituent elements are partially removed, and (b) is shown. ) Also shows a plan view with some components partially removed.

In FIGS. 6A and 6B, the same components as those shown in FIG. 1 are designated by the same reference numerals.

The difference in structure between the third embodiment and the second embodiment is that the second embodiment has the first and second gate electrodes 1 and 2.
2-1 and 12-2 have different widths, whereas the third
Of the first and second gate electrodes 12-1, 12-
2 has the same width, and the second embodiment is p-
The layer 7 is arranged adjacent to one of the p layers 5, while the third layer
In this embodiment, the p @-layer 7 is arranged apart from both p layers 5, and there is no difference in structure between the third embodiment and the second embodiment.

Further, FIG. 7A is a sectional view taken along the line EE 'in the plan view shown in FIG. 6B, and FIG. 7B is a sectional view taken along the line FF' in the plan view. It is a figure. Although not shown, the sectional view taken along the line CC ′ of the same plan view
It is the same as the cross-sectional view shown in FIG.

In FIGS. 7A and 7B, as shown in FIG.
The same components as those shown in (a) and (b) are designated by the same reference numerals.

As shown in FIG. 7A, the portion where the n1 + layer 8 and the n2 + layer 9 are arranged has a thyristor region and an IGBT region which are arranged adjacent to each other in the semiconductor substrate 1, and the thyristor region is the anode electrode. 4, a p1 + layer 4, an n buffer layer 3, an n− layer 2, a p− layer 7, and an n2 + layer 9, which are four layers pnp
The n-junction portion is formed, and the IGBT region is formed by the anode electrode 1.
0, p1 + layer 4, n buffer layer 3, n- layer 2, p layer 5, p
A four-layer pnpn junction composed of a 2+ layer 6 and an n1 + layer 8 and a first
The gate electrode 12-1 and the insulating film 13 are formed. On the other hand, as shown in FIG. 7B, since the n1 + layer 8 and the n2 + layer 9 are not arranged, the four-layer pnpn junction portion is not formed and the thyristor region is not formed. Also, the IGBT region is not configured.

Also in the composite semiconductor device of the third embodiment, the internal equivalent circuit is the same as the internal equivalent circuit of the first embodiment shown in FIG. 3, and the operation is also the first. Since the operation is almost the same as that of the embodiment,
A detailed explanation of the operation of the third embodiment is also omitted.

Then, according to the third embodiment, as shown in FIG.
As shown in (b), the lower part of the transverse gate electrode 12-3 is the non-arranged portions of the n1 + layer 8 and the n2 + layer 9, and the p-layer 5 and the p2 + layer 6 are replaced at these non-arranged portions, respectively. Since they are arranged, the lateral resistances of the p layer 5 and the p2 + layer 6 corresponding to the non-arranged portions of the n1 + layer 8 and the n2 + layer 9 are small. Especially, when this composite semiconductor device is turned off, a normally-on type p-channel MIS composed of the transverse gate electrode 12-3, the p 2+ layer 6 and the p layer 5 is formed.
Since the FET (M4) and the normally-off p-channel MISFET (M4) including the transverse gate electrode 12-3, the p layer 5, the n- layer 2, the p layer 5, and the p2 + layer 6 are turned on, the n2 + layer is formed. The holes (hole current) flowing into the p- layer 7 in the lower portion of 9 flow concentratedly in the p layer 5 in the lower portion of the transverse gate electrode 12-3 and do not pass through the lower portion of the n1 + layer 8. To reach the cathode electrodes 11 on both sides. For this reason,
Similar to the first and second embodiments, the second pnp transistor (Q3) and the second npn transistor (Q4).
The parasitic thyristor in the IGBT region made of does not latch up, and the breakdown withstand capability at turn-off and the load short-circuit withstand capability at on can be increased respectively, as compared with the known composite semiconductor device of this type.

Further, in the composite semiconductor device of the third embodiment, as shown in FIG. 7A, the widths of the first and second gate electrodes 12-1 and 12-2 are made substantially equal, and
Since the p − layer 7 is arranged separately from both p layers 5, at the time of turn-on, holes (hole current) flowing from the n − layer 2 to the p − layer 7 are present on both sides of the cathode electrode 1.
There is no direct flow to 1. Therefore, the potential of the p- layer 7 is less affected by the potential of the cathode electrode 11, and the potential easily rises, so that the thyristor region operates more easily than in the second embodiment. The advantage is that the on-voltage can be reduced.

Next, FIG. 8 is a constitutional view of a fourth embodiment of the composite semiconductor device according to the present invention, wherein (a) is a perspective view in which some of the constituent elements are partially removed, and (b) is shown. ) Also shows a plan view with some components partially removed.

In FIGS. 8A and 8B, the same components as those shown in FIG. 1 are designated by the same reference numerals.

The difference between the fourth embodiment and the second embodiment is that the second embodiment has a regular strip shape on the surface of the two p 2+ layers 6 along the longitudinal direction of the semiconductor substrate 1. While the n1 + layer 8 is selectively arranged, in the fourth embodiment, one p
The strip-shaped n1 + layers 8 are regularly arranged on the surface of the 2+ layer 6 along the longitudinal direction of the semiconductor substrate 1, but no n1 + layer 8 is arranged on the surface of the other p2 + layer 6. However, there is no difference in structure between the fourth embodiment and the second embodiment.

Also in the composite semiconductor device of the fourth embodiment, the internal equivalent circuit is the same as the internal equivalent circuit of the first embodiment shown in FIG. 3, and the operation is also the first. Since the operation is almost the same as that of the embodiment,
A detailed explanation of the operation of the fourth embodiment is also omitted.

In the composite semiconductor device of the fourth embodiment, the normally-on type p-channel MISFE formed in the lower part of the second gate electrode 12-2 at the time of turn-off.
T (M4) and normally-off p-channel MISFE
When T (M4) is turned on, holes (hole current) flowed from the n− layer 2 into the p− layer 7 under the n2 + layer 9.
Is to be swept out to the cathode electrode 11 through the entire side edge portion in the longitudinal direction of the semiconductor substrate 1, so that there is an advantage that the breakdown resistance at turn-off can be increased as compared with the second embodiment.

By the way, if no n1 + layer 8 is arranged on the surface of the other p2 + layer 6 as in the fourth embodiment, electrons will not flow from the n1 + layer 8 to the n2 + layer 9 at that portion. , The electrons flowing from the n1 + layer 8 to the n2 + layer 9 in the portion are the first MISFET (M1) and the second MISFET.
Since it has to pass through the two n-channel portions of (M2), and the amount of current is relatively small, the internal resistance of the composite semiconductor device is increased (the on-voltage is increased by not arranging the n1 + layer 8 of the portion). ) Is small. Further, when the composite semiconductor device is turned on, the MIS current (electrons) for firing the thyristor region is generated by the first and second gate electrodes 12-1 and 12-2 and the pair of transverse gate electrodes 1.
Since it is supplied from the n1 + layer 8 in the area surrounded by 2-3, the thyristor does not ignite.

Next, FIG. 9 is a constitutional view of a fifth embodiment of the composite semiconductor device according to the present invention, in which (a) is a perspective view in which some of the components are partially removed, and (b) is shown. ) Also shows a plan view with some components partially removed.

In FIGS. 9A and 9B, the same components as those shown in FIG. 1 are designated by the same reference numerals.

The difference between the structures of the fifth embodiment and the fourth embodiment is that the fourth embodiment has a regular strip shape along the longitudinal direction of the semiconductor substrate 1 only on the surface of one p2 + layer 6. N1
While the + layer 8 is selectively arranged, in the fifth embodiment,
The only difference is that no n1 + layer 8 is arranged on the surface of one p2 + layer 6, and other than that, there is no structural difference between the fifth embodiment and the fourth embodiment.

Also in the composite semiconductor device of the fifth embodiment, the internal equivalent circuit is almost the same as the internal equivalent circuit of the first embodiment shown in FIG. 3, and
Since the operation is almost the same as that of the first embodiment, detailed explanation of the operation of the fourth embodiment will be omitted.

Then, the composite semiconductor device of the fifth embodiment has the first and second gate electrodes 12-2 at the time of turn-off.
Normally-on p-channel M formed in the lower part of the
ISFET (M4) and normally-off type p-channel M
When the ISFET (M4) is turned on, n- layer 2 to n2 +
The holes (hole currents) flowing into the p − layer 7 in the lower portion of the layer 9 are swept out to the cathode electrode 11 through the entire side edges of the semiconductor substrate 1 in the longitudinal direction.
Compared with the fourth embodiment, there is an advantage that the breakdown resistance at turn-off can be significantly increased.

If no n1 + layers 8 are arranged on the surfaces of the two p2 + layers 6 as in the fifth embodiment, n1 + is formed.
Electrons do not flow from layer 8 to n2 + layer 9,
The electrons flowing from the n1 + layer 8 to the n2 + layer 9 are the first MISF.
Since the two n-channel portions of the ET (M1) and the second MISFET (M2) have to be passed through, and the amount of current is relatively small, the composite semiconductor device is not provided by disposing the two n1 + layers 8. The increase in internal resistance (increase in ON voltage) is small. Also, when the composite semiconductor device is turned on, the MIS current (electrons) for igniting the thyristor region is generated by the first and second gate electrodes 12-.
Since it is supplied from the n1 + layer 8 in the region surrounded by 1, 12-2 and the pair of transverse gate electrodes 12-3, the thyristor does not ignite.

Next, FIG. 10 is an electric circuit diagram showing an example of a three-phase inverter circuit configured by using the composite semiconductor device according to the present invention.

In FIG. 10, T ₁ and T ₂ are DC power supply terminals, SW ₁₁ , SW ₁₂ , SW ₂₁ , SW ₂₂ , SW ₃₁ , and SW _32.
Is a composite semiconductor device of the present invention, D ₁₁ , D ₁₂ , D ₂₁ , D ₂₂ ,
D ₃₁ and D ₃₂ are flywheel diodes, SB ₁₁ and SB
₁₂ , SB ₂₁ , SB ₂₂ , SB ₃₁ , SB ₃₂ are snubber circuits,
M is a three-phase AC motor.

[0075] Then, the composite semiconductor device SW _11, SW ₁₂ are connected in series between the DC power supply terminals T _1, T _2, the flywheel diode D ₁₁ and the snubber circuit SB ₁₁ is connected in parallel to the composite semiconductor device SW _11, the composite The flywheel diode D ₁₂ and the snubber circuit SB ₁₂ are connected in parallel to the semiconductor device SW ₁₂ . The composite semiconductor device SW _21, SW ₂₂ is also connected in series between the DC power supply terminals T _1, T _2, the flywheel diode D ₂₁ and the snubber circuit SB ₂₁ is connected in parallel to the composite semiconductor device SW _21, the composite semiconductor device SW _A flywheel diode D ₂₂ and a snubber circuit SB ₂₂ are connected in parallel to ₂₂ . Furthermore, the composite semiconductor devices SW ₃₁ , SW _32
1 also DC power terminal T, connected in series between T _2, the flywheel diode D ₃₁ and the snubber circuit SB ₃₁ is connected in parallel to the composite semiconductor device SW _31, a flywheel diode D ₃₂ and a snubber circuit to the composite semiconductor device SW ₃₂ SB ₃₂ is connected in parallel. The connection points of the composite semiconductor devices SW ₁₁ and SW ₁₂ , the connection points of the composite semiconductor devices SW ₂₁ and SW ₂₂ , and the connection points of the composite semiconductor devices SW ₃₁ and SW ₃₂ are respectively connected to the inputs of the three-phase AC motors, and as a whole. It constitutes a three-phase inverter circuit.

Composite semiconductor devices SW ₁₁ , SW according to the present invention
₁₂ , SW ₂₁ , SW ₂₂ , SW ₃₁ , SW ₃₂ are the first and second
It can be easily turned on / off by applying / removing a control voltage to / from the gate electrodes 12-1 and 12-2.
For example, unlike the known GTO thyristor, it is not necessary to apply a large amount of current to the gate electrode and it is not necessary to draw a large amount of current from the gate electrode, so that the configuration of the gate drive circuit is extremely simplified.

Further, the composite semiconductor device S according to the present invention
Since W ₁₁ , SW ₁₂ , SW ₂₁ , SW ₂₂ , SW ₃₁ , and SW ₃₂ utilize the saturation characteristics of the built-in MISFET, they can have a current limiting action despite the thyristor operation. Therefore, the composite semiconductor device S having such characteristics
If W ₁₁ , SW ₁₂ , SW ₂₁ , SW ₂₂ , SW ₃₁ , and SW ₃₂ are used in a three-phase inverter circuit, a large current can be controlled at a high speed without destroying the device due to a low ON voltage.
There is an advantage that a phase inverter circuit can be obtained.

Therefore, for example, as compared with a three-phase inverter circuit using a known GTO thyristor, the circuit can be made smaller, lighter in weight, lower in loss and lower in noise due to higher frequency and easier control. In comparison with a known three-phase inverter circuit using an IGBT, it is possible to achieve a large circuit capacity and a low loss due to a low on-voltage.

[0079]

As described above, according to the present invention,
At least a part of the n1 + layer (second emitter layer) 8 in the IGBT region of the composite semiconductor device is replaced with a p2 + layer (second base layer) 6, and a part of the n2 + layer (second emitter layer) 9 in the thyristor region is replaced with p. -Layer (second base layer) 7 is substituted, and the p- layer (second base layer) 7 in the thyristor region is passed through these substituted portions to the cathode electrode 11 via the p2 + layer (second base layer) 6 in the IGBT region. Since a charged particle (hole) coupling path to reach the hole is provided, holes pass from the p1 + layer (first emitter layer) 4 to the n− layer (first base layer) 2 to the p− layer (second base layer) in the thyristor region. When injected in 7, most of the hole current flows through the hole coupling passage, and the n1 + layer (second
P2 + layer (second base layer) 6 below the emitter layer 8
Since almost no current flows into the
Alternatively, even if an overcurrent caused by a short circuit of a load during operation flows in the composite semiconductor device, the IG based on the overcurrent is generated.
The voltage drop in the p2 + layer (second base layer) 6 in the BT region is small, and the parasitic thyristor in the IGBT region does not latch up.

As described above, according to the present invention, even if an overcurrent flows in the composite semiconductor device, the parasitic thyristor in the IGBT region does not latch up, so that the breakdown withstand capability during interruption and the load short circuit withstand capability during operation are different. There is an effect that a large composite semiconductor device can be obtained. Furthermore, according to the present invention, the occurrence of latch-up of the parasitic thyristor in the IGBT region can be reduced, so that it becomes possible to increase the area of knowledge of the thyristor region in which the main thyristor current flows, and the resistance loss at the time of ON (ON voltage It is also possible to obtain a composite semiconductor device having a small).

Further, according to the present invention, in the composite semiconductor device, at least a part of the sixth semiconductor layer (n1 + layer) 8 is replaced by the fourth semiconductor layer (p2 + layer) 6, and the seventh replacement portion and the seventh semiconductor portion. A second replacement portion obtained by replacing a part of the layer (n2 + layer) 9 with the fifth semiconductor layer (p- layer) 7 is provided, and passes through the first replacement portion from the fifth semiconductor layer (p- layer) 7 to the fifth semiconductor layer (p- layer) 7. A first charged particle (hole) coupling path reaching the second main electrode (K) 11 through each of the third semiconductor layer (p layer) 5 and the fourth semiconductor layer (p2 + layer) 6 is provided, and the second replacement portion is formed. Through the fifth semiconductor layer (p2 + layer) 6 to the first semiconductor layer (n- layer)
2, third semiconductor layer (p- layer) 5, fourth semiconductor layer (p2 +
The second main electrode (K) 11 through the respective layers 6)
Since the charged particle (hole) coupling passage is provided, holes are formed from the second semiconductor layer (p1 + layer) 4 to the first semiconductor layer (n- layer) 2
When injected into the fifth semiconductor layer (p- layer) 7 via the above, most of the hole current flows through the first and second hole coupling passages, and the lower part of the sixth semiconductor layer (n1 + layer) 8 Fourth
Since the current does not flow to the semiconductor layer (p2 + layer) 6, even if an overcurrent flows in the composite semiconductor device, the voltage drop in the fourth semiconductor layer (p2 + layer) 6 due to the overcurrent is slight, and the composite semiconductor The device does not latch up.

As described above, according to the present invention, even if an overcurrent flows in the composite semiconductor device, latch-up does not occur, so that the composite semiconductor has a large breakdown withstand capability during interruption and a large load short circuit withstand capability during operation. It is possible to obtain a device, and at the same time, by reducing the occurrence of latch-up, the area occupied by the main current flowing region (n2 + layer) 9 is expanded, and the resistance loss (ON voltage) at the time of ON is small. There is also an effect that a semiconductor device can be obtained.

[Brief description of drawings]

FIG. 1 is a perspective view and a plan view of a first embodiment of a composite semiconductor device according to the present invention.

2 is a cross-sectional view taken along the line AA 'and the line BB' in the plan view shown in FIG.

FIG. 3 is a circuit configuration diagram showing an internal equivalent circuit of the composite semiconductor device shown in FIG.

FIG. 4 is a perspective view and a plan view of a second embodiment of the composite semiconductor device according to the present invention.

5 is a cross-sectional view taken along line CC 'and line DD' in the plan view shown in FIG.

6A and 6B are a perspective view and a plan view of a third embodiment of the composite semiconductor device according to the present invention.

7 is a cross-sectional view taken along line EE 'and line FF' in the plan view shown in FIG.

8A and 8B are a perspective view and a plan view of a fourth embodiment of the composite semiconductor device according to the present invention.

9A and 9B are a perspective view and a plan view of a fifth embodiment of the composite semiconductor device according to the present invention.

FIG. 10 is an electric circuit diagram showing an example of a three-phase inverter circuit configured by using the composite semiconductor device according to the present invention.

FIG. 11 is a sectional view showing an example of the configuration of a known MIS gate type thyristor device.

FIG. 12 is a circuit diagram showing an internal equivalent circuit of a known MIS gate type thyristor device.

[Explanation of symbols]

1 semiconductor substrate 1a one main surface 1b the other main surface 2 n-type low impurity concentration first semiconductor layer (first base layer,
n− layer) 3 n-type buffer layer (first base layer, n-buffer layer) 4 p-type second semiconductor layer with high impurity concentration (first emitter layer, p1 + layer) 5 p-type third semiconductor layer (second base layer) Layer, p layer) 6 p-type high impurity concentration fourth semiconductor layer (second base layer,
p2 + layer) 7 p-type low impurity concentration fifth semiconductor layer (second base layer,
p- layer) 8 n-type high impurity concentration sixth semiconductor layer (second emitter layer, n1 + layer) 9 n-type high impurity concentration seventh semiconductor layer (second emitter layer, n2 + layer) 10 anode electrode (first Main electrode) 11 Cathode electrode (second main electrode) 12-1 First gate electrode (control electrode) 12-2 Second gate electrode (control electrode) 12-3 Traverse gate electrode (control electrode) 13, 14 Insulating film

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Claims (8)

[Claims] 1. A semiconductor substrate having first and second major surfaces, and at least a first and a second base layer and a first and a second base layer, respectively.
An IGBT region having a second emitter layer and a thyristor region are arranged adjacent to each other, an anode electrode is provided on the first main surface, a cathode electrode and an insulated gate electrode are provided on the second main surface, respectively, and the first region in the IGBT region is provided. 2, a MISFET is formed on the main surface side, the first emitter layer in the IGBT region and the thyristor region is conductively connected to the anode electrode, and the second emitter layer and the second base layer in the IGBT region are the cathode electrode. Conductively connected to
If the second emitter layer in the thyristor region is the MIS
In the composite semiconductor device, which is arranged to be coupled to the second emitter layer of the IGBT region via a FET, the IGBT
At least a part of the second emitter layer in the T region is replaced with the second base layer, and a part of the second emitter layer in the thyristor region is replaced with the second base layer, and the thyristor region is passed through the replacement part. 7. A composite semiconductor device, comprising: a charged particle coupling path extending from the second base layer to the cathode electrode through the second base layer in the IGBT region. 2. The charged particle coupling path includes a first coupling path from the second base layer in the thyristor area to a second base layer in the IGBT area via the MISFET, and a second coupling path in the thyristor area. A second base layer from the base layer directly adjacent to the second base layer of the IGBT region
The composite semiconductor device according to claim 1, wherein the composite semiconductor device comprises a coupling passage. 3. The first coupling passage constitutes a normally-on type p-channel MISFET, and the second coupling passage constitutes a normally-off type p-channel MISFET. Composite semiconductor device. 4. A first semiconductor layer of at least a first conductivity type,
A second conductive type second semiconductor layer having a high impurity concentration, which is disposed adjacent to one surface of the first semiconductor layer, and a plurality of second conductive type second semiconductor layers selectively formed on a part of the other surface of the first semiconductor layer. A third semiconductor layer, a fourth semiconductor layer of the second conductivity type having a high impurity concentration selectively formed on a part of the surface of each of the third semiconductor layers, and a third part of the other surface of the first semiconductor layer. A second conductivity type fifth semiconductor layer having a low impurity concentration, which is selectively formed so as to be adjacent to one of the semiconductor layers, and a first conductivity type which is selectively formed on a part of each surface of the fourth semiconductor layer. A sixth semiconductor layer having a high impurity concentration, a semiconductor substrate having a seventh semiconductor layer having a high impurity concentration of the first conductivity type selectively formed on a part of the surface of the fifth semiconductor layer, and a second semiconductor layer. Conductive to the first main electrode conductively connected to the surface and to the fourth semiconductor layer and the sixth semiconductor layer The second main electrode is continuously connected to the third semiconductor layer, the first semiconductor layer, and the fifth semiconductor layer, which are exposed between the sixth semiconductor layer and the seventh semiconductor layer, and are insulated from each other. In a composite semiconductor device comprising a control electrode insulated between the sixth semiconductor layer and the seventh semiconductor layer and exposed on the exposed third semiconductor layer, at least a part of the sixth semiconductor layer is formed as the fourth semiconductor layer. The first replacement portion that has been replaced and the second replacement portion that replaces a portion of the seventh semiconductor layer with the fifth semiconductor layer are respectively provided, and through the first replacement portion, from the fifth semiconductor layer to the above A first charged particle coupling path is formed through the third semiconductor layer and the fourth semiconductor layer to reach the second main electrode, and the fifth semiconductor layer to the first semiconductor layer are passed through the second replacement portion. And the third semiconductor layer Composite semiconductor device characterized by the formation of the second charged particle binding passage leading to the second main electrode through each said fourth semiconductor layer. 5. The first replacement portion and the second replacement portion are regularly arranged along a longitudinal direction of the semiconductor substrate,
The composite semiconductor device according to claim 4, wherein the composite semiconductor device is provided at substantially coincident positions. 6. The first replacement portion and the second replacement portion are regularly provided along the longitudinal direction of the semiconductor substrate, and the shape of the first replacement portion is the shape of the semiconductor substrate. 5. The composite semiconductor device according to claim 4, wherein the composite semiconductor device has a rectangular shape whose longitudinal direction is a long side direction, and the second replacement portion has a rectangular shape whose longitudinal direction is a short side direction. . 7. The first replacement portion is provided over the entire length in the longitudinal direction of the semiconductor substrate, and the second replacement portion is regularly provided along the longitudinal direction of the semiconductor substrate. The composite semiconductor device according to claim 4. 8. A set of at least three circuit branches comprising a pair of controllable elements connected in series, a DC power supply and a three-phase induction motor, wherein the three sets of circuit branches are connected between the power supply terminals of the DC power supply. In the three-phase power conversion device, wherein the connection point of a pair of controllable elements in the three sets of circuit branches is connected to the three-phase induction motor, the controllable element is any one of claims 1 to 7. A three-phase power conversion device, which is the composite semiconductor device according to item 1.