JPH07335774A - Bimos semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To lower production costs without lowing current driving capability of a bipolar transistor section and regardless of having a high resistance region in a MOS transistor section. CONSTITUTION:A part of an emitter of a bipolar transistor 62 and wiring of a high resistance load SRAM 61 are formed by a polycrystallineSi layer 53 of the same layer. In a portion to be a resistance element of the wiring of the high resistance load SRAM 61, an SiO2 layer 65 is formed in a portion in the direction of thickness, thus forming a thinner polycrystalline Si layer 53a. Thus, a smaller number of manufacture processes and hence lower production costs than in the case of forming separate polycrystal Si layers may be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BiMOS semiconductor device including a bipolar transistor portion and a MOS transistor portion, and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 4 shows an equivalent circuit of a memory cell of a high resistance load type SRAM. The flip-flop 11 of this memory cell is a driving NMOS transistor 1
2, 13 and load resistance elements 14 and 15, and the flip-flop 11 and transfer NMOS transistors 16 and 17 form a memory cell.

A ground line 21 is connected to the sources of the NMOS transistors 12 and 13, and the resistance elements 14 and 15 are connected.
A power supply line 22 is connected to. Also, the word line 23
Is the gate wiring of the NMOS transistors 16 and 17, and one of the source / drain of each of the NMOS transistors 16 and 17 is a true complementary bit line 24 or 2.
5 is connected.

FIG. 5 shows the high resistance load type SRA shown in FIG.
1 shows a conventional example of a BiMOS semiconductor device including M and a bipolar transistor. In order to manufacture this conventional example, as shown in FIG. 6A, a P-type Si substrate 31 is used.
Boron and phosphorus are selectively ion-implanted into the P-well 32 and the collector of the P-well 32 and the bipolar transistor.
Well 33 is formed.

After that, a SiO ₂ film having a thickness of about 400 nm is formed.
A film 34 is formed by the LOCOS method to partition the element isolation region, and a SiO ₂ film 35 having a film thickness of about 16 nm is formed on the surface of the element active region to form a gate oxide film. Then, a poly-Si layer 36 having a film thickness of about 150 nm and doped with phosphorus and a WSi ₂ layer having a film thickness of about 150 nm are sequentially deposited on the entire surface to form a polycide layer 36. The gate wirings of the transistors 12 and 13 and the word line 23 are patterned.

Next, as shown in FIG. 6B, boron is ion-implanted using a resist (not shown) having a predetermined pattern and the SiO ₂ film 34 as a mask to form a base P of the bipolar transistor. The diffusion layer 37 is formed in the N well 33.

Then, using a resist (not shown) having a predetermined pattern, the polycide layer 36 and the SiO ₂ film 34 as a mask, an acceleration energy of 30 keV and 5 × 10 ^{15 are used.}
Arsenic is ion-implanted at a dose of cm ⁻² to form an N ⁺ diffusion layer 41 serving as the source / drain of the NMOS transistors 12, 13, 16 and 17 in the P well 32, and a collector electrode extraction region of the bipolar transistor. An N ⁺ diffusion layer (not shown) is formed in the N well 33.

Next, as shown in FIG. 6C, the film thickness is 15
The SiO ₂ layer 42 is about 0nm is deposited on the entire surface as an interlayer insulating film, reaching the N ⁺ diffusion layer 41 which is the source of the NMOS transistors 12 and 13 connecting hole 43 of SiO ₂
It is formed in the layer 42 or the like. And, the film thickness is about 100 nm and the phosphorus-doped polycrystalline Si layer has a film thickness of 100 nm.
A WSi ₂ layer of a certain degree is sequentially deposited on the entire surface to form a polycide layer 44, and the polycide layer 44 is processed into the pattern of the ground line 21.

Next, as shown in FIG. 7A, the film thickness is 10
A SiO ₂ layer 45 having a thickness of about 0 nm is deposited on the entire surface as an interlayer insulating film, and the N ⁺ diffusion layer 41 and the NMOS transistors 13 and 12 to be the drains of the NMOS transistors 12 and 13 and the other sources / drains of the NMOS transistors 16 and 17 are formed. A contact hole 46 reaching both of the gate wiring and the polycide layer 36 is formed in the SiO ₂ layers 45, 42 and the like.

After that, a polycrystalline Si layer 47 having a film thickness of about 50 nm is deposited on the entire surface, and this polycrystalline Si layer 47 is processed into a pattern of the resistance elements 14 and 15 and the power supply line 22. Then, by using a resist (not shown) having a predetermined pattern as a mask, the resistive element 1 in the polycrystalline Si layer 47 is
The acceleration energy of 30 keV and 3 × 10 ¹⁵ c are applied to the connection portion between the Nos. 4 and 15 and the N ⁺ diffusion layer 41 and the power supply line 22.
Arsenic is ion-implanted at a dose of m ^-2 .

Next, as shown in FIG. 7B, the film thickness is 10
A SiO ₂ layer 51 having a thickness of about 0 nm is deposited on the entire surface as an interlayer insulating film, and the connection hole 52 reaching the P diffusion layer 37 is formed with Si.
It is formed on the O ₂ layers 51, 45, 42 and the like. Then, a polycrystalline Si layer 53 having a film thickness of about 120 nm is deposited on the entire surface, and the polycrystalline Si layer 53 is processed into an emitter pattern of a bipolar transistor.

After that, arsenic is ion-implanted into the polycrystalline Si layer 53 with an acceleration energy of 30 keV and a dose amount of 3 × 10 ¹⁵ cm ^-2 . Then, the polycrystalline Si layer 5 is formed by heat treatment.
Arsenic is diffused from 3 to form an N ⁺ diffusion layer 54 in the P diffusion layer 37, which becomes a part of the emitter of the bipolar transistor.

Next, as shown in FIG. 5, the interlayer insulating film 55 is formed.
Of the contact holes 56 reaching the polycrystalline Si layer 53
And a connection hole (not shown) reaching the N ⁺ diffusion layer 41 which is one source / drain of the NMOS transistors 16 and 17 are formed in the interlayer insulating film 55 and the like.

Then, the Al layer 57 is deposited on the entire surface, and the Al layer 57 is processed into a pattern of the emitter electrode and the bit lines 24, 25 for lowering the emitter series resistance, and the high resistance load type SRAM 61 and the bipolar transistor. And 62. After that, a surface protective film (not shown)
Etc. are formed to complete the BiMOS semiconductor device 63.

[0015]

By the way, if the emitter is formed by any one of the polycide layers 36, 44 and the polycrystalline Si layer 47, the polycrystalline Si layer 53 becomes unnecessary and the manufacturing process is reduced. This has traditionally been considered because of the low cost.

However, in the polycide layer, redistribution of impurities generally occurs due to segregation of impurities in the polycrystalline Si layer forming the polycide layer at the interface between the polycrystalline Si layer and the silicide layer or in the silicide layer. As a result, the resistance value of the polycrystalline Si layer increases. Therefore, the polycide layers 36, 4
If the emitter is also formed in step 4, the emitter series resistance increases and the current driving capability of the bipolar transistor decreases.

Further, the polycrystalline Si layer 47 is composed of the resistance element 14,
Since it is also used to form 15, the polycrystalline Si layer 47 is usually as thin as several tens of nm in order to increase the resistance value. On the other hand, since the connection hole 56 is formed on the polycrystalline Si layer 53, the polycrystalline S layer is formed by the etching.
The thickness of the polycrystalline Si layer 53 needs to be thicker than about 100 nm so that the i layer 53 is not lost. Therefore,
The requirements for the polycrystalline Si layers 47 and 53 are inconsistent with each other, and one of them cannot serve as the other.

[0018]

A BiMOS semiconductor device 63 according to a first aspect of the present invention includes a first semiconductor layer 53 which is a part of an emitter of a bipolar transistor portion 62 and has a relatively thick film thickness, and a MOS transistor portion. The second semiconductor layer 53, which has the wiring 61 and has a relatively thin film thickness in at least a part of the region 53a, is formed of the same semiconductor layer 53.

According to a second aspect of the present invention, there is provided a method of manufacturing a BiMOS semiconductor device 63, wherein a step of processing the semiconductor layer 53 of the same layer into a pattern of a part of the emitter of the bipolar transistor section 62 and the wiring of the MOS transistor section 61, and And a step of oxidizing a part of the semiconductor layer 53 in the film thickness direction in at least a part of the part 53a to be the wiring.

A method of manufacturing a BiMOS semiconductor device 63 according to a third aspect is the method of manufacturing a BiMOS semiconductor device 63 according to the second aspect, wherein a region of the semiconductor layer 53 other than the partial region 53a is a mask layer 64. The method is characterized by including a step of covering and a step of performing the oxidation using the mask layer 64 as a mask.

A method of manufacturing the BiMOS semiconductor device 63 according to a fourth aspect is the method of manufacturing the BiMOS semiconductor device 63 according to the third aspect, wherein impurities are introduced into the semiconductor layer 53 by using the oxide film 65 formed by the oxidation as a mask. It is characterized by having a step of performing.

A method of manufacturing a BiMOS semiconductor device 63 according to a fifth aspect of the present invention includes a step of processing the semiconductor layer 53 of the same layer in a pattern of a part of the emitter of the bipolar transistor portion 62 and the wiring of the MOS transistor portion 61, and A step of etching a part of the semiconductor layer 53 in the film thickness direction in at least a part of the part 53a to be the wiring.

[0023]

In the BiMOS semiconductor device 63 according to claim 1, since the semiconductor layer 53 is not a polycide layer as a part of the emitter of the bipolar transistor portion 62, the emitter series resistance caused by the redistribution of the impurities. Of the semiconductor layer 5 which does not increase and is a part of the emitter.
Since the film thickness of 3 is relatively thick, the emitter is surely left even if the connection hole 56 for the emitter electrode 57 is formed.

Furthermore, since the film thickness of at least a part of the region 53a of the semiconductor layer 53 which is the wiring of the MOS transistor portion 61 is relatively thin, this part of the region 53 is formed.
The resistance value of a is relatively high. Moreover, the semiconductor layer 53 which is a part of the emitter and the semiconductor layer 5 which is the wiring
3 and 3 are formed from the same semiconductor layer 53,
Only a few manufacturing steps are required.

In the method of manufacturing the BiMOS semiconductor device 63 according to the second aspect, since the semiconductor layer 53, not the polycide layer, forms part of the emitter of the bipolar transistor portion 62, the emitter series resistance caused by the redistribution of the impurities. There is no increase in

In the semiconductor layer 53 of the same layer, MO
Since at least a part of the portion of the S transistor portion 61 to be the wiring in the region 53a in the film thickness direction is oxidized, the film thickness of the semiconductor layer 53 to be a part of the emitter becomes relatively thick. The film thickness in at least a part of the region 53a to be the wiring becomes relatively thin.

Therefore, the connection hole 5 for the emitter electrode 57 is formed.
Even if 6 is formed, the emitter remains without fail, and the resistance value of at least a part of the region 53a to be the wiring becomes relatively high. Moreover, since a part of the emitter and the wiring are formed from the same semiconductor layer 53, the number of manufacturing steps is small.

In the method for manufacturing the BiMOS semiconductor device 63 according to the third aspect, at least a part of the semiconductor layer 53, which is to be the wiring of the MOS transistor portion 61, is a region 53.
Since the oxidation is performed using the mask layer 64 covering the region other than a as a mask, only the desired region of the semiconductor layer 53 can be selectively oxidized.

In the method for manufacturing the BiMOS semiconductor device 63 according to the fourth aspect, the oxide film 65 formed on the semiconductor layer 53 is used as a mask to introduce impurities into the semiconductor layer 53, and a new mask layer is introduced for this introduction. Therefore, although the mask layer 64 is formed to form the oxide film 65, the total number of steps is not increased.

In the method of manufacturing the BiMOS semiconductor device 63 according to the fifth aspect, since the semiconductor layer 53, not the polycide layer, forms part of the emitter of the bipolar transistor portion 62, the emitter series resistance caused by the redistribution of the impurities. There is no increase in

In the semiconductor layer 53 of the same layer, MO
Since at least a part of the portion of the S-transistor portion 61 to be the wiring in the region 53a is etched in the film thickness direction, the semiconductor layer 53 to be a part of the emitter becomes relatively thick. The film thickness in at least a part of the region 53a to be the wiring becomes relatively thin.

Therefore, the connection hole 5 for the emitter electrode 57 is formed.
Even if 6 is formed, the emitter remains without fail, and the resistance value of at least a part of the region 53a to be the wiring becomes relatively high. Moreover, since a part of the emitter and the wiring are formed from the same semiconductor layer 53, the number of manufacturing steps is small.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to a BiMOS semiconductor device including a high resistance load type SRAM and a bipolar transistor will be described below with reference to FIGS. The components corresponding to those of the conventional example shown in FIGS.

Although FIG. 1 shows this embodiment, also in the manufacture of this embodiment, as shown in FIGS. 2 (a) to 2 (c), the ground line 21 is formed by the polycide layer 44, and FIG. As shown in (a), substantially the same steps as those of the above-mentioned conventional example are executed until the SiO ₂ layer 45 as an interlayer insulating film is deposited on the entire surface.

However, in this embodiment, as shown in FIG. 3A, thereafter, the N ⁺ diffusion layer 41 and the NMOS serving as the drains of the NMOS transistors 12 and 13 and the other sources / drains of the NMOS transistors 16 and 17 are formed. A contact hole 46 reaching both of the polycide layer 36 which will be the gate wiring of the transistors 13 and 12 and a contact hole 52 reaching the P diffusion layer 37 are simultaneously formed in the SiO ₂ layers 45, 42 and the like.

Then, a polycrystalline Si layer 53 having a film thickness of about 120 nm is deposited on the entire surface, and the polycrystalline Si layer 53 is formed.
Are processed into patterns of the resistance elements 14 and 15, the power supply line 22 and the emitter of the bipolar transistor.

Next, as shown in FIG. 3B, the film thickness is 20
A Si ₃ N ₄ film 64 having a thickness of about nm is deposited on the entire surface, and a portion of the Si ₃ N ₄ film 64 on the region where the resistance elements 14 and 15 are to be formed is removed. Then, using the Si ₃ N ₄ film 64 as a mask, the polycrystalline Si layer 53 is oxidized in a steam atmosphere at 950 ° C.

As a result, in the portion where the Si ₃ N ₄ film 64 is removed, the SiO ₂ layer 6 having a film thickness of about 120 nm is formed.
5 is formed, and the SiO ₂ layer 6 is included in the polycrystalline Si layer 53.
The portion under 5 becomes a polycrystalline Si layer 53a having a film thickness of about 55 nm. The line width of the polycrystalline Si layer 53a is 0.4 μ, which is thinner than the polycrystalline Si layer 53 by about 0.1 μm.
It will be about m.

After that, arsenic is ion-implanted into the polycrystalline Si layer 53 with an acceleration energy of 50 keV and a dose amount of 3 × 10 ¹⁵ cm ^-2 . This ion implantation is performed on the entire surface,
With the above acceleration energy, arsenic penetrates the Si ₃ N ₄ film 64 but does not penetrate the SiO ₂ layer 65.
The O ₂ layer 65 serves as a mask.

Therefore, in the polycrystalline Si layer 53, the connection portion between the resistance elements 14 and 15 and the N ⁺ diffusion layer 41 and the power supply line 2 are connected.
Arsenic is ion-implanted only in the second portion and the emitter portion of the bipolar transistor. After that, arsenic is diffused from the polycrystalline Si layer 53 by heat treatment to form an N ⁺ diffusion layer 54 in the P diffusion layer 37, which becomes a part of the emitter of the bipolar transistor.

Next, as shown in FIG. 1, the interlayer insulating film 55 is formed.
Are formed to be flat and reach the polycrystalline Si layer 53 that becomes the emitter of the bipolar transistor and the connection hole that reaches the N ⁺ diffusion layer 41 that is one of the sources / drains of the NMOS transistors 16 and 17 (not shown). And are formed on the interlayer insulating film 55, the Si ₃ N ₄ film 64, and the like.

Then, the Al layer 57 is deposited on the entire surface, and the Al layer 57 is processed into a pattern of the emitter electrode and the bit lines 24, 25 for reducing the emitter series resistance, and the high resistance load type SRAM 61 and the bipolar transistor are formed. And 62. After that, a surface protective film (not shown)
Etc. are formed to complete the BiMOS semiconductor device 63.

In the above embodiment, the SiO ₂ layer 65 is used.
Although the Si ₃ N ₄ film 64 was used as a mask during the oxidation for forming the film, a SiO ₂ layer or the like that allows oxygen to pass to some extent may be used instead of the Si ₃ N ₄ film 64. Even in this case, the polycrystalline Si layer 53 is slightly oxidized in the portion where the SiO ₂ layer or the like is formed, and the polycrystalline Si layer 53 is largely oxidized in the portion where the SiO ₂ layer or the like is not formed.
The film thickness of the polycrystalline Si layer 53 can be made different for each part, as in the above-described embodiment.

Further, in the above-mentioned embodiment, the polycrystalline Si layer 5 is used.
Although the SiO ₂ layer 65 is formed by oxidation in order to reduce the film thickness of the portions of the No. 3 which should be the resistance elements 14 and 15, the thickness of this portion may be reduced by etching.

Further, the above-mentioned embodiment is a high resistance load type SRA.
Although the invention of the present application is applied to a BiMOS semiconductor device including M, a BiMOS including a TFT load type SRAM
The invention of the present application can also be applied to semiconductor devices and the like.
In this case, of the polycrystalline Si layer 53, the SiO ₂ layer 65
The thin portion below is used as the channel region of the TFT to reduce the off-current of this TFT, and at the same time, the SiO ₂ layer 6
The source / drain of the TFT is formed by ion implantation of impurities using 5 as a mask.

[0046]

According to the BiMOS semiconductor device of the first aspect,
Since the series resistance of the emitter does not increase, the current driving capability of the bipolar transistor section is high, and the yield is high because the emitter remains reliably, and the resistance value of at least a part of the wiring of the MOS transistor section is high. However, the manufacturing cost is low because the number of manufacturing steps can be small, even though the partial resistance can be made a high resistance region.

In the method for manufacturing the BiMOS semiconductor device according to the second and the fifth aspects, the current driving capability of the bipolar transistor portion can be increased because the emitter series resistance is not increased, and the emitter is surely left so that the yield is high. Further, since the resistance value of at least a part of the wiring of the MOS transistor portion is relatively high, this part of the area can be a high resistance region, but the number of manufacturing steps is small. Manufacturing costs can be reduced.

In the method of manufacturing the BiMOS semiconductor device according to the third aspect, only the desired region of the semiconductor layer can be selectively oxidized, so that the desired region can be made the high resistance region.

In the method for manufacturing the BiMOS semiconductor device according to the fourth aspect, the manufacturing process is increased because the total number of steps is not increased although the mask layer is formed to form the oxide film. There is no such thing.

[Brief description of drawings]

FIG. 1 is a side sectional view of an embodiment of the present invention.

FIG. 2 is a side sectional view sequentially showing the first half of the manufacturing process of the embodiment.

FIG. 3 is a side sectional view sequentially showing a second half of the manufacturing process of the embodiment.

FIG. 4 is an equivalent circuit diagram of a memory cell of a high resistance load type SRAM that can be included in a BiMOS semiconductor device.

FIG. 5 is a side sectional view of a conventional example of the invention of the present application.

FIG. 6 is a side sectional view sequentially showing a first half of a manufacturing process of a conventional example.

FIG. 7 is a side sectional view sequentially showing the second half of the manufacturing process of a conventional example.

[Explanation of symbols]

53 Polycrystalline Si Layer 53a Polycrystalline Si Layer 61 High Resistance Load SRAM 62 Bipolar Transistor 63 BiMOS Semiconductor Device 64 Si ₃ N ₄ Film 65 SiO ₂ Layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/786 21/336 9056-4M H01L 29/78 311 C 9056-4M 311 P

Claims (5)

[Claims] 1. A first semiconductor layer, which is a part of an emitter of a bipolar transistor portion and has a relatively large film thickness, and a wiring of a MOS transistor portion, and at least a partial region of the film thickness is relatively large. The second thin semiconductor layer is formed of the same semiconductor layer as the first semiconductor layer. 2. A step of processing a semiconductor layer of the same layer into a pattern of a part of an emitter of a bipolar transistor section and a wiring of a MOS transistor section, and at least one of the portions of the semiconductor layer to be the wiring. And a step of oxidizing a part in the film thickness direction in the partial region. 3. The method according to claim 2, further comprising a step of covering a region of the semiconductor layer other than the partial region with a mask layer, and a step of performing the oxidation using the mask layer as a mask. A method for manufacturing the BiMOS semiconductor device described. 4. The method for manufacturing a BiMOS semiconductor device according to claim 3, further comprising the step of introducing an impurity into the semiconductor layer using the oxide film formed by the oxidation as a mask. 5. A step of processing a semiconductor layer of the same layer in a pattern of a part of an emitter of a bipolar transistor section and a wiring of a MOS transistor section, and at least one of the portions of the semiconductor layer to be the wiring. And a step of etching a part in the film thickness direction in the partial region.