JPH065798A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To realize formation of good metallization by combining two resist patterning steps into one step without deteriorating reflow of interlayer insulation film. CONSTITUTION:The method for fabricating a semiconductor device, in which transistors of first and second conductivity types are formed on a same substrate 1, comprises a step for making contact holes 8 through the diffused regions 5, 6 and the interlayer insulation film 7 on the gate electrode 4 of each transistor, a step for implanting impurity ions of first conductivity type into the contact holes 8a of first and second conductivity type transistors while leaving a resist mask for forming a contact hole, a step for implanting impurity ions of second conductivity type into the contact hole of second conductivity type transistor, and a step for forming a metallization 18 in the contact hole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a P-channel transistor (Pch Tr) and an N-channel transistor (Nch T) on the same substrate.
and a method for manufacturing a CMOS transistor having r).

[0002]

2. Description of the Related Art As an example of manufacturing a MOS (complementary MOS) IC in which a circuit is composed of both Pch and Nch MOS transistors, a first conductivity type impurity and a second conductivity type are conventionally described with reference to FIGS. A method of selectively implanting type impurities into the contact holes by using different resist masks will be described.

In the following description, the first conductivity type impurity is N
The type and second conductivity type impurities are P-type, but the reverse is also possible.

First, FIG. 2A shows a sectional structure of a semiconductor device before etching a contact hole. Figure 2 (a)
Is a P well (second conductivity type) 2, N well (first conductivity type) 3, LOCOS oxide film 1a, gate electrode 4, Nch source / drain region 5, on a silicon (Si) substrate 1.
After forming the Pch source / drain regions 6, BPSG
FIG. 3 is a cross-sectional view showing a state where a (boron phosphorus silicate glass) interlayer insulating film 7 is deposited.

Next, as shown in FIG. 2B, a contact hole opening resist 8 is formed by coating on each of the source / drain regions 5 and 6 of the Tr and the gate electrode 4, and then the contact hole 9 is etched. Set up.

Next, after removing the resist 8, as shown in FIG. 3 (a), the first Nch Tr contact hole 8a is formed.
The Pch Tr region is covered with a resist 10 in order to perform compensation implantation 11 for conductivity type N-type impurities (phosphorus).
Phosphorus is ion-implanted only into the contact hole 8a in the r region.

Next, after removing the resist 10, FIG.
As shown in (b), Pch Tr contact hole 8
In order to perform compensation implantation 13 on the second conductivity type P-type impurity such as B ⁺ and BF ₂ ⁺ , the Nch Tr region is covered with the resist 12 and the P-type impurity is ion-implanted only in the Pch Tr region.

Next, in order to activate the contact hole compensation implanter and to reflow the BPSG interlayer insulating film 7, 9
Annealing is performed at 00 ° C., then an Al film is formed on the entire surface by a sputtering method, and after forming a resist pattern, the Al film is etched to form an Al wiring 18 (FIG. 3C).

In the subsequent steps, although not shown, forging annealing, overcoat CVD, and PAD opening are performed in the semiconductor device having a single-layer Al wiring, and in the semiconductor device having a multi-layer Al wiring, after forming the multilayer wiring, the forming process is performed. Thing annealing, overcoat CVD, and PAD opening are performed.

As described above, in the manufacturing method described as the first example of the prior art, the Nch Tr contact hole compensation implant resist 10 (FIG. 3A) and the Pch Tr contact hole compensation implant resist 12 (FIG. 3B). However, there is a drawback that the resist patterning of 2 takes 2 steps and man-hours.

Therefore, as a second example of the prior art, referring to FIGS. 2 and 4, Nc impurities (first conductivity type impurities) are ion-implanted into the entire surface without using a resist to obtain Nc.
Resist for hTr contact hole compensation implant 10
A manufacturing method in which (FIG. 3C) is simplified will be described.

First, as in the first example of the prior art, FIG.
After the steps of (a) and FIG. 2 (b), N used in the first example
ch Tr Contact hole compensation Implant resist 1
0 (FIG. 3A), N-type impurities (first conductivity type) are provided in all contact holes 8a and 8b in the Pch Tr and Nch Tr regions without a mask as shown in FIG. 4A. Ion implantation (compensation implantation) 14 of phosphorus of about 1 × 10 ¹³ to 1 × 10 ¹⁴ / cm ² is performed.

Next, as shown in FIG. 4B, Pch T
To compensate and implant P-type impurities such as B ⁺ and BF ₂ ⁺ only in the contact hole 8b of r, the Nch Tr side is covered with a resist 12, and the contact hole 8b in the Pch Tr region is covered with B ⁺ , BF ₂ ^+. P-type impurities such as 3 × 10
Ion implantation (compensation implantation) 13 is performed at about ^{15 to} 7 × 10 ¹⁷ / cm ² .

However, since a low concentration of phosphorus has already been implanted into the Pch Tr contact hole 8b by the maskless Nch Tr contact hole compensation implanter 14 shown in FIG. 4A, the Pch Tr contact hole 8b of FIG. N-type impurities are eliminated by the Pch Tr contact hole compensation implanter.

Next, the contact hole compensation implanter is activated and the BPSG interlayer insulating film 7 is reflowed at 900 ° C.
Annealing is performed at the temperature.

[0016]

Problem to be Solved by the Invention P shown in FIG.
The BPSG interlayer insulating film 7'in the ch Tr region has N
The type impurities are shown in FIG. 4A, and the P type impurities are shown in FIG.
Ions are implanted in step (b). In this way, B in which impurities of both N-type and P-type conductivity are ion-implanted
The PSG interlayer insulating film does not reflow well at about 900 ° C. Therefore, as shown in FIG. 4C in the Al wiring process, the Al wiring 1 is formed in the Nch Tr contact hole 16.
8 is formed well, but the coverage of the Al wiring 18 is reduced on the inner wall of the Pch Tr contact hole 15, and in the worst case, the Al wiring may be broken.

In view of the above-mentioned drawbacks of the prior art, the present invention uses two resist patterning steps as one step,
Moreover, it is an object of the present invention to provide a method for manufacturing a semiconductor device, which makes it possible to form excellent metal wiring without deteriorating the reflow of the interlayer insulating film.

[0018]

According to the present invention, there is provided a method of manufacturing a semiconductor device in which a transistor of a first conductivity type and a transistor of a second conductivity type are formed on the same substrate. A step of forming a contact hole in the drain diffusion region and an interlayer insulating film on the gate electrode, and removing impurities of the first conductivity type while leaving a resist mask for forming the contact hole, A step of implanting ions into a contact hole of a second conductivity type transistor, a step of implanting ions of the second conductivity type impurity into a contact hole of the second conductivity type transistor, and a step of forming a metal wiring in the contact hole. This is solved by a method for manufacturing a semiconductor device, which has the above.

In the present invention, the interlayer insulating film is preferably made of boron phosphosilicate glass.

[0020]

According to the present invention, as shown in FIG.
Ion implantation of a Nch Tr contact hole compensation implanter (first conductivity type) 17 is performed with the resist 8 for forming a contact hole for making contact with the ch and Nch source / drain regions left even after the contact hole is formed. ing. That is, this ion implantation allows the resist 10 for Nch Tr contact hole compensation implantation to be replaced with an etching resistant resist mask for forming contact holes, so that one resist patterning step can be omitted.

Moreover, in the present invention, as shown in FIG. 1A, N-type impurities are not ion-implanted into the BPSG interlayer insulating film 7 in the Pch Tr region due to the existence of the resist 8. Therefore, N-type and P-type impurities of both conductivity types are not ion-implanted into the BPSG interlayer insulating film 7, and good reflow is achieved.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a process sectional view for explaining an embodiment of the present invention.

In the present embodiment, N-type impurities (first conductivity type impurities) are ion-implanted while leaving the etching resistant resist mask for forming the contact holes, and thereby Nch is formed.
This is a manufacturing method step in which the resist 10 for Tr contact hole compensation implantation is omitted.

In this embodiment, first, a P well (second conductivity type) is formed on the silicon substrate 1 through the same steps as those described in the first example of the prior art (FIGS. 2A and 2B). ) 2, N well (first conductivity type) 3, LOCOS oxide film 1a, Nch
A source / drain region 5 and a Pch source / drain region 6 are formed, and further, a gate electrode 4, a BPSG interlayer insulating film 7, a contact hole opening resist 8 and a contact hole 9 are formed, and the structure of FIG. obtain.

In this embodiment, the thickness of the BPSG interlayer insulating film 7 is 0.5 μm and the width of the contact hole is 1 μm. After obtaining the structure of FIG. 1A, in this embodiment, contact hole formation is performed instead of the step of forming the Nch Tr contact hole compensation implant resist 10 (FIG. 3A) used in the first example of the prior art. As shown in FIG. 1A, the N-type impurities are left only in the silicon substrate 1 at the bottom of all the contact hole openings in the Pch Tr and Nch Tr regions with the etching-resistant resist mask 8 of FIG. As phosphorus 1 × 10 ¹³ to 1 × 10 ¹⁴
Ion implantation (compensation implantation) 17 is performed at about / cm ² .

In this ion implantation, a resist having a thickness of 1.5 μm remains on the contact hole and has a high aspect ratio. Therefore, a rotary platen is used for 20 to 20 μm.
Ions are implanted while rotating the wafer (substrate) at 50 rpm so that shadow regions where ions are not implanted do not occur.

Next, as shown in FIG. 1B, Pch T
As in the second example of the conventional technique 3 (FIG. 4B), only P-type impurities such as B ⁺ and BF ₂ ⁺ are added to the r contact hole 8b only.
Ion implantation is performed at about × 10 ^{15 to} 7 × 10 ¹⁵ / cm ² .

Then, for activation of the contact hole compensation implant and reflow of the BPSG interlayer insulating film 7, 9
Annealing is performed at a temperature of 00 ° C.

In this embodiment, the N-type impurities are not ion-implanted into the BPSG interlayer insulating film 7 in the Pch Tr region in the step of FIG. 1A, and the BPSG film is reflowed without any problem.

BPSG interlayer insulating film 7 by the above annealing
After the reflow, the Al film is formed by the sputtering method, and the Al wiring 18 is formed as shown in FIG.

Since the following steps are the same as those described in the prior art, description thereof will be omitted.

[0033]

As described above, according to the present invention, one step of resist patterning can be omitted, and further, the reflow of the interlayer insulating film for Al wiring can be performed well, and the Al wiring can be formed well. You can get it.

[Brief description of drawings]

FIG. 1 is a process sectional view for explaining an embodiment of the present invention.

FIG. 2 is a process sectional view (I) for explaining the first example of the conventional technique.

FIG. 3 is a process sectional view (II) for explaining the first example of the conventional technique.

FIG. 4 is a process sectional view for explaining the second example of the conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon (Si) substrate 2 P well (second conductivity type) 3 N well (first conductivity type) 4 Gate electrode 5 Nch source / drain (first conductivity type) 6 Pch source / drain (second conductivity type) 7 BPSG interlayer insulating film 7 ′ BP ion-implanted with N-type and P-type impurities
SG interlayer insulating film 8 Contact hole opening resist 9 Contact hole 10 Nch Tr contact hole compensation implant resist 11 Nch Tr contact hole compensation implant (first conductivity type) 12 Pch Tr contact hole compensation implant resist 13 Pch Tr contact hole Compensation implanter (second conductivity type) 14 Maskless Nch Tr contact hole Compensation implanter (first conductivity type) 15 Pch Tr contact hole 16 Nch Tr contact hole 17 Nch Tr contact hole Compensation implanter (first conductivity type) 18 Al wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 8617-4M H01L 21/265 X

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a first conductivity type transistor and a second conductivity type transistor are formed on the same substrate, wherein a source / drain diffusion region of each transistor and an interlayer insulating film on a gate electrode are formed. A step of forming a contact hole, and a step of ion-implanting the impurities of the first conductivity type into the contact holes of the transistors of the first conductivity type and the second conductivity type while leaving a resist mask for forming the contact hole. And a step of implanting ions of the second conductivity type impurity into a contact hole of the second conductivity type transistor, and a step of forming a metal wiring in the contact hole. 2. The method according to claim 1, wherein the interlayer insulating film is made of boron phosphosilicate glass.