JPH07335763A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit device, the number of processes of which is reduced and which can be manufactured in a self- alignment manner, and a manufacturing technique capable of easily producing the semiconductor integrated circuit device. CONSTITUTION:The manufacture of a semiconductor integrated circuit device has a process, in which a polycrystalline silicon film 13 is implanted with the ions of conductive impurities while using a gate electrode 16 as a mask and a semiconductor region 17 for a source and a semiconductor region 18 for a drain are formed, and a process, in which the semiconductor region 18 for the drain is implanted with the ions of impurities having a conductivity type reverse to the semiconductor region 18 for the drain through a hole 21 formed to a part of a capacity plate 20a shaped onto the semiconductor region 18 for the drain and a semiconductor region 22 having offset structure is formed. Accordingly, a self-alignment process can be adopted, and the semiconductor integrated circuit device can be manufactured by reducing the number of processes such as a photolithographic process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technology, and more particularly to a MOS (Metal Oxide) device.
Semiconductor) type semiconductor integrated circuit device.

[0002]

2. Description of the Related Art SRAM (Static Random Access Memor)
In the case of y), since the memory state is stable and the MOSFET is the main element, it is possible to obtain a semiconductor integrated circuit device which can easily be highly integrated and consumes less power.

In the SRAM, a TFT (Thin F
ilm Transister) has been adopted.

The TFT is an effective technique for increasing the degree of integration because it is a MOSFET in which a thin film made of amorphous silicon or polycrystalline silicon is used as an active region on a semiconductor substrate or the like.

[0005]

However, the above-mentioned TFT
The present inventor has found that there are various problems in the production of

That is, when the TFT is manufactured,
After forming a gate electrode on a part of the surface of an insulating film provided on a semiconductor substrate, a p-type semiconductor thin film made of amorphous silicon or polycrystalline silicon is used as an active region so as to cover the gate electrode. Then, after forming an n-type semiconductor region serving as a source and a drain in the active region by an ion implantation method, a drain near the gate electrode is formed to form an n-type semiconductor region serving as a drain of the offset structure. Therefore, a step of ion-implanting a p-type conductive impurity into a part of the n-type semiconductor region to be neutralized is required.

Therefore, in order to form a p-type semiconductor thin film serving as a source and a drain and a region to be neutralized, a photoresist film as a mask for selectively ion-implanting conductive impurities is formed. , A photolithography process such as developing after selectively exposing it using a photomask is required. Therefore, there is a problem that the number of masks increases and the number of steps also increases.

An object of the present invention is to provide a semiconductor integrated circuit device which can be manufactured in a small number of steps and can be manufactured in a self-aligned manner.

Another object of the present invention is to provide a manufacturing technique capable of easily manufacturing a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

The typical ones of the inventions disclosed in the present invention will be outlined below.

A semiconductor integrated circuit device of the present invention has a semiconductor region for a source, a semiconductor region for a drain, a gate electrode and a gate insulating film, and a semiconductor region for the drain and a first semiconductor below the gate electrode and the gate insulating film. A MOSFET having a second semiconductor region having an offset structure provided between the gate electrode, a gate electrode and an electric wiring layer having a hole corresponding to the second semiconductor region on the second semiconductor region. It is assumed that the electric wiring layer is provided on the surface of the insulating film provided on the drain semiconductor region.

The method of manufacturing a semiconductor integrated circuit device according to the present invention includes a step of forming a semiconductor region on the surface of an insulating film on a semiconductor substrate, and a gate electrode on a part of the surface of the semiconductor region via a gate insulating film. And a step of forming a source semiconductor region and a drain semiconductor region by ion-implanting a conductive impurity into the semiconductor region using the gate electrode as a mask, and a gate electrode and a drain semiconductor region are formed. Forming an electric wiring layer on the semiconductor region through an insulating film and forming a hole in a part of the electric wiring layer, and through the hole provided in a part of the electric wiring layer using the electric wiring layer as a mask. And a step of forming an offset structure semiconductor region by ion-implanting an impurity having a conductivity type opposite to that of the drain semiconductor region into the drain semiconductor region.

[0014]

According to the above-described semiconductor integrated circuit device of the present invention, the first semiconductor region for forming the source semiconductor region and the drain semiconductor region is previously formed as the semiconductor region as the TFT, and Due to the structure in which the gate insulating film and the gate electrode can be formed in the selective region of the first semiconductor region, the first electrode on one side of the gate electrode can be formed by the ion implantation method using the gate electrode as a mask. It is possible to form the source semiconductor region in the semiconductor region and the drain semiconductor region in the first semiconductor region on the other side of the gate electrode in a self-aligned manner.

An electric wiring layer having a hole corresponding to the second semiconductor region on the second semiconductor region, which is arranged on the surface of an insulating film provided on the gate electrode and drain semiconductor region. Since the electric wiring layer is provided, the electric wiring layer is used as a mask to form the second semiconductor region of the offset structure, and impurities are ion-implanted through the holes in the electric wiring layer to form the drain semiconductor region. Since it can be performed by ion implantation into the substrate, the electric wiring layer can be used as a mask in the ion implantation method when forming the second semiconductor region of the offset structure.

Therefore, the photolithography process for forming the source semiconductor region and the drain semiconductor region and the photolithography process for forming the second semiconductor region of the offset structure can be omitted, so that they can be formed. Since the formation of a photoresist film as a mask for selectively ion-implanting the conductive impurities of the above, the exposure process, the development process, the bake process, etc. are not necessary and the mask used for them is unnecessary, the semiconductor for the source is not required. The region and the semiconductor region for drain can be manufactured in a self-aligned manner by using the gate electrode, and the semiconductor integrated circuit device can be manufactured by reducing the number of steps such as reducing the photolithography step.

According to the method for manufacturing a semiconductor integrated circuit device described above, a step of forming a source semiconductor region and a drain semiconductor region by ion-implanting conductive impurities into the semiconductor region using the gate electrode as a mask, Using the electric wiring layer formed on the drain semiconductor region as a mask, ions of an impurity having a conductivity type opposite to that of the drain semiconductor region are ion-implanted into the drain semiconductor region through a hole provided in a part of the electric wiring layer. By including a step of forming a semiconductor region having an offset structure, the source semiconductor region and the drain semiconductor region can be formed in a self-aligned manner by using the gate electrode as a mask, and the drain semiconductor region has an offset structure. It can be formed by ion-implanting conductive impurities through holes provided in the electric wiring layer. Thus, the number of steps such as the photolithography step can be reduced, and the source semiconductor region and the drain semiconductor region can be manufactured in a self-aligned manner by using the gate electrode, and the semiconductor integrated circuit device can be easily manufactured. It can be manufactured at low cost by using manufacturing technology.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and a duplicate description will be omitted.

(Embodiment 1) FIGS. 1 to 10 are views showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention, and FIGS. 1 to 7, 9 and 10 are sectional views. 8 is a plan view. The semiconductor integrated circuit device and the manufacturing method thereof according to the present invention will be specifically described with reference to FIG.

First, as shown in FIG. 1, a plurality of MOSFETs are formed on a semiconductor substrate 1 made of p-type silicon single crystal or the like.
Wafer processing, which is a manufacturing process for forming semiconductor elements such as T and other diodes, is performed.

That is, after p-type impurities for forming a channel stopper for preventing inversion are ion-implanted into a region for forming an element isolation field insulating film which is an inactive region of the semiconductor substrate 1, the semiconductor substrate 1 A field insulating film 2 made of a thick silicon oxide film is formed by thermally oxidizing a selective region on the surface of the. In this case, the heat treatment diffuses the p-type impurities to form a channel stopper layer (not shown) made of a p-type diffusion layer.

Next, work is performed to form a MOSFET in the active region.

That is, after the gate insulating film 3 made of a silicon oxide film is formed on the surface of the semiconductor substrate 1, a polycrystalline silicon film containing conductive impurities is formed on the semiconductor substrate 1 by the CVD method, Next, after the silicon oxide film 5 is formed on the surface of the polycrystalline silicon film, the silicon oxide film 5 and the polycrystalline silicon film are selectively removed by the photolithography technique to form the gate electrode 4.

Then, using the gate electrode 4 as a diffusion mask in the region where the surface of the semiconductor substrate 1 is exposed, ion-implantation of n-type impurities into the semiconductor substrate 1 is performed, and then heat treatment is performed to remove them. By diffusing the impurities, the n-type semiconductor region 6 serving as the source and the n-type semiconductor region 7 serving as the drain are simultaneously formed.

Next, as shown in FIG. 2, after the silicon oxide film 5 is formed on the side wall of the gate electrode 4, the surface of the semiconductor substrate 1 including the n-type semiconductor regions 6 and 7 is exposed. A MOSFET is manufactured by ion-implanting an n-type impurity and diffusing it to simultaneously form an n-type semiconductor region 8 serving as a source and an n-type semiconductor region 9 serving as a drain.

In FIG. 2, n-channel MOSFE is used.
Although T is shown, a p-channel MOSFET is also formed in a region (not shown) of the semiconductor substrate 1, and these MOSFETs are used to form a CMOS structure.

Next, as shown in FIG. 3, the source n
After the contact electrodes 10 and 11 are formed in the n-type semiconductor region 8 and the n-type semiconductor region 9 serving as the drain,
The insulating film 12 is formed so as to cover the upper portion of the FET.

The insulating film 12 is, for example, a silicon oxide film formed by a CVD method, a PSG (Phospho Silicate Glass) film which is a silicon oxide film containing phosphorus, or a silicon oxide film B containing boron and phosphorus.
It is a single-layer film made of a PSG (Boro Phospho Silicate Glass) film or a laminated film in which these are deposited.

After the insulating film 12 is formed, if necessary, a flattening process can be performed to flatten the surface of the insulating film 12.

The above-mentioned flattening treatment is performed by reflowing the PSG film or the BPSG film containing a high concentration of phosphorus (P) by heat treatment at a high temperature. Note that as the planarization treatment, a mode in which the surface of the insulating film 12 is planarized by an etch back method or a chemical mechanical polishing (CMP) method can also be adopted.

Next, as shown in FIG. 4, a step of forming a MOSFET having a TFT structure on the field insulating film 2 is performed.

That is, the polycrystalline silicon film 13 having a film thickness of, for example, 300 Å is formed by the CVD method. The polycrystalline silicon film 13 is a semiconductor region serving as an active region and may be an amorphous silicon film. C
The conditions of the VD method are, for example, SiH ₄ is used as a reaction gas, and the temperature condition is, for example, 510 ° C.

Next, a silicon oxide film 14 having a film thickness of, for example, 30 Å is formed on the surface of the polycrystalline silicon film 13 by a thermal oxidation method (for example, a dry oxygen atmosphere at 800 ° C.). The silicon oxide film 14 serves as a protective film at the time of ion implantation described below.

Next, for example, arsenic is ion-implanted through the silicon oxide film 14 into the polycrystalline silicon film 13 by an ion implantation method to form an n-type polycrystalline silicon film 13.
The ion implantation amount of arsenic is, for example, 1.0 × 10 ¹² ions / c
m ²

Next, a photoresist film is formed on the surface of the silicon oxide film 14, and the unnecessary silicon oxide film 14 and the polycrystalline silicon film 13 are removed by photoetching by using a photolithography technique, and then shown in FIG. As described above, the pattern of the active region of the MOSFET having the TFT structure is formed.

Next, after removing the unnecessary photoresist film, an operation of removing the silicon oxide film 14 on the polycrystalline silicon film 13 is performed.

Next, as shown in FIG. 5, after a silicon oxide film having a film thickness of 200 Å is formed by, for example, a CVD method, a silicon nitride film having a film thickness of 100 Å is formed by, for example, a CVD method, and the silicon oxide film and the silicon nitride film are formed. A gate insulating film 15 composed of a film is formed.

Next, a conductive polycrystalline silicon film to be the gate electrode 16 is formed on the surface of the gate insulating film 15 by the CVD method, and then the polycrystalline silicon film and the gate insulating film thereunder are formed by using the photolithography technique. The unnecessary region of 15 is selectively removed to form the patterned gate electrode 16 and gate insulating film 15.

Next, as shown in FIG. 6, the gate electrode 16
Using as a diffusion mask, the polycrystalline silicon film 13
BF ₂ which becomes a p-type impurity is ion-implanted into the region where the surface is exposed by, for example, an ion implantation method so as to have a concentration of 2 × 10 ¹⁴ pieces / cm ² , and the p-type source semiconductor region 17 is formed. And the p-type drain semiconductor region 18 are simultaneously formed. Since the gate electrode 16 is used as a mask when forming the p-type semiconductor region 17 for source and the p-type semiconductor region 18 for drain, a photolithography process is newly used as a mask. Is unnecessary, the process can be shortened.

Next, as shown in FIG. 7, after the interlayer insulating film 19 is formed on the semiconductor substrate 1, the surface of the interlayer insulating film 19 is planarized if necessary to have a flat surface. An interlayer insulating film 19 is formed, and then a polycrystalline silicon film 20 having a film thickness of 700Å is formed by, for example, a CVD method.

Next, a silicon oxide film (not shown) having a film thickness of, for example, 30 Å is formed on the surface of the polycrystalline silicon film 20 by a thermal oxidation method (for example, a dry oxygen atmosphere at 800 ° C.). . The silicon oxide film serves as a protective film at the time of ion implantation as described below.

Next, for example, BF ₄ is ion-implanted by an ion implantation method through the polycrystalline silicon film 20 through the silicon oxide film to form the p-type polycrystalline silicon film 20. B
The ion implantation amount of F ₄ is 7.5 × 10 ¹⁴ ions / cm ² .

Next, as shown in FIGS. 8 and 9, a photoresist film is formed on the surface of the silicon oxide film on the polycrystalline silicon film 20, and the unnecessary silicon oxide film and the unnecessary silicon oxide film are formed by using the photolithography technique. Polycrystalline silicon film 20
Is removed by photoetching, and a pattern is formed as a capacitance plate 20a to be one electrode of the capacitor. In this case, the capacitor plate 20a is characterized in that a hole 21 for ion implantation for forming a drain having an offset structure is provided in a later step.

The above-mentioned capacitance plate 20a is an electric wiring layer and also has a function such as a wiring layer for a power source (Vcc).
It can be used as an electric wiring layer of various modes such as an electric wiring layer that also serves as a and a Vcc wiring layer.

Next, using the capacitance plate 20a as a mask, an n-type impurity such as arsenic is ion-implanted into the p-type drain semiconductor region 18 thereunder through the hole 21 formed in the capacitance plate 20a by ion implantation. Implantation is performed to form the neutral semiconductor region 22 of the offset structure. The arsenic ion implantation amount is, for example, 1.0 × 10.
¹² pieces / cm ² .

When the semiconductor region 22 having the offset structure is formed by the ion implantation method, impurity ions such as arsenic are ion-implanted in an oblique direction from upper right to lower left in FIG. , Gate electrode 16 and gate insulating film 1
The semiconductor region 22 can be formed so as to penetrate into the region of the polycrystalline silicon film 13 underneath 5.

That is, even if a positional deviation phenomenon in manufacturing occurs, such as when the holes 21 in the capacitance plate 20a are formed by using the photolithography technique and the holes 21 are deviated from the design dimension or a predetermined arrangement pattern, this inclination is caused. By using the implanter, the semiconductor region 22 having a predetermined offset structure can be formed. Further, due to the above-mentioned positional displacement phenomenon, when the normal vertical ion implantation method is adopted, the semiconductor region 22 having the offset structure is formed.
There may be a case where a part of the p-type drain semiconductor region 18 remains on the left side of, but this can be prevented by adopting the inclined implantation.

Further, in this embodiment, the gate insulating film 15 and the gate electrode 16 are arranged on the polycrystalline silicon film 13 which is the active region, but the gate electrode 16 is formed in advance and Gate insulating film 1 on top
5 is formed and a polycrystalline silicon film 13 which is an active region is arranged on the polycrystalline silicon film 13 to form a dielectric film on the polycrystalline silicon film 13, Capacitance plate 20a through the membrane
And using the capacitance plate 20a as a mask to ion-implant conductive impurities into the drain semiconductor region 18 formed on the right side of the polycrystalline silicon film 13 through the hole 21 formed in the capacitance plate 20a. The semiconductor region 22 having an offset structure can be formed.

Further, in forming the semiconductor region 22, the capacitance plate 20a is used as a mask for ion implantation for forming the offset structure, and a photoresist film or the like is newly used as a mask for the ion implantation. Since the forming process and the photolithography process are unnecessary, the manufacturing process can be simplified.

That is, according to the first embodiment described above,
Source semiconductor region 17 and drain semiconductor region 1
The polycrystalline silicon film 13 which is a semiconductor region for forming 8 is previously formed as a semiconductor region as a TFT, and the gate insulating film 15 and the gate electrode 16 are formed in the selective region of the polycrystalline silicon film 13. Due to the structure that can be formed, the gate electrode 1
6 is used as a mask to form a source semiconductor region 17 in the polycrystalline silicon film 13 on one side of the gate electrode 16 and a drain semiconductor region 18 in the polycrystalline silicon film 13 on the other side of the gate electrode 16. It can be formed in a consistent manner.

The capacity plate 20 provided on the gate electrode 16 and the drain semiconductor region 18 and also on the surface of the interlayer insulating film 19 also serving as an electric wiring layer.
By including a, the capacitor plate 20a is used as a mask to form the semiconductor region 22 of the offset structure, and impurities are ion-implanted through the holes 21 in the capacitor plate 20a to form the drain semiconductor region 18
Since it can be performed by implanting ions into the substrate, it is possible to use the capacitance plate 20a which also serves as an electric wiring layer as a mask in the ion implantation method when forming the semiconductor region 22 of the offset structure.

Therefore, the photolithography step for forming the source semiconductor region 17 and the drain semiconductor region 18, and the semiconductor region 2 having the offset structure.
Since it is possible to reduce the photolithography process for forming 2, the formation of a photoresist film as a mask for selectively ion-implanting conductive impurities for forming them, the exposure process, the development process, and Since the bake process and the like are unnecessary and the mask used for them is unnecessary, the source semiconductor region 17 and the drain semiconductor region 18 can be manufactured in a self-aligned manner by using the gate electrode 16. A semiconductor integrated circuit device can be manufactured by reducing the number of steps such as reducing the photolithography step.

Further, since the semiconductor integrated circuit device can be manufactured by reducing the number of steps such as the photolithography step, the mask used in the photolithography step is not required, so that the mask fabrication can be reduced. Therefore, the manufacturing cost can be reduced. Further, since the number of selective etching steps performed by forming a photoresist film in the photolithography step and wet etching or dry etching using the photoresist film can be reduced, foreign matters or inconveniently generated accidentally in the photolithography step can be reduced. Since processing and the like are eliminated, a semiconductor integrated circuit device having excellent element characteristics can be manufactured.

Further, since the capacitance plate 20a is used as a mask for ion implantation, when the semiconductor region 22 having the offset structure is formed, the position of the hole 21 and the position of the semiconductor region 22 in the capacitance plate 20a are mutually different. By doing so in a state corresponding to the above, even in a fine region in the MOSFET arranged by a fine dimension, the hole 21 of the capacitance plate 20a arranged in a region different from the region and also serving as an electric wiring layer is formed. The precision can be improved by using the method, and the semiconductor region 22 having the offset structure can be formed at a predetermined position by fine processing.

Next, as shown in FIG. 10, for example, a silicon oxide film having a film thickness of, for example, 100 Å is formed on the semiconductor substrate 1 by the CVD method, and then the film thickness is, for example, 100 Å by the CVD method. After forming a silicon nitride film and forming an interlayer insulating film 23 that also serves as a dielectric film of a capacitor made of a silicon oxide film and a silicon nitride film, a planarization process is performed as necessary to perform interlayer insulation having a flat surface. The film 23 is formed.

Next, a polycrystalline silicon film having a film thickness of, for example, 700 Å is formed on the interlayer insulating film 23 by the CVD method or the like, and thereafter, an oxide film having a film thickness of, for example, 30 Å is formed on the surface of the polycrystalline silicon film. Silicon film (not shown)
Are formed by a thermal oxidation method (for example, a dry oxygen atmosphere at 800 ° C.). The silicon oxide film serves as a protective film at the time of ion implantation as described below.

Next, for example, BF ₄ is ion-implanted by an ion implantation method through the polycrystalline silicon film through a silicon oxide film to form a p-type polycrystalline silicon film. BF ₄
The ion implantation amount of is, for example, 7.5 × 10 ¹⁴ ions / cm ²
And

Next, a photoresist film is formed on the surface of the silicon oxide film on the p-type polycrystalline silicon film, and the unnecessary silicon oxide film and the polycrystalline silicon film are photoetched by using the photolithography technique. Then, a pattern is formed as a capacitance plate 24a which becomes the other electrode of the capacitor.

The capacitor plate 2 in the capacitor
The interlayer insulating film 19 formed under 4a can be used as a dielectric film in the capacitor. In this case, as the interlayer insulating film 19, a silicon oxide film having a film thickness of, for example, 100 Å is formed by the CVD method, and then a silicon nitride film having a film thickness of, for example, 100 Å is formed by the CVD method. An interlayer insulating film 19 made of a film and a silicon nitride film is formed. The interlayer insulating film 23 formed on the capacitance plate 20a and the capacitance plate 24a thereon can be omitted if necessary.

In the first embodiment described above, a capacitor having the capacitance plates 20a and 24a as one electrode is
It is possible to easily form a structure in which the memory cells are arranged on the MOSFETs. As a result, the radiation such as α-rays entering from the outside can be stopped by the capacitor, so that the soft error resistance of the memory cell arranged under the capacitor can be improved, and the MOSFET can be used as a constituent element. There is S
The reliability and electrical characteristics of a semiconductor integrated circuit device such as a RAM can be improved, and it can be manufactured by a simple manufacturing process.

As another mode of the first embodiment described above, a capacitor having the capacitance plates 20a and 24a as one electrode is used as one component of the memory cell, and the capacitor and the MOSFET are electrically connected. As a result, a semiconductor integrated circuit device such as a DRAM (Dynamic Random Access Memory) can be manufactured by a simple manufacturing process.

In this case, the direction of the spontaneous polarization generated in the interlayer insulating film 23 (or the interlayer insulating film 19) as the dielectric film is changed by the direction of the voltage applied to the two electrodes including the capacitance plates 20a and 24a in the capacitor. Can store information of "1" and "0". The direction of spontaneous polarization generated in the dielectric film is determined by the capacitance plates 20a and 24a.
Information can be stored in a non-volatile manner because it remains even if the voltage applied to is removed.

(Embodiment 2) As shown in FIG. 11, a semiconductor integrated circuit device and a method of manufacturing the same according to another embodiment of the present invention include a source semiconductor region of a TFT structure and a drain semiconductor region of an offset structure. It is characterized by adopting an inclined implanter.

That is, as shown in FIG. 11, the gate insulating film 15 and the gate electrode 16 are formed in the patterned active region in the selective region on the polycrystalline silicon film 13.

Next, using the gate electrode 16 as a diffusion mask, for example, a p-type impurity is formed in a region where the surface of the polycrystalline silicon film 13 is exposed by an ion implantation method using a tilted implantation. BF ₂ 25 2 x 10 ¹⁴
Ions are ion-implanted so as to have a concentration of pcs / cm ² to simultaneously form the p-type semiconductor region 17 for source and the p-type semiconductor region 18 for drain.

When the p-type source semiconductor region 17 and the p-type drain semiconductor region 18 are formed, since the gate electrode 16 is used as a mask, the photoresist film is newly used as a mask. Since the photolithography process is unnecessary, the manufacturing process can be shortened.

Further, when forming the pattern as the capacitance plate 20a which becomes one electrode of the capacitor in the above-described first embodiment, the hole 21 for ion implantation to serve as the drain of the offset structure is formed in the capacitance plate 20a.
Therefore, the manufacturing process can be shortened from this point as well.

Further, when the drain semiconductor region 18 of the offset structure is formed by the ion implantation method, BF
_Since the ion implantation of 225 is performed in the oblique direction from the upper left to the lower right in FIG. 11 and the structure in which the gate electrode 16 is protruded, the gate electrode 16 is affected by the inclined implanter. 1
A predetermined region on the right side of 6 is a shaded region, and a region where ions are not implanted can be provided in that region. Therefore, a region of the polycrystalline silicon film 13 on the right side of the gate electrode 16 and the insulating film 15 corresponding to the tilt angle of the tilted implanter is not used as an offset region with an offset length corresponding to the tilt angle of the tilted implanter. It can be a semiconductor region.

Furthermore, when the drain semiconductor region 18 having the offset structure is formed by the ion implantation method,
By adopting a tilted implanter in which BF ₂ 25 is ion-implanted in an oblique direction from the upper left to the lower right in FIG. 11, a region of the polycrystalline silicon film 13 below the gate electrode 16 and the gate insulating film 15 is formed. The contacted shape can be used as a semiconductor region as an offset region. By adopting this inclined implanter, in forming the holes 21 in the capacitance plate 20a in the above-described first embodiment by using the photolithography technique, it is possible to avoid manufacturing deviations from the design dimensions or a predetermined layout pattern. Even if the displacement phenomenon occurs, the drain semiconductor region 18 having a predetermined offset structure can be formed regardless of the displacement phenomenon.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned Embodiments 1 and 2, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, in the first and second embodiments, the case where the semiconductor substrate is a semiconductor integrated circuit device manufactured as a starting material has been described, but the present invention is not limited to this, and as another aspect, silicon oxide is used. Alternatively, an insulating substrate made of alumina or the like is used as a starting material, a semiconductor region to be an active region such as a polycrystalline silicon film is formed thereon, and a semiconductor element such as MOSFET is formed in the semiconductor region.
The present invention can be applied to a semiconductor integrated circuit device having a licon on insulator structure and a manufacturing method thereof.

[0072]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

According to the semiconductor integrated circuit device of the present invention, the first semiconductor region for forming the source semiconductor region and the drain semiconductor region is previously formed as the semiconductor region as the TFT, and the first semiconductor region is formed. Since the gate insulating film and the gate electrode can be formed in the selective region of the semiconductor region, the first semiconductor region on one side of the gate electrode by the ion implantation method using the gate electrode as a mask. The source semiconductor region and the drain semiconductor region can be formed in the first semiconductor region on the other side of the gate electrode in a self-aligned manner.

Further, an electric wiring layer having a hole corresponding to the second semiconductor region on the second semiconductor region, which is provided on the gate electrode and the semiconductor region for the drain and arranged on the surface of the insulating film. Since the electric wiring layer is provided, the electric wiring layer is used as a mask to form the second semiconductor region having the offset structure, and impurities are ion-implanted into the drain semiconductor region through the holes in the electric wiring layer by the ion implantation method. Because it can be done by driving in,
The electric wiring layer can be used as a mask in the ion implantation method when forming the second semiconductor region of the offset structure.

Therefore, the photolithography process for forming the source semiconductor region and the drain semiconductor region and the photolithography process for forming the second semiconductor region having the offset structure can be omitted, so that they are formed. Since the formation of a photoresist film as a mask for selectively ion-implanting conductive impurities for exposure, the exposure process, the development process, and the baking process are not necessary and the mask used for them is not necessary, The semiconductor region and the semiconductor region for drain can be manufactured in a self-aligned manner by using the gate electrode, and the semiconductor integrated circuit device can be manufactured by reducing the number of steps such as reducing the photolithography step. .

Further, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, a step of forming a source semiconductor region and a drain semiconductor region by ion-implanting conductive impurities into the semiconductor region using the gate electrode as a mask. By using the electric wiring layer formed on the drain semiconductor region as a mask, ions of impurities having a conductivity type opposite to that of the drain semiconductor region are ion-implanted into the drain semiconductor region through a hole provided in a part of the electric wiring layer. And forming a semiconductor region having an offset structure by using the gate electrode as a mask, the source semiconductor region and the drain semiconductor region can be formed in a self-aligned manner, and the drain semiconductor region has an offset structure. Can be formed by ion-implanting conductive impurities through holes provided in the electric wiring layer. Thus, the number of steps such as the photolithography step can be reduced, and the source semiconductor region and the drain semiconductor region can be manufactured in a self-aligned manner by using the gate electrode, and the semiconductor integrated circuit device can be easily manufactured. It can be manufactured at low cost using manufacturing technology.

Further, according to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, a part of the electric wiring layer can be used as a capacitance plate which is one electrode of the capacitor, and the capacitance plate can prevent soft error. An SRAM can be manufactured as Furthermore, since the capacitance plate can be used as a mask for ion implantation to form the drain semiconductor region of the offset structure,
Since the offset structure and the MOSFET having the offset structure can be manufactured by microfabrication, in addition to the fact that the shape of the hole formed in a part of the capacitance plate can be defined by the shape of the micropattern, the capacitor,
The MOSFET having the offset structure and the semiconductor integrated circuit device having the MOSFET can be manufactured in a self-aligned manner by adopting a simple manufacturing process. Further, as a result of fine processing being possible in a small number of steps in forming a semiconductor region having an offset structure, a semiconductor integrated circuit device can be manufactured in a highly integrated state in a small area.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 8 is a plan view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

[Explanation of symbols]

1 semiconductor substrate 2 field insulating film 3 gate insulating film 4 gate electrode 5 silicon oxide film 6 semiconductor region 7 semiconductor region 8 semiconductor region 9 semiconductor region 10 contact electrode 11 contact electrode 12 insulating film 13 polycrystalline silicon film 14 silicon oxide film 15 gate Insulating film 16 Gate electrode 17 Semiconductor region for source 18 Semiconductor region for drain 19 Interlayer insulating film 20 Polycrystalline silicon film 20a Capacitance plate 21 Hole 22 Semiconductor region 23 Interlayer insulating film 24a Capacitance plate 25 BF ₂

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Eri Fujita 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hiritsu Cho-LS Engineering Co., Ltd. (72) Inventor Yasuko Yoshida Kodaira, Tokyo 5-20-1 Joumizuhonmachi, Ichi, Ltd. Within the Semiconductor Business Division, Hitachi, Ltd. (72) Inventor Keiichi Yoshizumi 5-20-1 Jomizuhoncho, Kodaira-shi, Tokyo Within the Semiconductor Division, Hitachi Ltd. (72) Invention Yutaka Hoshino 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (72) Inventor Naotaka Hashimoto 5-20-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor In-house (72) Inventor Kazushi Fukuda 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Division (72) Who Asayama TadashiIchiro Tokyo Kodaira Josuihon-cho 5-chome No. 20 No. 1 Co., Ltd. Hitachi semiconductor business unit

Claims (9)

[Claims] 1. A semiconductor region for a source and a semiconductor region for a drain, a gate electrode and a gate insulating film, and between the drain semiconductor region and the first semiconductor region below the gate electrode and the gate insulating film. MOSF having an offset structure second semiconductor region provided
ET and an electric wiring layer having a hole corresponding to the second semiconductor region above the second semiconductor region, the insulating film being provided on the gate electrode and the drain semiconductor region. A semiconductor integrated circuit device, comprising: an electric wiring layer disposed on a surface thereof. 2. A semiconductor region for source and a semiconductor region for drain, a gate electrode and a gate insulating film, and a semiconductor region for drain and a first semiconductor region on the gate electrode and the gate insulating film. MOSF having an offset structure second semiconductor region provided
ET and an electric wiring layer having a hole corresponding to the second semiconductor region on the second semiconductor region, the electric wiring layer being provided on the first semiconductor region and the drain semiconductor region. A semiconductor integrated circuit device comprising: an electric wiring layer disposed on a surface of an insulating film. 3. A semiconductor region for source and a semiconductor region for drain, a gate electrode and a gate insulating film, and between the semiconductor region for drain and the first semiconductor region below the gate electrode and the gate insulating film. A second semiconductor region of the offset structure, wherein the first semiconductor region extends and is provided
A semiconductor region, and an electric wiring layer arranged on the surface of an insulating film provided on the second semiconductor region, the gate electrode and the drain semiconductor region. A semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein the electric wiring layer is used as a capacitance plate which is one electrode of a capacitor. 5. The MOSFET has a TFT structure, the electric wiring layer is used as a capacitance plate which is one electrode of a capacitor, and the MOSFET and the capacitance plate are used as a part of SRAM. Claims 1 and 2, characterized in that
3. The semiconductor integrated circuit device according to 3 or 4. 6. A step of forming a semiconductor region on a surface of an insulating film on a semiconductor substrate, a step of forming a gate electrode on a part of the surface of the semiconductor region via a gate insulating film, the gate electrode Forming a semiconductor region for a source and a semiconductor region for a drain by ion-implanting a conductive impurity into the semiconductor region by using a mask; and on the semiconductor region in which the gate electrode and the semiconductor region for a drain are formed. Forming an electric wiring layer through an insulating film and forming a hole in a part of the electric wiring layer; and using the electric wiring layer as a mask, through a hole provided in a part of the electric wiring layer. Forming a semiconductor region having an offset structure by ion-implanting an impurity having a conductivity type opposite to that of the drain semiconductor region into the drain semiconductor region. The method of manufacturing a semiconductor integrated circuit device according to claim. 7. A step of forming a gate electrode on a part of a surface of an insulating film on a semiconductor substrate via a gate insulating film, and forming a semiconductor region on the insulating film including the gate electrode. A step of ion-implanting a conductive impurity into a part of the semiconductor region to form a semiconductor region for a source and a semiconductor region for a drain, and forming an electric wiring layer on the semiconductor region via an insulating film Together with the step of forming a hole in a part of the electric wiring layer, and using the electric wiring layer as a mask, through the hole provided in a part of the electric wiring layer, the conductivity type opposite to the drain semiconductor region. A step of forming a semiconductor region having an offset structure by ion-implanting the impurities into the drain semiconductor region. 8. In the step of forming the semiconductor region of the offset structure, the conductivity type opposite to that of the drain semiconductor region is provided through a hole provided in a part of the electrical wiring layer by using the electrical wiring layer as a mask. When ion-implanting the impurities into the semiconductor region for drain, an inclined implanter is used in a direction in which the semiconductor region for drain is ion-implanted into the semiconductor region under the gate insulating film. A method for manufacturing a semiconductor integrated circuit device according to claim 6. 9. A step of forming a semiconductor region on the surface of an insulating film on a semiconductor substrate; a step of forming a gate electrode on a part of the surface of the semiconductor region via a gate insulating film; Using a tilted implanter in a direction in which the semiconductor region under the gate insulating film is ion-implanted from above a region forming a semiconductor region for a source,
Forming a source semiconductor region and an offset structure drain semiconductor region by ion-implanting an impurity of a conductivity type opposite to that of the semiconductor region into the semiconductor region using the gate electrode as a mask. Manufacturing method of semiconductor integrated circuit device.