KR100252872B1 - Method for forming contact line of semiconductor device - Google Patents

Abstract

PURPOSE: A method of forming a contact wiring for a semiconductor device is provided to form a stable contact wiring in case of a great contact aspect ratio by forming contact pads on a region for forming a wiring layer. CONSTITUTION: First, an isolation oxide is formed on a first conductive semiconductor substrate. Then, second conductive wells(22) are formed on the substrate. Next, a gate electrode formed of a gate oxide, a conductive layer and a gate cap oxide is formed on the substrate and wells. Then, sidewall spacers are formed on both sides of the gate electrode. Next, a semiconductor layer is formed between the isolation oxides(39). Then, second contact pads(36,38) are formed on the semiconductor layer on the substrate by implanting second conductive ions, and second conductive impurity areas(31a,31b) are formed in the second conductive wells under the contact pad. Finally, a wiring layer for connecting the first and second conductive contact pads is formed.

Description

Contact wiring formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the contact wiring of a semiconductor device. In particular, when the aspect ratio is very large, a stable contact wiring is formed by forming pads for contact not only in the cell region but also in the core or the peripheral region. The contact wiring forming method of the semiconductor element which can be made.

As a result of efforts to reduce the size of the MOSFET constituting the integrated circuit in order to obtain good circuit operation performance and high integration in the semiconductor integrated circuit, the technology of the semiconductor integrated circuit has been scaled down to less than micron. Therefore, in the MOSFET, the gate line width is narrowed, and in the MOSFET, the short channel effect is one of the characteristics of the MOSFET as the size of a single device decreases as integration is repeated. In order to solve the problem of hot carriers, the LDD (Lightly Doped Drain) structure is applied to the MOSFET to solve such problems, and to reduce the signal transmission speed caused by the increase in wiring resistance due to the increase in integration. In order to solve this problem, various researches and developments have been made by employing a gate structure using polysides. In addition, after the impurity regions to be used as sources / drains are formed on both side semiconductor substrates of the gate electrodes, the wiring process is performed after the ILD (Inter Layer Dielectric) process including a planarization process on the entire surface of the substrate including the gate electrodes. The contact hole is formed by selectively removing the ILD layer formed on the upper side of the circuit. The contact wiring process also increases the aspect ratio due to the miniaturization of the semiconductor device, thereby securing the margin of the bit line or the memory contact portion. There is a difficulty, and research to solve this problem is being actively conducted.

Such MOSFETs include p channel MOS, n channel MOS, and CMOS. Initially, MOS devices mainly used pMOS devices, which are relatively easy to control in power consumption and integrated circuit manufacturing. However, as the speed of the devices becomes important, the mobility of the carriers increases the mobility of holes. NMOS devices that use electrons that have mobility about 2.5 times faster than. In addition, CMOS devices are lower than pMOS and nMOS devices in terms of integrated density and complicated manufacturing processes, but have very low power consumption.

Currently, the memory cell part of the device uses NMOS and the peripheral circuit part uses CMOS.

Such a contact wiring forming method of a conventional semiconductor device will be described with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a process for forming contact wirings of a conventional semiconductor device.

The contact wiring of the conventional semiconductor device has shown that a pad for contact is formed only in a cell region among a cell region (left side of the figure) and a core and a ferry (peripheral) region (right side of the figure).

First, as shown in FIG. 1A, a field oxide film 2 is formed in a predetermined region of a p-type semiconductor substrate 1 to define an active region and a field region, and then the p-type semiconductor substrate. The n-type well 3 is formed in the predetermined region of (1). Subsequently, the gate oxide film 4, the polysilicon layer, and the cap oxide film 6 are sequentially formed on the entire surface of the semiconductor substrate 1, and then selectively patterned (photolithography process + etching process) to form a gate electrode 5 having a predetermined interval. ). Then, n-type low concentration impurity ions are implanted into the p-type semiconductor substrate 1 on both sides of the gate electrode 5 to form an n-type LDD region 7, and then the sidewall spacers 8 are formed on the side of the gate electrode 5. Then, the source / drain regions 9 are formed by implanting n-type high concentration impurity ions into the p-type semiconductor substrate 1 by an ion implantation process using the gate electrode 5 and the sidewall spacers 8 as masks. At this time, in the n-type well 3 region, an LDD region 7 and a source / drain region 9 which are opposite to the n-type well 3 are formed by a p-type low concentration and high concentration impurity ion implantation process. That is, the cell region is formed of NMOS, and the core and ferry regions are formed of CMOS. Subsequently, a thin third oxide film 10 is deposited on the entire surface, and then an interlayer insulating film 11 is formed by chemical vapor deposition (CVD). Then, the photoresist film 12 is applied to the entire surface and selectively patterned so that the interlayer insulating film 11 on the source / drain region 9 above the cell region (left side of the drawing) is exposed by the exposure and development processes.

As shown in FIG. 1B, the source / drain region 9 is anisotropically etched by the interlayer insulating layer 11 and the third oxide layer 10 of the cell region by an etching process using the patterned photosensitive layer 12 as a mask. The exposed node contact hole 13 and the bit line contact hole 14 are formed. Then, the photosensitive film 12 is removed.

As shown in FIG. 1C, a polysilicon layer is formed on the entire surface of the interlayer insulating film 11 including the node contact hole 13 and the bit line contact hole 14 of the cell region, and the interlayer insulating film 11 of the core and ferry regions. (15) is formed. Subsequently, after the photosensitive film 16 is applied to the entire surface, the node contact hole 13 and the bit line contact hole 14, the node contact hole 13 and the bit line contact hole 14 in the cell region are exposed and developed. The photosensitive film 16 is selectively patterned so as to remain only on the polysilicon layer 15 adjacent to the?

As shown in FIG. 1D, the polysilicon layer 15 of the cell region is anisotropically etched by using the patterned photoresist 16 as a mask to etch the node contact pad 15a and the bit line contact pad 15b in the cell region. ). At this time, the polysilicon layer 15 of the core and ferrite regions is removed.

As shown in FIG. 1E, a contact hole 17 is formed by selectively removing the third oxide film 10 and the interlayer insulating film 11 above the source / drain regions 9 formed in the core and ferry regions. Subsequently, an aluminum layer 18 contacting the source / drain regions 9 is formed on the entire surface of the interlayer insulating layer 11 of the core and ferry regions including the contact holes 17, and then selectively patterned (photolithography process + etching). Step) to complete the wiring forming step of the conventional semiconductor element. In this case, although not shown in the drawing, a process for forming a capacitor is performed in the node contact pad 15a in the cell region, and a bit line wiring layer forming process is performed in the bit line contact pad 15b.

The conventional method for forming contact wiring of a semiconductor device has the following problems.

First, there are deep contact holes for wiring with aluminum in the core and ferry areas, making the contact hole formation process difficult, and in severe cases, contact holes are not formed completely. The possibility of alignment is low, which lowers the reliability of the contact wiring process.

Second, in the process of forming a wiring layer by forming a conductive layer such as aluminum in the contact hole, the space between pads is small, making it difficult to form a stable contact wiring.

The present invention has been made to solve the problems of the conventional method of forming the contact wiring of the semiconductor device as described above. Since the contact pad is formed in the area where the wiring layer is to be formed, the semiconductor is suitable for forming stable contact wiring when the contact aspect ratio is large. It is an object of the present invention to provide a method for forming contact wiring of a device.

1A to 1E are cross-sectional views illustrating a process of forming contact wirings in a conventional semiconductor device.

2A through 2L are cross-sectional views illustrating a process of forming contact wirings in a semiconductor device of the present invention.

Explanation of symbols for the main parts of the drawings

20: first conductive semiconductor substrate 21: field oxide film

22 second conductivity type well 23 gate insulating film

24 gate electrode 25 gate cap insulating film

26 sidewall spacer 27 undoped polysilicon layer

28, 29, 32, 35, 37: photosensitive film 30, 36, 38: 2nd conductivity type contact pad

31a, 31b, 31c: second conductivity type impurity region

33: first conductivity type contact pad

34: first conductivity type impurity region 39: insulating film

40: contact hole 41: metal contact wiring layer

A method of forming a contact wiring of a semiconductor device according to the present invention includes the steps of forming an insulating insulating film in a predetermined region of a first conductive semiconductor substrate divided into a cell region and a core and a ferry region, and the predetermined semiconductor substrate in the core and ferry regions. Forming a second conductive well in a region, forming a gate electrode comprising a gate insulating film, a conductive layer and a gate cap insulating film on a predetermined region of the first conductive semiconductor substrate and the second conductive well; Forming a sidewall spacer on both sides of the gate electrode, forming a semiconductor layer on the first conductive semiconductor substrate and the second conductive well between the isolation insulating film, and on the upper surface of the first conductive semiconductor substrate. The second conductive type impurity ions are implanted into the semiconductor layer and heat treated to form a second conductive type contact pad. Forming a second conductivity type impurity region in the first conductivity type semiconductor substrate below the tack pad, and implanting and heat treating a first conductivity type impurity ion into the impurity layer above the second conductivity type well to form a first conductivity type Forming a type contact pad and simultaneously forming a first conductivity type impurity region in the second conductivity type well under the first conductivity type contact pad, and electrically connecting the first and second conductivity type contact pads Forming a wiring layer as much as possible.

Such a method for forming contact wiring of the semiconductor device according to the present invention will be described with reference to the accompanying drawings.

2A to 2L are cross-sectional views illustrating a process of forming contact wirings in a semiconductor device of the present invention.

In the method for forming contact wiring of the semiconductor device of the present invention, the process cross section (left diagram) of the cell region and the process cross section (right diagram) of the core and ferry regions will be described simultaneously.

First, as shown in FIG. 2A, a selective ion implantation process and localization using a local oxide of silicon (LOCOS) mask (not shown) in a predetermined region of the first conductive semiconductor substrate 20 is performed. In the process, the field oxide layer 21 is formed to define an active region and a field region. Subsequently, a second conductivity type well 22 is formed in a predetermined region of the first conductivity type semiconductor substrate 20 defined by core and ferry regions. Next, a gate insulating film 23, a polysilicon layer, and a gate cap insulating film 25 are sequentially formed on the entire surface of the semiconductor substrate 20, and then selectively patterned (photolithography process + etching process) to form a gate electrode having a predetermined interval ( 24). Next, sidewall spacers 26 are formed on side surfaces of the gate cap insulating layer 25, the gate electrode 24, and the gate insulating layer 23. Subsequently, an undoped polysilicon layer 27 is formed on the entire surface of the substrate including the gate electrode 24. In this case, the gate insulating film 23, the gate cap insulating film 25, and the sidewall spacers 26 may be formed of any one of an oxide film and a nitride film. In particular, the gate cap insulating film 25 is formed by chemical vapor deposition (CVD), is formed to a thickness of about 3000 to 5000 kPa thicker than a general gate cap insulating film, and the undoped polysilicon layer 27 is 1000 to It is formed to a thickness of 4000Å. In addition, the first conductive semiconductor under the side surface of the gate electrode 24 formed above the first conductive semiconductor substrate 20 and the second conductive well 22 before the process of forming the sidewall spacers 26. Lightly doped drain (LDD) regions may be formed by performing an ion implantation process and a heat treatment process to form low concentration impurity regions of opposite conductivity types in the substrate 20 and the second conductive well 22, respectively.

As shown in FIG. 2B, the undoped polysilicon layer 27 and the gate cap insulating layer 25 are polished and placed only on both sides of the gate electrode 24. In this case, the polishing method is a chemical mechanical polishing (CMP) method to finish the polishing process before the upper surface of the gate electrode 24 is exposed. That is, since the undoped polysilicon layer 27 and the gate cap insulating film 25 are polished to the same height, the flatness is excellent.

As shown in FIG. 2C, the first photosensitive film 28 is applied to the entire surface of the substrate including the undoped polysilicon layer 27, which is polished and positioned only between the gate electrodes 24, and then, as shown in FIG. The first photosensitive film 28 is patterned so as to remain only above the active region in an exposure and development process using (not shown). Subsequently, an isolation region (field oxide layer 21) except for the undoped polysilicon layer 27 on the upper side of the semiconductor substrate 20 defined as the active region is formed by an etching process using the patterned first photoresist layer 28 as a mask. The undoped polysilicon layer 27 formed on the upper side is removed. That is, the undoped polysilicon layer 27 formed on the upper side of the field oxide film 21 can be easily removed by the developing step after the exposure step using the LOCOS mask.

As shown in FIG. 2D, the first photosensitive film 28 is removed. Next, a second photosensitive film 29 is coated on the entire surface of the substrate including the undoped polysilicon layer 27, and then exposed to a developing process. The first conductive type of the undoped polysilicon layer 27 of the core and ferri regions may be formed. The second photoresist layer 29 is patterned such that only the undoped polysilicon layer 27 on the upper side of the semiconductor substrate 20 is exposed. Subsequently, a second conductivity type impurity ion is implanted into the undoped polysilicon layer 27 by an ion implantation process using the patterned second photosensitive layer 29 as a mask. In this case, when the first conductive semiconductor substrate 20 is formed of a p-type semiconductor substrate, n-type impurity ions (eg, arsenic (As: Arsenic) or phosphorus in the second conductive impurity ion implantation process) may be used. (P: Phosphorus) ions are implanted and p-type impurity ions (for example, boron (B) ions) are implanted when formed into an n-type semiconductor substrate. Then, arsenic (As: Arsenic) or phosphorus (P: Phosphorus) ions, which are preferably n-type impurity ions, are implanted.

As shown in Fig. 2E, the second photosensitive film 29 is removed. Subsequently, the undoped polysilicon layer 27 implanted with the second conductivity type impurity ions is heat-treated to form a second conductivity type first contact pad 30. At this time, the second conductivity type impurity ions of the second conductivity type first contact pad 30 are also diffused into the first conductivity type semiconductor substrate 20 under the second conductivity type first contact pad 30 to form the second conductivity type. The conductive first impurity region 31a is formed. At this time, the heat treatment temperature is carried out at 500 ~ 900 ℃.

As shown in FIG. 2F, a third photosensitive film 32 is coated on the entire surface of the substrate including the second conductive first contact pad 30, and then the second conductive well of the core and ferri regions is exposed and developed. (22) The third photosensitive film 32 is selectively patterned so that the upper undoped polysilicon layer 27 is exposed. Subsequently, a first conductivity type impurity ion is implanted into the undoped polysilicon layer 27 by an ion implantation process using the patterned third photoresist layer 32 as a mask. In this case, when the second conductivity type well 22 is formed as an n type, boron (B: boron) ion, which is a p type impurity ion, is implanted in the first conductivity type impurity ion implantation process and formed as a p type well. In this case, arsenic (As: Arsenic) or phosphorus (P: Phosphorus) ions, which are n-type impurity ions, are implanted. Then, boron ions which are preferably p-type impurity ions are implanted.

As shown in Fig. 2G, the third photosensitive film 32 is removed. Subsequently, the undoped polysilicon layer 27 implanted with the first conductivity type impurity ions is heat treated to form a first conductivity type contact pad 33. At this time, the first conductivity type impurity ions implanted into the undoped polysilicon layer 27 are diffused by the heat treatment process to form a first conductivity type contact pad 33 and the first conductivity type contact pad 33. The first conductivity type impurity ions are also diffused into the second conductivity type well 22 at the bottom to form a first conductivity type impurity region 34. In other words, p-type or n-type impurity ions are implanted into the undoped polysilicon layer 27 in FIGS. 2d and 2f to form a p-type or n-type doped polysilicon layer and used as a contact pad. The impurity ions of the contact pad thus formed are diffused into the semiconductor substrate or the well by annealing to form an impurity region to be used as a source / drain region.

As shown in FIG. 2H, a gate cap including an undoped polysilicon layer 27 in the cell region, a first conductive contact pad 33 and a second conductive first contact pad 30 in the core and ferry regions. The fourth photoresist layer 35 is coated on the entire surface of the insulating layer 25 and then patterned so that the undoped polysilicon layer 27 of the bit line contact forming region of the cell region is exposed through an exposure and development process. do. Next, an impurity ion of a second conductivity type is implanted into the undoped polysilicon layer 27 of the bit line forming region by an ion implantation process using the patterned fourth photoresist layer 35 as a mask.

As shown in FIG. 2I, the fourth photosensitive film 35 is removed. Subsequently, the undoped polysilicon layer 27 implanted with the second conductivity type impurity ions is heat treated to form a second conductivity type second contact pad 36. At this time, the undoped polysilicon layer 27 becomes the second conductive second contact pad 36 and the first conductive semiconductor under the second conductive second contact pad 36 by the heat treatment process. A second conductivity type second impurity region 31b is formed in the substrate 20.

As shown in FIG. 2J, the fifth photosensitive layer 37 is coated on the entire surface of the gate cap insulating layer 25 including the contact pads 30, 33, and 36. The fifth photosensitive layer 37 is patterned to expose the undoped polysilicon layer 27. Subsequently, a second conductivity type impurity ion is implanted into the undoped polysilicon layer 27 of the node contact forming region exposed by an ion implantation process using the patterned fifth photosensitive film 37 as a mask.

As shown in Fig. 2K, the fifth photosensitive film 37 is removed. Subsequently, the undoped polysilicon layer 27 implanted with the second conductivity type impurity ions is heat treated to form a second conductivity type third contact pad 38. In this case, a second conductive third impurity region 31c is formed in the first conductive semiconductor substrate 20 under the second conductive third contact pad 37 by the heat treatment process.

In this case, the process of forming the second conductive third contact pad 38 and the second conductive third impurity region 31c may be performed by using a second conductive second contact pad as shown in FIGS. 2H and 2I. 36) and the second conductivity type second impurity region 31b. That is, since the second conductive third contact pad 38 is formed to be the same conductive type as the second conductive second contact pad 36, the second conductive second contact pad 36 in FIGS. 2H and 2I. In the process of exposing and developing the fourth photoresist film 35 for forming the second photoresist film 35, the fourth photoresist film 35 in the region where the second conductive third contact pad 38 is formed is simultaneously exposed and developed. 2 During the ion implantation process for forming the contact pads 36, the second conductivity type impurity ion implantation process for the formation of the second conductivity type third contact pad 38 is simultaneously performed and heat treated to form the second conductivity type second contact. The pad 36, the second conductivity type third contact pad 38, the second conductivity type second impurity region 31b and the second conductivity type third impurity region 31c can be formed at the same time.

As shown in FIG. 2L, an insulating film 39 is formed on the field oxide layer 21 including the second conductive type first contact pad 30 and the first conductive type contact pad 33 in the core and ferry regions. After the formation, the insulating layer 39 is selectively patterned (photolithography process + etching process) to expose the upper surface of the second conductivity type first contact pad 30 and the first conductivity type contact pad 33. The contact hole 40 is formed. Next, a metal layer is formed on the insulating layer 39 including the contact hole 40 and then selectively patterned (photolithography process + etching process) to form a metal contact wiring layer 41. At this time, the metal contact wiring layer 41 is formed of a conductive metal, preferably formed of any one of aluminum or tungsten. In this case, although not shown in the figure, a process of forming a capacitor and a process for bit line wiring are performed in the cell region.

The method for manufacturing a contact wiring of the semiconductor device of the present invention as described above has the following effects.

First, since the contact pads are formed between the gate electrodes, the contact pads have a wider width and sufficient alignment margins with the contact wirings through the contact holes can be provided to enable stable contact wiring, thereby improving the reliability of the contact wiring of the semiconductor device.

Second, since the contact pads are formed up to the height of the gate electrode, the problem of the contact hole forming process, which occurs when the aspect ratio is large, can be solved to easily cope with high integration of semiconductor devices.

Third, contact pads are formed in the core and ferry regions up to the gate electrode formation height, thereby solving the problem of contact wiring, which occurs as the aspect ratio increases in the core and ferry regions, thereby providing a highly reliable semiconductor device.

Claims (6)

Forming an isolation insulating film in a cell region and a predetermined region of a first conductive semiconductor substrate divided into a core and a ferry region; Forming a second conductivity type well in the semiconductor substrate predetermined region of the core and ferry regions; Forming a gate electrode comprising a gate insulating film, a conductive layer, and a gate cap insulating film on predetermined regions of the first conductive semiconductor substrate and the second conductive well; Forming sidewall spacers on both sides of the gate electrode; Forming a semiconductor layer over the first conductive semiconductor substrate and the second conductive well between the isolation insulating films; The second conductive type impurity ions are implanted into the semiconductor layer on the upper side of the first conductive type semiconductor substrate and heat-treated to form a second conductive type contact pad, and at the same time, the first conductive type semiconductor is located below the second conductive type contact pad. Forming a second conductivity type impurity region on the substrate; The first conductive type impurity ions are implanted into the semiconductor layer on the second conductive type well and heat-treated to form a first conductive type contact pad, and at the same time, the second conductive well under the first conductive type contact pad is formed. Forming a first conductivity type impurity region; And forming a wiring layer to be electrically connected to the first and second conductive contact pads. The method of claim 1, wherein the semiconductor layer is formed at the same height as the gate cap insulating layer. The method of claim 2, wherein the forming of the semiconductor layer at the same height as the gate cap insulating layer comprises forming a semiconductor layer on the entire surface of the substrate including the gate electrode, and polishing the gate cap insulating layer including the semiconductor layer. Forming a contact wiring only between the gate electrodes. 4. The contact wiring of a semiconductor device according to claim 3, wherein said gate cap insulating film before forming said semiconductor layer between said gate electrode by grinding said semiconductor layer and said gate cap insulating film is formed to have a thickness of 3000 to 5000 GPa. Formation method. The method of claim 4, wherein the semiconductor layer above the isolation insulating layer is removed from the semiconductor layer. 6. The method of claim 5, wherein when the insulating insulating film is formed of a field oxide film, a photosensitive film is coated on the entire surface of the semiconductor layer including the gate cap insulating film to remove the semiconductor layer above the insulating insulating film. A contact wiring formation method for a semiconductor device, comprising the exposure process using a used LOCOS mask.

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