JPH07326966A - Pll circuit - Google Patents

Abstract

PURPOSE:To form a PLL circuit of a VCO system capable of obtaining high oscillation stability by absorbing the variation of processes. CONSTITUTION:Through the use of a VCO 11 provided with a first terminal for inputting control voltage from a loop filter 6 and a second terminal for connecting a range resistor for adjusting an output frequency range, a frequency detection circuit 12 detects whether or not the output signal frequency of VCO is within a prescribed frequency range based on a reference clock. Then, a digital signal corresponding to the detection result is outputted as a select signal and the resistor of a serial resistor circuit network is selectively connected to the second terminal of VCO 11 corresponding to this select signal so as to change the range resistance of VCO.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit suitable for a digital demodulation circuit and for reproducing the clock signal synchronized with an external input signal.

[0002]

2. Description of the Related Art In general, a circuit for digitally demodulating an audio signal in a receiver for BS or CS broadcasting, as shown in FIG. 4, uses a detection circuit 2 based on an oscillation signal from a crystal oscillator circuit 1 for carrier synchronization. An input digital modulation signal is detected and a baseband signal is generated. Then, this baseband signal is input to the PLL circuit 3, where a baseband latch clock signal synchronized with the baseband signal is reproduced, and this is input to the clock terminal of the latch circuit 4 to latch the baseband signal and latch it. The subsequent data and reproduction clock are sent to the digital signal processing circuit in the subsequent stage for use.

Since high oscillation stability is required for such a PLL circuit, as shown in the figure, the phase comparator 5, the loop filter 6, the voltage controlled crystal oscillator (VCXO) 7, and the frequency divider are conventionally used. VCXO type PL consisting of 8
The L circuit has been widely used.

[0004]

However, in the PLL circuit of the VCXO system, the crystal oscillator and the voltage variable capacitance diode are required as external parts, which is not preferable in the case of integration. Therefore, it is conceivable to use a normal voltage controlled oscillator (VCO) instead of the VCXO. However, in order to obtain high oscillation stability, the pull-in range of the PLL cannot be wide, and therefore the VCO itself may be affected by variations in the manufacturing process. If the oscillation frequency of the
There was a problem that it would be impossible to pull in at.

Therefore, according to the present invention, a VCO type PLL that absorbs process variations and obtains high oscillation stability.
The purpose is to provide a circuit.

[0006]

SUMMARY OF THE INVENTION The present invention is a voltage controlled oscillator having a first terminal for inputting a control voltage from a loop filter and a second terminal for adjusting an output frequency range, and an output of the voltage controlled oscillator. In a PLL circuit equipped with a phase comparator for inputting a signal to one end and an external signal to the other end, frequency detection for detecting whether or not the output signal frequency of the voltage controlled oscillator is within a predetermined frequency range A circuit, a resistor circuit network for selectively connecting a resistor to the second terminal of the voltage controlled oscillator according to an input select signal, and the select signal for the resistor circuit network according to the detection result of the frequency detection circuit. And a resistance selector for outputting the above are provided to solve the above problems.

Further, in the present invention, the frequency detection circuit includes a counter that counts a reference clock for one cycle of the output signal of the voltage controlled oscillator, and a comparator that compares the content of the counter with a predetermined value. The resistance selector includes an up-down counter that counts up and down according to the comparison result of the comparator, and a decoder that decodes the contents of the up-down counter and outputs the select signal.

Further, in the present invention, the frequency detection circuit compares a first counter which counts a reference clock for one cycle period of an output signal of the voltage controlled oscillator with the content of the first counter with a predetermined value. A comparator and a second counter that counts the output signal of the voltage controlled oscillator, and inputs the comparison result of the comparator to the resistance selector every time the content of the second counter reaches a specific value. .

Further, in the present invention, the PLL circuit is a PLL circuit for inputting a baseband signal obtained by detecting a digital demodulated signal by a detection circuit as the external signal and reproducing a clock signal synchronized with the external signal. , The frequency detection circuit outputs 1 of the output signal of the voltage controlled oscillator.
A counter for counting the reference clock of the cycle period and a comparator for comparing the content of the counter with a predetermined value, and inputting an oscillation signal of a crystal oscillator for carrier synchronization connected to the detection circuit as the reference clock. Characterize.

[0010]

According to the present invention, if the frequency detection result by the frequency detection circuit is not within the frequency range in which the PLL can be pulled in, the range resistance of the VCO is switched to shift the oscillation frequency range of the VCO. By this, VCO11
The oscillating frequency of is within the frequency range in which the PLL can be pulled in, and thereafter the phase is locked by the original operation of the PLL.

[0011]

1 is a block diagram showing the configuration of an embodiment of the present invention, in which the same components as those of the conventional example of FIG. 4 are designated by the same reference numerals. In the present invention, the conventional VCXO 7 is replaced with a VCO 11 that does not require external components. This VCO 11 has a first terminal for inputting the control voltage from the loop filter 6 and a range resistor for adjusting the output frequency range. A second terminal for connection.

Further, the frequency detection circuit 12 for detecting whether or not the output signal frequency of the VCO 11 is within a predetermined frequency range based on the reference clock, and the frequency detection circuit 12
A resistor selector 13 that outputs a digital signal corresponding to the detection result of 1 as a select signal, and a resistor network 14 that selectively connects a resistor to the second terminal of the VCO 11 according to the input select signal are provided. Here, since the oscillation clock of the crystal oscillation circuit 1 for carrier synchronization is usually considerably higher than the baseband latch clock,
It is suitable as a clock for frequency measurement.

With such a configuration, if the frequency detection result by the frequency detection circuit 12 is not within the pull-in frequency range of the PLL, the range resistance of the VCO 11 is switched to control the oscillation frequency of the VCO 11. As a result, the oscillation frequency of the VCO 11 falls within the pull-in frequency range of the PLL, and thereafter the phase is locked by the original operation of the PLL.

Next, a specific circuit example shown in FIG. 2 will be described. First, the frequency detection circuit 12 receives the frequency-divided signal from the frequency divider 8, detects the edge thereof, and outputs the pulse signal shown in FIG. 3b, and the carrier synchronization crystal oscillation circuit 1. A first counter 21 that inputs a reference clock to a clock terminal and an output pulse signal of the edge detection circuit 20 to a reset terminal, and a second counter 21 that inputs an output pulse signal of the edge detection circuit 20 to a clock terminal.
The counter 23, the count result A of the first counter 21, the lower limit count value B and the upper limit count value C for reference are input, and it is determined whether the count result A is within the range surrounded by B and C. And a comparator 22 for judging.

Further, the resistance selector 13 inputs the first output and the second output of the comparator to the counter enable terminal CE and the up / down control terminal, respectively, and inputs the output of the second counter 23 to the clock terminal. Of the up / down counter 24 and a decoder 25 for converting the 4-bit output of the counter 24 into a 16-bit select signal in which only one bit is at H level. When, the input signal to the CE terminal becomes L level indicating the inactive state, when A <B, the input signal to the U / D terminal becomes L level indicating the down mode, and the input signal to the CE terminal Becomes H level indicating active state, and when A> C,
The input signal to the U / D terminal becomes the HL level indicating the up mode, and the input signal to the CE terminal becomes the HL level indicating the active state.

On the other hand, the resistor network 14 includes a resistor group in which 15 resistors 100 to 114 having a resistance value r1 and one resistor 115 having a resistance value r2 are connected in series, and each resistor 100.
~ 115 transmission gates 200-215 connected between one end of ~ 115 and the second terminal of VCO 11
And each transmission gate 200 to 21
A 16-bit signal from the decoder 25 is input to each of the signals 5. Therefore, when the on resistance of the transmission gate is R, the combined resistance of the series resistance group is r2 + nr.
It becomes 1 + R (n = 0 to 15).

In the VCO 300, a resistor 300 having a resistance value r3 is connected between the second terminal and the power supply voltage, and the voltage at the connection point between the resistor r3 and the transmission gate adjusts the oscillation frequency range of the VCO. Is supplied as a range control voltage. In this embodiment, since the up / down counter 24 is composed of 4 bits, -8 to
16 states of +7 can be taken, and when 0, series resistance group 10
It is configured so that a resistor in the middle of 0 to 115 is selected. The frequency when the data latch clock is locked is 1024 kHz, and the reference clock is 2
2.909 MHz shall be used.

The operation of this embodiment will be described below with reference to the timing chart of FIG. Baseband latch clock, which is a divided signal of VCO 11 (FIGS. 3a and 3e)
Is input to the edge detection circuit 20, a pulse signal (FIGS. 3B and 3G) corresponding to the rising edge is output, and the pulse signal resets the first counter 21. Therefore, the first counter 21 keeps the reference clock (see FIG. 3) for the period of one cycle of the baseband latch clock.
Count f). In this embodiment, the frequency when the baseband latch clock is locked is 10 as described above.
Since the reference clock is 24 kHz and 22.909 MHz is used, the count value (FIG. 3h) of the first counter 21 is “22” or “23” when locked. On the other hand, as the upper limit count values B and C, for example, “2
0 "and" 25 "are set. Therefore, if the count value A is 20 <A <25, the signal to the CE terminal becomes inactive and the count value of the up / down counter 24 does not change.

However, due to process variations, VC
If the oscillation frequency of O11 deviates, the content of the first counter exceeds the upper limit or lower limit count value, and CE
The signal to the terminal becomes active, and if A <20, the counter 24 is in the down mode, and if A> 25, the counter 24 is in the up mode. Here, the second counter 2
3 counts the baseband latch clock and generates an output signal (FIG. 3c) when the content (FIG. 3d) reaches a specific value, for example, “10”. Therefore, 1 is generated in every 10 cycles of the baseband latch clock. Only once, the contents of the counter 24 are up and down by the up / down mode signal to the U / D terminal of the comparator 22.
The second counter 23 is used in order to stabilize the VCO oscillation frequency by switching the range resistance by changing the contents of the up / down counter with an appropriate interval. The output of the edge detection circuit 20 is directly omitted and the up / down counter 24 is directly omitted.
Alternatively, the frequency detection result may be fetched into the counter 24 every one cycle of the baseband latch clock by inputting to the clock terminal.

In this way, the up / down counter 2
When the content of 4 changes, a decode signal corresponding to the content of 4 is output from the decoder 25, and different transmission gates of the series resistance group are turned on, whereby the range resistance connected to the second terminal of the VCO 11 changes. The value changes, and the range control voltage of the VCO also changes accordingly. Therefore, the oscillation frequency range of the VCO 11 changes and falls within the pull-in range of the PLL. Specifically, if the frequency of the baseband latch clock is too low, the content of the up / down counter 24 goes down, which turns on the lower transmission gate of the resistor network 14. Therefore, the value of the combined resistance connected to the second terminal of the VCO 11 becomes small, the range control voltage drops, and the oscillation frequency range of the VCO 11 shifts to the lower side. For this reason, even if the voltage from the loop filter 6 is the same, the oscillation frequency of the VCO 11 becomes low, so that it falls within the pull-in range of the PLL.

On the contrary, if the frequency of the baseband latch clock is too high, the content of the up / down counter 24 is increased, and the upper transmission gate of the resistor network 14 is turned on. Therefore, VC
The value of the combined resistance connected to the second terminal of O11 increases, the range control voltage rises, and the oscillation frequency range of VCO 11 shifts to the higher side. For this reason, even if the voltage from the loop filter 6 is the same, the oscillation frequency of the VCO 11 becomes high and falls within the pullable range of the PLL. After that, the locked state is maintained by the original operation of the PLL.

As described above, even if the oscillation frequency of the VCO 11 shifts due to process variations, the oscillation frequency of the VCO can be set within the pull-in range of the PLL by changing the value of the range resistance.

[0023]

According to the present invention, a PLL circuit having high oscillation stability can be constructed without using external parts such as a crystal oscillator or a voltage variable capacitance diode, which is optimal for integration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a specific circuit configuration of an example.

FIG. 3 is a diagram showing a timing chart of an example.

FIG. 4 is a block diagram showing a conventional PLL circuit.

[Explanation of symbols]

 1 crystal oscillator circuit for carrier synchronization 2 detection circuit 3, 10 PLL circuit 4 baseband latch circuit 5 phase comparator 6 loop filter 8 frequency divider 11 VCO 12 frequency detection circuit 13 resistance selector 14 resistance network

Claims (4)

[Claims] 1. A voltage controlled oscillator having a first terminal for inputting a control voltage from a loop filter and a second terminal for adjusting an output frequency range; and an output signal of the voltage controlled oscillator at one end and the other end. In a PLL circuit having a phase comparator for inputting an external signal, a frequency detection circuit for detecting whether or not the output signal frequency of the voltage controlled oscillator is within a predetermined frequency range, and an input select signal. A resistor circuit network that selectively connects a resistor to the second terminal of the voltage controlled oscillator according to the above, and a resistor selector that outputs the select signal to the resistor circuit network according to the detection result of the frequency detection circuit. A PLL circuit characterized by the above. 2. The frequency detection circuit includes a counter that counts a reference clock for one cycle of the output signal of the voltage controlled oscillator, and a comparator that compares the content of the counter with a predetermined value. 2. The PLL according to claim 1, comprising an up-down counter that counts up and down according to a comparison result of the comparator, and a decoder that decodes the content of the up-down counter and outputs the select signal. circuit. 3. The frequency detection circuit includes a first counter that counts a reference clock for one period of an output signal of the voltage controlled oscillator, a comparator that compares the content of the first counter with a predetermined value, and the voltage. 2. A second counter for counting the output signal of the controlled oscillator, wherein the comparison result of the comparator is input to the resistance selector every time the content of the second counter reaches a specific value. PLL circuit. 4. The PLL circuit is a PLL circuit for inputting a baseband signal obtained by detecting a digital demodulated signal by a detection circuit as the external signal and reproducing a clock signal synchronized with the external signal, wherein the frequency detection is performed. The circuit is
An oscillation signal of a crystal oscillator for carrier synchronization, which comprises a counter that counts a reference clock for one period of the output signal of the voltage controlled oscillator and a comparator that compares the content of the counter with a predetermined value, and is connected to the detection circuit. 2. The PLL circuit according to claim 1, wherein is input as the reference clock.