JPH07321282A - Semiconductor device, method of fabricating the same and fabricating apparatus - Google Patents

Abstract

PURPOSE:To simplify a structure, realize high reliability and improve integration density by exposing an electrode pad at the side surface of a laminated semiconductor substrate and mutually connect the pad and semiconductor substrate with a wiring layer formed at the side surface thereof to form the integrated circuit function. CONSTITUTION:A semiconductor substrate 8 on which an electrode pad 9 is formed is stacked in a plurality sheets. The electrode pad 9 is exposed at the side surface of the stacked semiconductor substrate 8 and these are mutually connected with a wiring layer 10,formed at the side surface thereofto form an integrated circuit function. As explained above, since the semiconductor substrate 8 is stacked in direct without using wiring substrate and the electrode pad 9 exposed at the side surface is mutually connected with the gas deposition method, the volume occupied by the semiconductor device can be made very small to obtain a very small size and high functional semiconductor device can be obtained. Moreover, since the constitution is simplified, high reliable device can be fabricated easily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode forming method for a semiconductor device, a semiconductor device formed by the method, and a manufacturing apparatus.

[0002]

2. Description of the Related Art In recent years, high density integration of semiconductor devices, particularly LSI, has been remarkable, but there is a limit to integration by miniaturizing an area in the horizontal direction. Consideration is being given to integration and speeding up. FIG. 18 is a sectional view showing a structure of a conventional semiconductor device having a structure in which semiconductor chips are stacked (hereinafter referred to as a stacked semiconductor device). In the figure, 1 is a semiconductor chip, 2 is a wiring board on which the semiconductor chip 1 is mounted, 3 is a wiring layer arranged on the wiring board 2, and 4 is an electrode of the semiconductor chip 1 and the wiring layer 3 of the wiring board 2 are connected. Wire 5 is a through hole provided in the wiring board 2, 6 is a through hole 5
To connect the wiring layers 3 of the two wiring boards 2 to each other, for example, a bonding material such as solder, 7 is inserted into the through hole 5 to connect the wiring layers 3 of the two wiring boards 2 to each other, and A pin that becomes a terminal.

As shown in FIG. 18, a semiconductor chip 1 is once mounted on another wiring board 2, the wiring boards 2 are laminated and the wiring layers 3 are interconnected.

[0004]

The conventional semiconductor device is
Since it is configured as described above, the number of parts is increased by providing the wiring board 2 separately, and the structure becomes complicated as an integrated semiconductor element. For this reason, the reliability is lowered and the manufacturing cost is increased, which is difficult to put into practical use.

The present invention has been made to solve the above problems, and an object thereof is to obtain a stacked semiconductor device having a simple structure, high reliability, and improved integration. Further, it is an object of the present invention to provide a manufacturing method and a manufacturing apparatus suitable for this laminated semiconductor device.

[0006]

[Means for Solving the Problems] Claim 1 according to the present invention
The semiconductor device described is a semiconductor substrate in which a plurality of semiconductor substrates on which element pads are formed are formed, and the electrode pads are
It is exposed on the side surface of the stacked semiconductor substrates and interconnected by a wiring layer formed on this side surface to form an integrated circuit function.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises a step of laminating a plurality of semiconductor substrates each having an element structure and electrode pads formed on a peripheral portion thereof, and then a step of forming the laminated semiconductor substrates. A step of removing the surface portion of the side surface by polishing or the like to expose the electrode pad, and then spraying ultrafine metal particles from a nozzle by a gas deposition method to form a wiring layer on the side surface of the laminated semiconductor substrate. And connecting the electrode pads to each other.

According to a third aspect of the present invention, in a semiconductor device according to the present invention, a wiring layer is formed on a semiconductor substrate having an element structure so as to have intersecting portions that intersect each other with an insulating film interposed therebetween, and the insulating film is formed as described above. It is formed only at the intersection.

According to a fourth aspect of the present invention, in the semiconductor device according to the fourth aspect, the wiring layers are formed on the side surfaces of the stacked semiconductor substrates so as to have intersecting portions intersecting each other with the insulating film interposed therebetween, and the insulating film is formed. It is formed only at the intersection.

A semiconductor device manufacturing method according to a fifth aspect of the present invention uses a technique of spraying ultrafine particles from a nozzle by a gas deposition method to form a film on a semiconductor substrate, and a wiring which becomes a lower layer at an intersection. A layer is formed by spraying ultrafine metal particles, and then an insulating film is formed on the wiring layer at the intersection by spraying ultrafine particles of an insulating material. It is formed by spraying fine particles.

According to a sixth aspect of the present invention, a bump electrode is formed on a side surface of a stacked semiconductor substrate or a main surface of the uppermost semiconductor substrate.

A semiconductor device according to a seventh aspect of the present invention has a through hole, and the bump electrode upper layer portion is inserted into the through hole of the mounting substrate on which the wiring layer connected from the through hole is formed. And a conductive bonding material is used to bond the side surfaces of the stacked semiconductor substrates or the main surface of the uppermost semiconductor substrate to the mounting substrate.

The semiconductor device according to the eighth aspect of the present invention is one in which the laminated semiconductor substrates are covered with a sealing resin except for the tops of the bump electrodes.

According to a ninth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein bumps are produced by spraying ultrafine metal particles from a nozzle onto a side surface of a stacked semiconductor substrate or a main surface of the uppermost semiconductor substrate by a gas deposition method. It forms an electrode.

According to a tenth aspect of the present invention, in the semiconductor device according to the tenth aspect, the bump electrode is formed in a predetermined region other than on the electrode pad, and a lead line made of a conductive film connecting the bump electrode and the electrode pad is formed. It was done.

A semiconductor device according to an eleventh aspect of the present invention has an electrode pad, a bump electrode, and a lead line made of a conductive film on a semiconductor substrate having elements, and the bump electrode is on the electrode pad. The lead line is formed in a predetermined region other than the above and connects the bump electrode and the electrode pad.

According to a twelfth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein ultrafine metal particles are sprayed from a nozzle by a gas deposition method onto a main surface of a semiconductor substrate or side surfaces of stacked semiconductor substrates to form bump electrodes. In the method for manufacturing a semiconductor device to be formed, the electrode pads previously formed by spraying the ultrafine metal particles while relatively scanning the bump electrode formation surface of the semiconductor substrate and the nozzle in planes parallel to each other. A lead line is formed from the area, and it is stationary at a predetermined position and the ultrafine metal particles are deposited to a predetermined height to form the bump electrode, or conversely, the bump electrode is formed at a predetermined position. The lead line is formed continuously up to the electrode pad region.

A semiconductor device according to a thirteenth aspect of the present invention is such that the bump electrode, the lead wire, or the wiring layer has a multilayer structure made of a plurality of kinds of metals.

According to a fourteenth aspect of the present invention, in the semiconductor device according to the fourteenth aspect, the lowermost layer of the bump electrode, the lead wire or the wiring layer having a multi-layer structure is made of Ti or Cr.

According to a fifteenth aspect of the present invention, in a semiconductor device manufacturing apparatus, a plurality of ultrafine particle producing means for producing ultrafine particles by heating and evaporating a plurality of types of raw materials, respectively, and a plurality of produced ultrafine particles. A plurality of transportation means for transporting the fine particles into the film forming chamber and a plurality of nozzles in the film forming chamber are used to continuously spray and deposit the plurality of types of ultrafine particles on the substrate to be processed to form a multi-layered film. And means for forming.

According to a sixteenth aspect of the present invention, in the semiconductor device according to the sixteenth aspect, a heat radiating plate is provided between the stacked semiconductor substrates, and a part of the heat radiating plate is projected from the side surface of the semiconductor substrate, and the heat radiating plate is projected. A wiring layer is formed on the side surface of the stacked semiconductor substrate which is not formed.

According to a seventeenth aspect of the present invention, in the semiconductor device according to the seventeenth aspect, a heat radiating plate is provided between the stacked semiconductor substrates, a part of the heat radiating plate is projected from the side surface of the semiconductor substrate, and the heat radiating plate is projected. A wiring layer is formed on the side surface of the stacked semiconductor substrate, which is not stacked, and is covered with a sealing resin except for the top of the bump electrode and the protruding portion of the heat dissipation plate.

[0023]

In the semiconductor device according to the present invention, a plurality of semiconductor substrates are directly laminated without using a separate wiring substrate, and the electrode pads are exposed on the side surface and interconnected by the wiring layer to form an integrated circuit function. It is possible to obtain a highly functional semiconductor device integrated into an extremely small volume. Moreover, since the structure is simple, reliability is also improved.

Wiring for removing the surface portions of the side surfaces of the stacked semiconductor substrates to expose the electrode pads on the side surfaces and interconnecting the electrode pads by a gas deposition method (hereinafter referred to as G / D method). A layer is formed on the side surface. By using the G / D method in this way, a wiring layer can be formed on the side surface of the stacked semiconductor substrates, and a plurality of semiconductor substrates can be formed.
By connecting the electrode pads by a wiring layer on the side surface, an integrated semiconductor device is obtained. This makes it possible to easily manufacture an extremely small and highly functional stacked semiconductor device.

Further, since the wiring layer has the intersecting portion on the semiconductor substrate, the wiring layers can be electrically separated and intersect with each other, and the degree of freedom in designing the semiconductor device is improved.

Further, since the wiring layer formed on the side surface of the stacked semiconductor substrates is provided with the intersection, the degree of freedom in interconnection between the electrode pads is increased, and the degree of freedom in designing the semiconductor device is improved.

Further, since the lower wiring layer is formed by the G / D method, the insulating film is formed only in the region to be the intersection, and the upper wiring layer is further formed, so that the intersection can be easily and continuously formed. It is possible to form a wiring layer having

Further, since the bump electrodes are provided on the side surface or the upper surface of the laminated semiconductor substrates, the extremely small and highly functional laminated semiconductor device can be surely connected to the external electronic device. Further, since the bump electrodes can be formed not only on the upper surface of the stacked semiconductor substrates but also on the side surfaces, the number of electrodes taken out to the outside is increased and the degree of freedom in designing the semiconductor device is improved.

Further, since the bump electrode is inserted into the through hole and joined to the mounting substrate, the very small and highly functional laminated semiconductor device can be surely connected to the outside. Further, it is possible to bond the side surface and the upper surface of the stacked semiconductor substrates to the mounting substrate, and the degree of freedom in designing the semiconductor device is improved. Furthermore, in the case of joining the side surface and the mounting board, the interconnection between the electrode pads exposed on the side surface can use both the wiring layer formed on the side surface and the wiring layer formed on the mounting board. The degree of freedom of interconnection between the electrode pads is extremely increased, and the degree of freedom in design is improved, and the number of extraction electrodes to the outside is increased.

Further, since the bump electrode is sealed with resin except the top portion thereof, a very small and highly functional laminated resin-sealed semiconductor device can be obtained.

Further, since the bump electrodes are formed by the G / D method, the stacked semiconductor device as described above, in which the bump electrodes are formed on the side surface or the upper surface of the stacked semiconductor substrates and connected to the outside, is easy. Can be manufactured.

Further, since the lead line is provided and the bump electrode is formed in a region other than the electrode pad, the position where the bump electrode is formed is not limited, and the degree of freedom in designing the semiconductor device is improved. Further, when mounting on the mounting board, the position of the through hole is not limited on the mounting board side, so that the degree of freedom in design is improved.

Further, since the lead line and the bump electrode are continuously formed by the G / D method, the electrode structure having a high degree of freedom can be easily manufactured.

Further, since the bump electrode, the lead wire or the wiring layer has a multi-layer structure, the underlying metal layer can be formed below the main metal layer, and by selecting an appropriate material,
Improves adhesion to semiconductor substrates and electrode pads and prevents mutual diffusion. Furthermore, by using a metal layer made of Ti or Cr as the lowermost layer, the above effect can be reliably obtained.

Further, the GD apparatus has a plurality of ultrafine particle generating means, and a plurality of kinds of ultrafine particles are transported to a plurality of nozzles by a plurality of transportation means and continuously sprayed to form a multi-layered film. Since it is configured to have a means, it is possible to continuously and easily form a film having a multi-layer structure in the same film forming chamber, and it is possible to easily manufacture a bump electrode, a lead wire, a wiring layer and a wiring layer having an intersecting portion having a multi-layer structure. .

Further, since a heat radiating plate is provided between the stacked semiconductor substrates and a part of the heat radiating plate is protruded from the side surface of the semiconductor substrate, it is very small and has high functionality, good heat dissipation and good reliability. A highly stacked semiconductor device can be obtained. Further, a laminated semiconductor device having such a heat dissipation plate, on which bump electrodes are formed, is covered with sealing resin except for the tops of the bump electrodes and the protruding parts of the heat dissipation plate. A resin-sealed semiconductor device of the mold is obtained.

[0037]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. Note that the description of the same parts as those of the conventional technique will be appropriately omitted. 1 is a perspective view showing a structure and a manufacturing method of a semiconductor device according to a first embodiment of the present invention. As shown in the figure, a plurality of semiconductor substrates 8 are stacked, and the electrode pads 9 exposed on the end faces are interconnected by a wiring layer 10 to form an integrated stacked semiconductor device.

Such a stacked semiconductor device is manufactured as follows. First, a plurality of semiconductor substrates 8 each having an element structure and having electrode pads 9 formed on the periphery thereof are attached to each other by using a material such as polyimide. Next, the side surfaces of the semiconductor devices which are stacked and have a three-dimensional structure are subjected to a method such as polishing to expose the electrode pads 9 on the surface. Next, G ・ D
By the method, the ultrafine metal particles 12 are sprayed from the nozzle 11 to form the wiring layer 10 and interconnect the predetermined electrode pads 9. As a result, the stacked semiconductor device has an integrated circuit function.

The GD method is a technique developed in recent years, in which ultrafine particles are sprayed from a nozzle onto a substrate to form a film.
The outline will be described below. First, a raw material such as a metal is heated and evaporated in an ultrafine particle generation chamber pressurized with an inert gas. Then, the vaporized metal atoms are cooled by the collision with the inert gas and condensed to generate high-purity ultrafine particles. In addition to the ultrafine particle production chamber with high pressure, a low-pressure biofilm chamber is provided, and the ultrafine particles produced as described above are passed through the transport pipe together with the inert gas by utilizing the pressure difference between the two chambers. Eject at high speed from a thin nozzle.
It is possible to form a film by colliding and adhering the jetted ultrafine particles on a substrate to be processed placed under reduced pressure.
Method D.

As described above, according to the first embodiment, the semiconductor substrate 8 is directly laminated without using a separate wiring substrate and the electrode pads 9 exposed on the end faces are interconnected by the G / D method. Can occupy a very small volume, and a very small and highly functional semiconductor device can be obtained. Further, since the structure is simple, a highly reliable one can be easily manufactured.

The wiring layer 10 formed by the G / D method is shown in FIG.
The structure shown in FIG. 2 is not limited to the one parallel to the stacking direction of the semiconductor substrates 8 and may be the one shown in FIG.

Example 2. The following is a description of the laminated semiconductor device shown in the first embodiment, in which the electrode pads 9 are provided with the intersections when they are interconnected by the G / D method.
Second Embodiment FIG. 3 is a side view showing the structure of a semiconductor device according to a second embodiment of the present invention. In the figure, 13 is an intersection of the wiring layer 10, and the cross-sectional structure of this intersection 13 is shown in FIG.
As shown in FIGS. 3 and 4, the lower wiring layer 10a
At the intersection 13 where the wiring layer 10b and the upper wiring layer 10b intersect, the insulating film 14 is formed on the wiring layer 10a, and the wiring layer 10b is formed thereon. In this way, the wiring layers 10 interconnecting the electrode pads 9 of the stacked semiconductor device are electrically separated from each other by interposing the insulating film 14, so that the wiring layers 10 intersect each other. And the degree of freedom in designing the semiconductor device is improved.

The formation of the intersection 13 as described above is
The G / D method can be used. In the G / D method, not only a metal but also an insulating material such as Al ₂ O ₃ can be formed.
Then, the insulating film 14 is formed only on the intersections 13 by the G.D method, and the wiring layer 10b is further formed by the G.D method.

Incidentally, the intersection 1 as shown in the second embodiment.
The formation of 3 is not limited to the wiring layer 10 formed on the side surface in the laminated semiconductor device, but can be widely applied to a semiconductor substrate having only one wiring layer as long as the wiring layer is formed by the G / D method. effective.

Example 3. Next, the uppermost semiconductor substrate 8 of the stacked semiconductor device shown in the first and second embodiments.
In the figure, a main surface of which is provided with bump electrodes for connection to the outside is shown. 5 is a side view showing the structure of a semiconductor device according to a third embodiment of the present invention. In the figure, 15 is a bump electrode formed on the electrode pad 9 on the main surface of the stacked uppermost semiconductor substrate 8.

Such a bump electrode 15 is formed by the G · D method as follows. The operation stage is scanned to align the electrode pad 9 directly below the nozzle 11, the ultrafine metal particles 12 produced in the ultrafine particle producing chamber are guided through the transport pipe, and high speed injection is performed from the subsequent nozzle 11. After the metal ultrafine particles 12 are sprayed for a predetermined time by the shutter provided on the transport pipe to form the bump electrode 15 having a predetermined height on the electrode pad 9, the electrode pad 9 for forming the next bump electrode 15 is formed. The nozzle 11 is moved directly below.

Further, the laminated semiconductor device having the bump electrodes 15 shown in FIG. 5 may be mounted on a mounting substrate 17 such as a flexible film having through holes 16 as shown in FIG. As shown in FIG. 6, a wiring layer 18 is provided on both surfaces of the mounting substrate 17 and is integrated with a metal 18a adhered to the inner wall of the through hole 16, and the upper layer portion of the bump electrode 15 is inserted into the through hole 16, The semiconductor device is mounted by joining the upper layer portion of the bump electrode 15 and the metal 18a on the inner wall of the through hole 16 with a conductive joining material 19 such as solder.

Furthermore, the bump electrode 15 shown in FIG.
As shown in FIG. 7, the stacked semiconductor device having the
Only the top of the bump electrode 15 may be exposed and sealed with the sealing resin 20.

According to the third embodiment, it is possible to easily take out the connection terminal with the external electronic device in the highly functional stacked semiconductor device integrated in an extremely narrow area.

Example 4. The bump electrode 15 formed on the main surface of the uppermost semiconductor substrate 8 of the stacked semiconductor device may be formed in a region other than the electrode pad 9, and as shown in FIG. The line 21 may be formed, and the bump electrode 15 may be formed at a predetermined position by connecting to the line 21.

The bump electrode 15 and the lead wire 21 shown in FIG. 8 are formed by the G / D method as follows. As shown in FIG. 9, while scanning the operation stage holding the semiconductor device, the ultrafine metal particles 12 are sprayed from the nozzle 11 to form the lead wire 21 on the electrode pad 9, and the operation stage is stopped at a predetermined position. The bump electrode 15 is formed to a predetermined height. On the contrary, the bump electrode 15 may be first formed at a predetermined position, and then the operation stage may be scanned to form the lead line 21 up to the electrode pad 9.

In the fourth embodiment, the position where the bump electrode 15 is formed is not limited to the electrode pad 9, so that the degree of freedom in designing the semiconductor device is improved. Further, when the mounting board 17 is mounted, the degree of freedom in designing the mounting board 17 is improved.
In addition, the lead wire 21 and the bump electrode 1 are formed by the G / D method.
Since 5 and 5 are continuously formed, an electrode structure having a high degree of freedom can be easily formed.

By providing the lead wire 21 as described above,
The electrode structure in which the bump electrode 15 is formed in a region other than the electrode pad 9 is not limited to the stacked semiconductor device and may be formed on a semiconductor substrate having only one layer, and the same effect can be obtained.

Example 5. The bump electrode 15 or the bump electrode 15 and the lead wire 21 shown in the third and fourth embodiments are formed on the main surface of the uppermost semiconductor substrate 8 of the stacked semiconductor device. As shown
The bump electrode 15 may be formed on the side surface of the laminated semiconductor substrate 8. When the semiconductor substrate 8 is stacked, the electrode pads 9 are exposed on the side surfaces by polishing or the like, and the wiring layer 10 for interconnecting the electrode pads 9 is formed by the G / D method, the lead wire 21 and the bump electrode 15 are continuously formed. To form.

Although FIG. 10 shows the bump electrode 15 formed on only one of the four side surfaces, it can be formed on all four surfaces. As a result, the bump electrode 15 that can be taken out to the outside can be formed not only on the upper surface of the semiconductor device but also on the side surface, and the number of electrodes is increased, and the degree of freedom in designing the semiconductor device is improved.

Further, as described above, the bump electrode 15 is formed on the side surface.
FIG. 11 shows a laminated semiconductor device in which the side surface is joined to the mounting substrate 17 having the through hole 16 by the method described in the third embodiment. As a result, the wiring that interconnects the electrode pads 9 is a three-layered wiring consisting of the wiring layer 10 formed on this side surface and the two wiring layers 18 formed on both sides of the mounting substrate 17, for each side surface. With the availability of layers, the freedom of interconnection of the electrode pads 9 is greatly increased and the design constraints are very low.
In addition, the number of electrodes that can be taken out to the outside also increases. Furthermore, it is also possible to separately use the three wiring layers 10 and 18 as a signal layer, a ground layer, and a power supply layer, respectively.

Example 6. Next, in the wiring layer 10 for interconnecting the bump electrodes 15 formed by the G / D method and the lead lines 21 and the electrode pads 9 used therewith, which are used in the first to fifth embodiments, a plurality of types are used. A structure in which different metals are laminated is shown. FIG. 12 is a cross-sectional view showing the structure and manufacturing method of the bump electrode 15 of the semiconductor device according to the sixth embodiment of the present invention. As shown in FIG.
For example, a material such as Ti or Cr is deposited as a base metal layer 22a at a predetermined position, for example, on the metal pad 9 by the G / D method, and then, as a main body of the bump electrode 15 on the base metal layer 22a, for example, Au or the like. The above materials are deposited by the G / D method.

Although FIG. 12 shows the multilayer structure of the bump electrode 15, the bump electrode 15, the lead wire 21 and the wiring layer 10 (hereinafter referred to as the bump electrode 1) formed by the G / D method.
5, the lead wire 21 and the wiring layer 10 are collectively referred to as an electrode wiring layer 22).
Also, it has the effect of increasing the adhesion between the semiconductor substrate 8 and the electrode wiring layer 22 and preventing mutual diffusion.

FIG. 13 is a schematic view of a gas deposition apparatus for forming the metal electrode layer 22 having the above-mentioned multilayer structure. In the figure, 23 is an ultrafine particle generation chamber, 24 is a film forming chamber, 25 is an ultrafine particle generation mechanism, 26 is a transport mechanism, 27 is a shutter mechanism, 28 is a nozzle, 29 is a substrate to be processed, 3
0 is the operating stage. As shown in the figure, a plurality of ultrafine particle generating mechanisms 25 are provided, and the transport mechanism 2 is correspondingly provided.
6, a plurality of shutter mechanisms 27 and a plurality of nozzles 28 are provided. As a result, the substrate 2 to be processed is removed from the film forming chamber 24.
Continuously remove two or more kinds of metals without removing 9
It can be stacked and deposited by the D method.

By using the above gas deposition apparatus, it is possible to easily obtain the electrode wiring layer 22 which has good adhesion and is prevented from interdiffusion with the base, and the reliability of the semiconductor device is improved. To do. Further, the intersection 13 of the wiring layer 10 shown in the second embodiment can be easily formed by using such a gas deposition apparatus.

Although FIG. 12 shows the two-layer bump electrode 15, an adhesion layer made of Ti or Cr is formed to improve the adhesion, and diffusion made of TiN, W, Ni, Cu or the like is formed thereon. It is also possible to form a preventive layer and further deposit a metal layer such as Au as a main component on the preventive layer. Furthermore, such an electrode wiring layer 22 having a multi-layered structure by the G / D method can be widely applied not only to a laminated semiconductor device but also to a semiconductor substrate having only one layer.

Example 7. The electrode wiring layer 22 by the G / D method used in the first to sixth embodiments is the electrode wiring layer 22.
It may be formed by forming a pattern of a photoresist film having an opening in the formation region in advance, depositing a metal film by the G / D method, and then removing the photoresist film. As a result, another adjacent electrode wiring layer 2
Prevents contact with 2 and promotes miniaturization.

Further, among the electrode wiring layers 22 by the G / D method used in the above-mentioned first to sixth embodiments, the bump electrode 1
5 may be formed at different heights, for signals,
The bump electrodes 15 having different heights for different purposes such as grounding may be used.

Example 8. Next, a laminated semiconductor device provided with a heat sink will be described below. 14 is a perspective view showing the structure of a semiconductor device according to an eighth embodiment of the present invention. As shown in the figure, the semiconductor substrate 8 and the heat dissipation plate 31 are alternately laminated and bonded to each other, and the electrode pads 9 are exposed on the side surface of the semiconductor substrate 8 where the heat dissipation plate 31 does not project, and the space between the electrode pads 9 is exposed. A mounting substrate on which the wiring layer 10 is formed by the G / D method and interconnected, the bump electrode 15 is formed at a predetermined position, and the through hole 16 corresponding to the position of the bump electrode 15 is formed and the wiring layer 18 is formed. It is joined with 17.

At this time, the heat dissipation plate 31 is projected from the semiconductor substrate 8 in two directions in which the electrode pads 9 are not interconnected by the G / D method in order to improve heat dissipation. Further, since the heat dissipation plate 31 is generally made of metal to improve heat conduction, in that case, a notch is provided in a region of the interconnect which is in contact with the wiring layer 10, and an insulating layer 32 such as an epoxy resin is embedded in the notch. .

The laminated type semiconductor device provided with such a heat dissipation plate 31 is small in size and has a high function, and is also excellent in heat dissipation of heat generated from the element. In FIG. 14, the side faces interconnecting the electrode pads 9 are two facing faces, and the projecting directions of the heat dissipation plate 31 are the other two facing directions, but the present invention is not limited thereto, and the heat dissipation plate 31 is not limited thereto. The projecting direction is arbitrary from one direction to three directions, and the side surfaces that are interconnected may be any surface of the heat dissipation plate 31 that does not project. Further, the heat dissipation plate 31 is not limited to one provided between all the semiconductor substrates, and one or more heat dissipation plates 31 are effective. Furthermore, FIG.
The semiconductor device as shown in FIG. 4 may be covered with a sealing resin except the portion of the mounting substrate 17 which will be the external electrode.

Example 9. FIG. 15 shows another example of a stacked semiconductor device provided with a heat dissipation plate. The semiconductor substrate 8 and the heat dissipation plate 31 are alternately laminated and bonded together, and the side surface of the semiconductor substrate 8 where the heat dissipation plate 31 does not project. The electrode pad 9 is exposed on the wiring layer 1 and the space between the electrode pads 9 is formed by the G / D method.
0 to form interconnections, and bump electrodes 15 are formed at predetermined positions on the main surface of the uppermost semiconductor substrate 8 by the G / D method.
Further, the top of the bump electrode 15 and the protruding portion of the heat dissipation plate 31 are exposed, and the other portions are resin-sealed.

Even in such a semiconductor device, the eighth embodiment
In the same manner as above, it is possible to obtain a small and highly functional product with excellent heat dissipation. Further, in order to further improve heat dissipation, as shown in FIG. 16, a ventilation hole 32 may be provided in the protrusion of the heat dissipation plate 31, and as shown in FIG. 17, the protrusion of the heat dissipation plate 31 is cooled. The water pipe 33 may be used. Further, the heat radiating plate 31 used in the above-mentioned eighth and ninth embodiments may be made hollow to allow ventilation or water to flow therein, and the heat radiation property is further improved.

[0069]

As described above, according to the present invention, since a plurality of semiconductor substrates are directly laminated to form an integrated circuit function, a very small and highly functional semiconductor device can be obtained.
Moreover, since the structure is simple, reliability is also improved.

Further, by laminating a plurality of semiconductor substrates and removing the surface portions of the side surfaces to expose the electrode pads on the side surfaces, G.
By the method D, a wiring layer is formed on the side surface to connect the electrode pads to each other, so that a very small and highly functional laminated semiconductor device can be easily manufactured.

Further, since the wiring layer formed on the semiconductor substrate is provided with the intersecting portion, the wiring layers can be electrically separated and intersect with each other, and the degree of freedom in designing the semiconductor device is improved. further,
Since the wiring layer formed on the side surface of the stacked semiconductor substrates is provided with the intersection, the degree of freedom of interconnection between the electrode pads is increased, and the degree of freedom in designing the semiconductor device is improved. Further, since the wiring layer having such an intersection is formed by the G / D method, the wiring layer having a high degree of freedom can be continuously and easily formed.

Further, since the bump electrodes are formed on the side surface or the upper surface of the stacked semiconductor substrates, it is possible to reliably connect the extremely small and highly functional stacked semiconductor device to an external electronic device. Further, since the number of extraction electrodes to the outside is large, a semiconductor device having a high degree of freedom in design can be obtained.

Further, by bonding the laminated semiconductor device having the bump electrodes as described above to the mounting substrate,
Can be connected to the outside reliably. Further, it is possible to join the mounting substrate on each of the side surface and the upper surface, and a semiconductor device having a high degree of freedom in design can be obtained. Further, the wiring layer formed on the mounting substrate can be used for the interconnection between the electrode pads, and the degree of freedom in the interconnection between the electrode pads is extremely large,
A semiconductor device having a high degree of freedom in design and a large number of extraction electrodes to the outside can be obtained. Furthermore, by sealing the resin excluding the bump electrode top portion, it is possible to reliably connect to the outside, and it is possible to obtain a very small and highly functional laminated resin-sealed semiconductor device.

Further, by using the G / D method, bump electrodes can be easily formed on the side surface or the upper surface of the stacked semiconductor substrates, and a very small and highly functional stacked semiconductor device connected to the outside can be manufactured. Can be done easily.

Further, since the lead wire is provided and the bump electrode is formed in a region other than the electrode pad, the position where the bump electrode is formed is not limited, and the degree of freedom in designing the semiconductor device is improved. Further, as a result, the position of the through hole of the mounting board is not limited, so that the degree of freedom in designing the mounting board is improved. Furthermore, the lead lines and the bump electrodes as described above can be easily formed continuously by the G / D method.

Further, since the electrode wiring layer has a multi-layer structure,
It is possible to obtain an electrode wiring layer having high adhesion to a semiconductor substrate or an electrode pad and preventing mutual diffusion. Further, by using Ti or Cr for the lowermost layer of the electrode wiring layer having a multilayer structure, the above effect can be ensured.

Further, since the G / D apparatus is constructed so as to continuously spray a plurality of types of ultrafine particles from a plurality of types of nozzles in the same film forming chamber to form a multi-layered film, the above-mentioned multi-layered structure is formed. The electrode wiring layer and the wiring layer having the intersection can be easily formed.

Further, by providing the heat dissipation plate between the laminated semiconductor substrates, it is possible to obtain a laminated semiconductor device which is extremely small in size, has a high function, and has a good heat dissipation property and a high reliability. Furthermore, a laminated resin-encapsulated semiconductor device having the above effect is obtained by resin-sealing a heat-dissipating plate having bump electrodes excluding the top of the bump electrode and the protruding portion of the heat-dissipating plate. can get.

[Brief description of drawings]

FIG. 1 is a perspective view showing a structure and a manufacturing method of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a side view showing an arrangement example of wiring layers in the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a side view showing a structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing a structure of an intersection of wiring layers in a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a side view showing a structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a cross-sectional view showing what mounts the semiconductor device shown in FIG. 5 on a mounting board.

FIG. 7 is a cross-sectional view showing the semiconductor device shown in FIG. 5 sealed with resin.

FIG. 8 is a perspective view showing a structure of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 9 is a sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 10 is a perspective view showing a structure of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 11 is a cross-sectional view showing what mounts the semiconductor device shown in FIG. 10 on a mounting board.

FIG. 12 is a cross-sectional view showing a structure and a manufacturing method of bump electrodes of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 13 is a schematic view of a semiconductor device manufacturing apparatus according to a sixth embodiment of the present invention.

FIG. 14 is a perspective view showing a structure of a semiconductor device according to an eighth embodiment of the present invention.

FIG. 15 is a sectional view showing a structure of a semiconductor device according to a ninth embodiment of the present invention.

FIG. 16 is a perspective view showing the structure of a modified example of the semiconductor device according to the ninth embodiment of the present invention.

FIG. 17 is a perspective view showing the structure of a modified example of the semiconductor device according to the ninth embodiment of the present invention.

FIG. 18 is a cross-sectional view showing the structure of a conventional semiconductor device.

[Explanation of symbols]

8 semiconductor substrate, 9 electrode pad, 10 wiring layer, 10
a lower wiring layer, 10b upper wiring layer, 1
1 nozzle, 12 ultrafine metal particles, 13 intersection, 14
Insulating film, 15 bump electrode, 16 through hole, 17 mounting substrate, 18 wiring layer, 19 conductive bonding material, 20 sealing resin, 21 lead wire, 22a underlying metal layer, 24
Deposition chamber, 25 ultra-fine particle generation mechanism, 26 transport mechanism,
28 nozzles, 29 substrate to be processed, 31 heat sink.

Claims (17)

[Claims] 1. A plurality of semiconductor substrates each having a device structure and having electrode pads formed thereon are stacked, and the electrode pads are exposed on a side surface of the stacked semiconductor substrate and are interconnected by a wiring layer formed on the side surface. A semiconductor device which is connected to form an integrated circuit function. 2. A step of stacking a plurality of semiconductor substrates each having an element structure and having electrode pads formed on a peripheral portion thereof, and then removing a surface portion of a side surface of the stacked semiconductor substrates by polishing or the like to form the electrode pad. And a step of spraying ultrafine metal particles from a nozzle by a gas deposition method to form a wiring layer on the side surface of the laminated semiconductor substrate and interconnecting the electrode pads. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is manufactured. 3. A wiring layer is formed on an element-configured semiconductor substrate with intersecting portions that intersect each other with an insulating film interposed therebetween, and the insulating film is formed only at the intersecting portions. Semiconductor device. 4. A wiring layer is formed on a side surface of a stacked semiconductor substrate so as to have intersecting portions that intersect each other with an insulating film interposed therebetween, and the insulating film is formed only at the intersecting portions. The semiconductor device according to claim 1. 5. A technique of depositing ultrafine particles from a nozzle by a gas deposition method to form a film on a semiconductor substrate is used to form a lower wiring layer at the intersection by spraying metal ultrafine particles, and then insulating 4. A film is formed on the wiring layer at the intersection by spraying ultrafine particles of an insulating material, and an upper wiring layer at the intersection is formed by spraying ultrafine metal particles. Alternatively, the method for manufacturing a semiconductor device according to the above item 4. 6. The semiconductor device according to claim 1, wherein bump electrodes are formed on a side surface of the stacked semiconductor substrates or a main surface of the uppermost semiconductor substrate. 7. A bump electrode upper layer portion is inserted into the through hole of a mounting substrate having a through hole, and a wiring layer connected from the through hole is formed, and is bonded by a conductive bonding material, 7. The semiconductor device according to claim 6, wherein a side surface of the stacked semiconductor substrates or a main surface of the uppermost semiconductor substrate is bonded to the mounting substrate. 8. The semiconductor device according to claim 6, wherein the stacked semiconductor substrates are covered with a sealing resin except for the tops of the bump electrodes. 9. The bump electrode is formed by spraying ultrafine metal particles from a nozzle onto a side surface of the stacked semiconductor substrates or a main surface of the uppermost semiconductor substrate by a gas deposition method. A method for manufacturing a semiconductor device according to any one of 1. 10. The bump electrode is formed in a predetermined region other than on the electrode pad, and a lead line made of a conductive film connecting the bump electrode and the electrode pad is formed. 9. The semiconductor device according to any one of 8. 11. A semiconductor substrate having an element structure, which has an electrode pad, a bump electrode, and a lead line made of a conductive film, the bump electrode is formed in a predetermined region other than the electrode pad, and the bump is formed. A semiconductor device, wherein the lead line is formed so as to connect an electrode and the electrode pad. 12. A method of manufacturing a semiconductor device, comprising: forming a bump electrode by spraying ultrafine metal particles from a nozzle onto a main surface of a semiconductor substrate or a side surface of a stacked semiconductor substrate by a gas deposition method. While relatively scanning the surface on which the bump electrode is formed and the nozzle in a plane parallel to each other, the ultrafine metal particles are sprayed to form a lead line from the electrode pad region formed in advance, and the wire is stopped at a predetermined position. Then, the ultrafine metal particles are deposited to a predetermined height to form the bump electrodes, or conversely, the lead electrodes are continuously formed to the electrode pad region after the bump electrodes are formed at predetermined positions. The method for manufacturing a semiconductor device according to claim 10, wherein 13. The semiconductor device according to claim 1, wherein the bump electrode, the lead line, or the wiring layer has a multi-layer structure made of a plurality of kinds of metals. . 14. The semiconductor device according to claim 13, wherein the lowermost layer of the multilayer bump electrode, the lead line or the wiring layer is made of Ti or Cr. 15. A plurality of ultrafine particle generating means for heating and evaporating a plurality of kinds of raw materials to generate ultrafine particles, and a plurality of transportation means for respectively transferring the generated plurality of kinds of ultrafine particles into a film forming chamber. A means for forming a multi-layered film by continuously spraying and depositing the plurality of types of ultrafine particles on the substrate to be processed from a plurality of nozzles in the film forming chamber, respectively. Manufacturing equipment. 16. A heat dissipation plate is provided between the stacked semiconductor substrates, a part of the heat dissipation plate is projected from a side surface of the semiconductor substrate, and wiring is provided on a side surface of the stacked semiconductor substrate where the heat dissipation plate is not projected. The semiconductor device according to any one of claims 1, 4, 6, 7, 10, 13 or 14, wherein a layer is formed. 17. A heat radiating plate is provided between the stacked semiconductor substrates, a part of the heat radiating plate is projected from the side surface of the semiconductor substrate, and wiring is provided on the side surface of the stacked semiconductor substrate where the heat radiating plate is not projected. 7. The semiconductor device according to claim 6, wherein a layer is formed and is covered with a sealing resin except for the top of the bump electrode and the protruding portion of the heat dissipation plate.