JPH07319778A - Memory diagnosis system - Google Patents

Abstract

PURPOSE:To shorten the memory diagnosis time by preventing the time required for memory diagnosis from being increased in proportion to the number of memory banks at the time of the increase of the number of memory banks. CONSTITUTION:When data is written in a memory bank 2a in the diagnostic access mode, data read out from the memory bank 2a is written in a memory bank 2b, and data read out from the memory bank 2b is written in a memory bank 2c, and data read out from the memory bank 2c is written in a memory bank 2d. In the memory consisting of plural memory banks in this manner, the same address is given to plural memory banks, and data written in one memory bank is written in adjacent memory banks in order.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diagnostic method for a memory composed of a plurality of memory banks, and more particularly to a diagnostic method for a memory which enables high speed diagnosis.

[0002]

2. Description of the Related Art Conventionally, this kind of memory diagnosis is performed by writing data to and reading data from each of a plurality of memory banks for each address, and checking whether the written data and the read data match. Was used to determine whether the memory bank is normal or abnormal. When the diagnosis of one memory bank is completed, the diagnosis of the next memory bank is started, and the diagnosis of each memory bank is performed in order.

[0003]

Therefore, the conventional memory diagnosis method has a problem that the time required for diagnosis increases as the number of memory banks increases and the capacity of the memory increases.

An object of the present invention is to solve such a problem and to provide a memory diagnosis method in which the time required for memory diagnosis does not increase proportionally even if the number of memory banks increases.

[0005]

In order to solve the above problems, the memory diagnostic method of the present invention provides a memory composed of a plurality of memory banks with the same address given to the plurality of memory banks at the time of diagnosis. Data writing means for sequentially writing data written in one memory bank to adjacent memory banks is provided.

[0006]

In the memory according to the diagnostic system of the present invention, by writing to one memory bank once, it is possible to write to a plurality of memory banks, and the time required for memory diagnosis is increased. Can be significantly shortened.

[0007]

An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a memory adopting a diagnosis method according to the present invention. In FIG. 1, reference numeral 1 is a control unit for which writing or reading is instructed in a normal access mode or a diagnostic access mode by a command 15, 2a, 2b, 2c and 2d are a plurality of memory banks 3a, 3b and 3c constituting a memory. , 3d are data input / output buffers for inputting / outputting data to / from the memory banks 2a, 2b, 2c, 2d, and 6 are data input / output buffers 3.
A data input / output buffer for inputting / outputting data to / from a, 3b, 3c, 3d. 7 is a memory bank 2a, 2b, 2
c, 2d are address lines for specifying the respective addresses of the memory banks, and 11 is the memory bank 2 of the control unit 1.
a, 2b, 2c, 2d control signal, 12 a control signal for the control unit 1 to control the data input / output buffers 3a, 3b, 3c, 3d, 13 a control unit 1 for controlling the data input / output buffer 6 Control signal, 14 is memory bank 2a,
Data lines for inputting / outputting data to / from 2b, 2c, 2d.

Next, the operation of the memory having the above configuration in the normal and diagnostic access modes will be described. (1) Writing in Normal Access Mode When the control unit 1 is instructed to write in the normal access mode by the command 15, the memory bank 2a, 2b, designated by the upper bit 7a of the access input from the address line 7, Control signal 11 for either 2c or 2d
(Any one of the control signals 11a, 11b, 11c, and 11d) is output to instruct the write operation, and the control signal 1
3 to output the data from the data line 14 to the data input / output buffer 6, and further to output the control signal 12 (12a,
12b, 12c, 12d) to output the data input / output buffer 6 to the data input / output buffers 3a, 3b, 3c, 3d.
The write data from is output to the memory bank. As a result, the specified memory bank fetches the data from the data input / output buffer, and the lower bit 7b of the address is read.
Stored at the address specified by.

(2) Reading in normal access mode When the control unit 1 is instructed to read in the normal access mode by the command 15, all the memory banks 2a,
A control signal 11 (11a, 11b, 1 is applied to 2b, 2c, 2d).
1c, 11d) to instruct a read operation, and control signal 12 (control signal 12a, 12b, 12c, 12d) to the data input / output buffer connected to the memory bank designated by the upper address bit 7a. ) Is output to cause the data input / output buffer to output the data from the memory bank to the data input / output buffer 6, and the control signal 13 is output to the data input / output buffer 6 to be output from the data input / output buffer to the data line 14. To be done.

(3) Writing in Diagnostic Mode When the command 15 instructs writing in the diagnostic access mode, the control unit 1 outputs the control signal 11a of the memory bank 2a to instruct the writing operation, and also the control signal. 13 to output the data line 14 to the data input / output buffer 6.
From the data input / output buffer 6 and the control signal 12a to output the write data from the data input / output buffer 6 to the memory bank 2a. As a result, the memory bank 2a fetches the data from the data input / output buffer, and the lower bit 7b of the address is read.
Stored at the address specified by.

Next, the control signal 11a for the memory bank 2a.
Is output to instruct a read operation, the control signal 11b of the memory bank 2b is output to instruct a write operation, and the control signal 12a is output to output the data read from the memory bank 2a to the data input / output buffer 3a. The data I / O buffer 3b outputs the control signal 12b to cause the data I / O buffer 3b to output the read data from the data I / O buffer 3a to the memory bank 2b. As a result, the memory bank 2b becomes the memory bank 2a.
The data from the address specified by the lower bit 7b of the address is fetched and stored in the address specified by the lower bit 7b of the address.

Next, the control signal 11b for the memory bank 2b.
To output a read operation, to output a control signal 11c for the memory bank 2c to output a write operation, and to output a control signal 12b to output data read from the memory bank 2b to the data input / output buffer 3b. The data I / O buffer 3c outputs the control signal 12c to cause the data I / O buffer 3c to output the read data from the data I / O buffer 3b to the memory bank 2c. As a result, the memory bank 2c becomes the memory bank 2b.
The data from the address specified by the lower bit 7b of the address is fetched and stored in the address specified by the lower bit 7b of the address.

Next, the control signal 11c for the memory bank 2c
To output a read operation, output a control signal 11d of the memory bank 2d to output a write operation, and output a control signal 12c to output data read from the memory bank 2c to the data input / output buffer 3c. The control signal 12d is output to the input / output buffer 3d to cause the data input / output buffer 3d to output the read data from the data input / output buffer 3c to the memory bank 2d. As a result, the memory bank 2d becomes the memory bank 2c.
The data from the address specified by the lower bit 7b of the address is fetched and stored in the address specified by the lower bit 7b of the address.

(4) Reading in Diagnostic Mode The operation of the control unit 1 when the command 15 instructs reading in the diagnostic access mode is the same as the reading in the normal access mode.

The diagnosis of this memory is performed as follows. First, when writing to the memory bank 2a in the diagnostic access mode, the data read from the memory bank 2a is written to the memory bank 2b, the data read from the memory bank 2b is written to the memory bank 2c, and the memory The data read from the bank 2c is written in the memory bank 2d. Next, reading from the memory bank 2d is performed, and it is confirmed that the data written in the memory bank 2a and the data read from the memory bank 2d match. This is repeated for all addresses in the memory bank 2a.

As described above, in the memory according to the diagnostic method of this embodiment, a plurality of banks can be diagnosed at the same time with the number of times of writing and reading required for diagnosing one memory bank. The time required for can be greatly reduced.

[0017]

As described above, according to the present invention, in a memory composed of a plurality of memory banks, the same address is given to the plurality of memory banks, and the data written in one memory bank are adjacent to each other. Since the data write means for sequentially writing data is provided, it is possible to simultaneously diagnose a plurality of banks with the number of times of writing and reading required to perform a diagnosis of one memory bank, which is necessary for the memory diagnosis. The time can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory adopting a diagnostic method according to the present invention.

[Explanation of symbols]

 1 control unit 2a, 2b, 2c, 2d memory bank 3a, 3b, 3c, 3d, 6 data input / output buffer 7 address line 7a upper address 7b lower address 14 data line 15 command

Claims (1)

[Claims] 1. In a memory composed of a plurality of memory banks, at the time of diagnosis, a data writing means for giving the same address to the plurality of memory banks and sequentially writing the data written in one memory bank to an adjacent memory bank. A memory diagnostic method characterized by being equipped with.