JP2533170Y2 - Diagnostic data capture device - Google Patents

Description

[Detailed description of the invention] "Industrial application field" This invention is applied, for example, when a semiconductor test apparatus is to be diagnosed, and for example, whether or not an output (diagnosis data) from a register is a predetermined value. The present invention relates to a device for capturing diagnostic data to be examined.

In "conventional art" conventional capture device diagnostic data, the board 50 ₁ to 50 _p, as shown in Figure 2 is part of a semiconductor testing apparatus is configured, each of these boards 50 ₁ to 50 _p various circuits Are mounted and these boards are connected to each other to constitute one device. Data to be diagnosed in each board (diagnosis data) is branched from the output side of registers (flip-flops) 51 _{1 to} 51 _q and
₁ to 50 _p of diagnostic units 52 _{1 to} 52 _p are supplied respectively. R / W control line 53 from diagnostic control unit 13, address bus 14, data bus 2
1 are connected to the diagnosis units 52 _{1 to} 52 _p , respectively. In addition,
The number of registers 51 _{1 to} 51 _{q on} each board may vary from board to board.

Diagnostic unit 52 ₁ is configured as shown in Figure 3. That is, the registers 51 ₁ ... 51 _q each output, for example, data, that is, diagnostic data D _{1 ,.} Diagnostic data in this example register 51 ₁ to 51 _q is supplied to the data input D ₀ to D ₇ of the multiplexer 11.

Address bus 14 is usually 8 bits, the lower three bits A ₀ to A ₂ in A ₀ to A ₇ is supplied as a selection signal to the multiplexer 11. Remaining address A ₃ to A ₇ are supplied to the address decoder 12, the output of the decoder 12 when the address in this example selects board 50 ₁ goes high, its output is supplied to the enable terminal E of the multiplexer 11 You.

Thus by the address A ₃ to A _7, the board 50 ₁ is selected will multiplexer 11 is enabled, if the select address A _0, A _1, A ₂ data D ₀ at 000 at that time, register Diagnostic data D ₁ 51 ₁ is selected from the multiplexer 11, and these outputs are passed through the gate 15 opened by the read command READ from the R / W control line 53 to the data bus 21.
The diagnostic data is collected by the diagnostic control unit 13. If address A ₀ to A _2, for example 111 in a manner similar diagnostic data D ₂ of the register 51 ₂ in the multiplexer 11 is taken out, it is taken into the diagnosis controller 13 through the gate 15.

In this conventional apparatus capture diagnostic data, because the address is 8-bit A ₀ to A _7, it is impossible to capture diagnostic data from only 256 points. To increase the number of diagnostic points, the number of bits of the address bus may be increased.However, considering the re-creation of the bus control associated with the diagnostic control unit 13, the addition of an address decoder for the expansion, and the scalability of the old system, Difficult.

[Means for Solving the Problems] According to the present invention, a data decoder for decoding a plurality of specific bits from a data bus is provided in a diagnostic unit, a register is provided in correspondence with the data decoder, and a data decoder is provided. When it is detected by the address decoder that the data on the data bus is a diagnostic address from the address, other specific bits of the data bus and the output of the data decoder are stored in the registers. The corresponding multiplexer is enabled by an output corresponding to the output of the data decoder of the register, and the data inputs of the multiplexers are provided with diagnostic data, and the multiplexer is provided in the other specific bits of the register. Input diagnostic data is selected and output. It is read by decree.

"Embodiment" FIG. 1 shows an embodiment of the present invention, in which parts corresponding to those in FIG. 3 are denoted by the same reference numerals. This example board 50 _s are added, an example of application to a case of collecting diagnostic data from it. Board 50 data in the diagnostic part 52 _s of _s decoder 22
Are provided, and specific bits D _{3 to} D ₇ of bits D _{0 to} D ₃₁ in data bus 21 are applied to data decoder 22. Data decoder 22 is for performing one selection in diagnosis unit newly provided, the output only when the unique data D ₃ to D ₇ are given is from a low level to a high level. An address decoder 24 is connected to the address bus 14, and the address decoder 24 decodes an address indicating that data on the data bus 21 is a diagnostic address. The output of the address decoder 24 is supplied to the gate 25, and the gate 25 is also supplied with a write command WCMD from the diagnostic control unit R / W control line 53, and the output of the gate 25 is supplied to the register 26 as a latch command.

The register 26 is provided in the diagnostic unit 52 _s , and specific bits of the data bus 21, for example, lower three bits D _{0 to} D ₂ are given to data input terminals D _{0 to} D ₂ of the register 26, and an output of the data decoder 22 is provided. There is provided to the data input terminal D _3. When a write command WCMD is given from the diagnostic control unit 13 to the gate 25,
If the address for selecting the diagnosis unit 52 _s as the data of the data bus 21 is applied, the data D ₀ to D ₂ at this time, the output of the data decoder 22 is latched in the register 26. Output Q ₃ and the corresponding output of the data decoder 22 in the output of the register 26 is inputted as the enable signal to the multiplexer 27, the output Q ₀ to Q ₂ respectively corresponding to the data D ₀ to D ₂ in the output of the register 26 Multiplexer as selection control signal
Supplied to 27. As in the case of Figure 3, the multiplexer 27 diagnostic data from the register 51 ₁ to 51 _q in the board 50 _s is given to the data input terminal D ₀ to D _7.

When a specific address indicating that diagnosis (writing) is performed from the diagnosis control unit 13 to the address decoder 24, that is, a specific address indicating that data on the data bus is an address specifying the diagnosis unit, is given. if addresses are given to the data bus 21 is only to indicate the diagnosis unit 52 _s data D ₀ to D ₂ on the data bus 21 are respectively latched in the register 26, also latches the decoded output of the data decoder 22 to the register 26 is, the diagnosis unit 52 makes the multiplexer 27 in the _s is enabled and the board 50 registers 51 ₁ to 51 in _q in _s, diagnostic data specified by bits D ₀ to D ₂ are output from the multiplexer 27, the output Is taken out to the data bus 21 through the gate 15 by a read command READ from the R / W control line 53, and is input to the diagnosis control unit 13.

"Effects of the invention" As described above, according to the invention, the address for selecting the diagnostic unit is allocated by the data bus.
Generally, the data bus is, for example, 32 bits (the address bus is 8 bits).
(Bits) and the number of bits are quite large, so using the data bus for the increase in the number of diagnostics, using the data bus, specifying the diagnostic location and taking in the diagnostic data Without increasing the number of bits on the address bus, that is, without modifying the address bus 14, the bit width of the data decoder 22,
According to the bit width of 26, the number of diagnostic locations can be increased by adding the data decoder 22 and the register 26 at any locations.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a main part of a diagnostic data capturing device according to the present invention, FIG. 2 is a block diagram showing an overall configuration of the diagnostic data capturing device, and FIG. It is a block diagram showing a part.

Claims (1)

(57) [Scope of request for utility model registration] An apparatus for taking in diagnostic data inputted from a diagnostic control unit to each diagnostic unit provided for each board to be diagnosed through a read / write control line, an address bus, and a data bus. And an address decoder for detecting, from an address from the address bus, that data on the data bus indicates that the data is a diagnostic address. A data decoder for decoding bits; and an output of the data decoder provided in the diagnostic unit, the output of the data decoder being in response to a write command from the read / write control line in the detection state, and the identification in the data bus. A register in which a second specific plurality of bits other than the plurality of bits are written; and the data provided in the diagnostic unit and being output from the register. A multiplexer that is enabled by an output corresponding to the output of the data decoder, is selectively controlled by the second specific plurality of bits in the output of the register, and receives diagnostic data input to the diagnostic unit to a data input terminal. Means for reading the outputs of these multiplexers by a read command from the read / write control line.