JPH07319696A - Information processor - Google Patents

Abstract

PURPOSE:To suppress performance decline at the time of execution in an advance off mode and to improve debugging efficiency in an information processor for performing the pipeline processing of instruction execution. CONSTITUTION:An instruction supplied by an instruction supply circuit 10 is sent to an instruction processing circuit 30 for performing the pipeline processing, the instruction executed in the respective stages is stored in an processing instruction holding circuit 60 and the instruction kind of a succeeding instruction supplied by the instruction supply circuit 10 is compared with the instruction kind registered by initial setting in an instruction storage circuit 40 in a succeeding instruction comparator circuit 50. In the case of coincidence, an instruction supply control circuit 20, the instruction processing circuit 30 and the processing instruction holding circuit 60 are controlled so as to interrupt the supply of the succeeding instruction until the processings in the instruction processing circuit 30 of all the preceding instructions are ended.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for carrying out pipeline processing, and more particularly to an information processing apparatus for avoiding logic injustice when a logic injustice exists.

[0002]

2. Description of the Related Art In order to speed up data processing in a computer, a technique for pipeline processing of data has been used in many computers. By pipeline processing the data, the processing result of the data can be output every clock.

When some kind of logic illegality exists on the pipeline, it is usually impossible to operate the computer. However, if the content of the logic illegality causes the execution result to become illegal only when the execution of a certain instruction is continuously executed in the pipeline, the execution of that instruction is not continuously executed in the pipeline. Although the processing performance will be reduced by controlling the above, it becomes possible to operate the computer while avoiding logical injustice. By avoiding logic injustice and operating it, it becomes possible to evaluate the hardware until the hardware is replaced with the one in which the logic injustice is corrected.

In order to avoid the above-mentioned logic injustice, in the conventional information processing apparatus, in addition to the normal instruction supply control system (advance on) mode, instructions are not continuously executed in the pipeline. Therefore, for all types of instructions, a mode of an instruction processing control method (advance-off) of a complete sequential processing type that controls so that only one instruction is processed on the pipeline without prefetching the instruction, Further, as disclosed in Japanese Patent Laid-Open No. 63-240634 and Japanese Patent Laid-Open No. 2-100138, a command or a command sequence of a specific type is not prefetched, and the specific command or command is not performed. Instruction sequential control type instruction processing control system (instruction advance control) that controls not to supply the subsequent instruction until the pipeline processing of the column is completed. The mode of) has been achieved by the provision.

[0005]

In the logic fraud avoidance method in the above-mentioned conventional information processing apparatus, both the complete preprocessing control method and the instruction prefetch control method of the instruction sequential processing type, all in processing, or a specific type. The subsequent instructions of all types are not supplied to the instruction processing pipeline until the processing of the instruction is completed. Therefore, when the mode is set to the conventional advance-off or instruction advance-off mode, the processing performance is significantly reduced.

There are certainly cases where the logic illegality cannot be avoided unless the mode is set to the conventional advance-off or instruction advance-off mode. However, depending on the content of the logic illegality, only when the succeeding instruction is an instruction of a certain type, There is also a case where a logic error occurs by supplying the subsequent instruction to the instruction processing pipeline before the processing of the preceding instruction is completed.

In this case, in reality, if the subsequent instruction is an instruction of a type that does not cause logical injustice, it is possible to supply the subsequent instruction to the instruction processing pipeline, but the conventional advance-off or instruction When the advanced-off mode is set, no matter what type of subsequent instruction the subsequent instruction can be supplied to the instruction processing pipeline unless all of the preceding processing or an instruction of a certain specific type is completed. Therefore, there is a problem that the performance is deteriorated more than necessary.

Furthermore, when the advance-off or instruction advance-off mode in the conventional logic fraud avoidance method is used during hardware evaluation, undetected logic fraud (bug).
However, there is a problem that it is covered up and evaluation is missed.

For example, it is assumed that the designer finds during the evaluation that the processing logic of the type B has a logic error when the pipeline execution of the type B instruction is started during the processing of the instruction type A instruction. When avoiding this logic fraud and continuing the evaluation,
Instructions of type B are registered and instruction advance off is performed. In this case, in the conventional hardware operation of instruction advancing off, while the instruction of type B is being processed on the pipeline, the supply of all subsequent instructions to the pipeline is interrupted, and the instruction processing of type B is completed. After waiting, the supply of subsequent instructions to the pipeline will start. Therefore, if there is a logic illegality different from the above-mentioned logic illegality when the designer starts the execution of the type C as an undiscovered logic illegality, the logic illegality is found hidden. There is a problem that is delayed.

An object of the present invention is to provide an information processing apparatus capable of avoiding performance degradation during execution of the advance-off mode, solving the problem that undiscovered logic illegality cannot be detected / evaluated, and improving debug efficiency. To do.

[0011]

An information processing apparatus according to a first aspect of the present invention is an information processing apparatus for performing an instruction execution pipeline process, the instruction supplying unit supplying an instruction to an instruction processing pipeline, and the instruction supplying unit. , An instruction supply control means for controlling the supply of instructions, an instruction processing means for performing pipeline processing of the instruction supplied from the instruction supply means, and one or a plurality of devices which can be set to store an arbitrary instruction. The first instruction storage means, the processing instruction storage means for storing the instruction being processed in the instruction processing means, the respective instructions stored in the first instruction storage means and the instruction supply means are supplied. A first comparing means for comparing an instruction with each other, and when any one of the comparison results in the first comparing means matches, the instruction supplying means to the instruction processing means The instruction supply means for interrupting the supply of the subsequent instruction and restarting the supply of the instruction to continue the pipeline processing after the processing in the instruction processing means is completed for all the instructions stored in the processing instruction storage means. And the instruction processing means.

An information processing apparatus according to the second invention is an information processing apparatus for executing instruction execution pipeline processing, and controls instruction supply means for supplying an instruction to the instruction processing pipeline and instruction supply to the instruction supply means. Instruction supply control means, instruction processing means for performing pipeline processing of the instruction supplied from the instruction supply means, and one or a plurality of first instruction storage means that can be set to store an arbitrary instruction. A processing instruction storing means for storing an instruction being processed in the instruction processing means, and a first instruction comparing each instruction stored in the first instruction storing means with an instruction supplied from the instruction supplying means. Comparing means, one or a plurality of second instruction storing means that can be set to store an arbitrary instruction, instructions stored in the second instruction storing means, and the processing. Second comparison means for comparing the respective instructions stored in the instruction storage means, any one of the comparison results in the first comparison means being coincident and the comparison result in the second comparison means If any of the above is coincident, the supply of the instruction from the instruction supply means to the instruction processing means is interrupted, the comparison result in the second comparison means is no longer coincident, and the instruction supply is restarted later to restart the pipeline. The instruction supply means and the instruction processing means are controlled so as to continue the processing.

An information processing apparatus according to a third aspect of the present invention is the information processing apparatus according to the second aspect, wherein the instruction processing control of the information processing apparatus of the first invention and the instruction processing control of the information processing apparatus of the second invention are performed. A control mode holding means capable of setting a switching designation and a selection means for performing a switching selection to one of the two instruction / command processing controls according to a value stored in the control mode holding means. There is.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a main part of a first embodiment of an information processing system of the invention.

The instruction supply circuit 10 is a circuit for supplying an instruction to be executed to the instruction processing circuit 30. The instruction supply circuit 10 stores an address in the main memory indicated by the instruction cache address stored in the F stage (instruction cache) register 301. The subsequent instruction is read. In the instruction supply circuit 10, the instruction supply control circuit 20 controls the instruction supply.

In the instruction processing circuit 30, during normal operation (advance-on mode), the instruction etched in the F stage is sent to the instruction processing circuit 30 at every clock cycle.
D stage (instruction decode), R stage (register read), A stage (operand address generation), B
Stage (operand data read), E stage (operand operation execution), W stage (execution result storage)
A series of pipeline processing up to is performed.

When the instruction advance-off mode is set, the type of the subsequent instruction which is not to be supplied to the instruction processing circuit 30 until the processing of all the instructions being processed in the instruction processing circuit 30 is completed is stored as an instruction storage. It is registered in any of the instruction storage registers 401 to 404 in the circuit 40 by initial setting. In the case of the present embodiment, it is possible to register up to four types of instructions.

The subsequent instructions supplied from the instruction supply circuit 10 are the comparators 51 to 51 in the subsequent instruction comparison circuit 50.
54, instruction storage registers 401-40
4 and the comparison result is O
It is sent to the R gate 55, and the logical sum of the four comparison results is output from the subsequent instruction comparison circuit 50 to the AND gate 80.

The subsequent instruction supplied from the instruction supply circuit 10 is also sent to the processing instruction holding circuit 60. The processing instruction holding circuit 60 is a circuit that registers the type of the instruction being processed on the instruction pipeline in the instruction processing circuit 30, and is registered in the processing instruction type holding registers 601b to 606b.
In the case of this embodiment, since the instruction processing pipeline in the instruction processing circuit 30 has six stages, six processing instruction holding registers are prepared.

The processing instruction holding registers 601 to 606 are composed of in-execution flags 601a to 606a and processing instruction type holding registers 601b to 606b, respectively. The value of the in-execution flag being 1 means that the instruction stored in the corresponding processing instruction holding register is being processed by the instruction processing circuit 30.

The processing instruction holding register control circuit 61 performs new registration and deregistration of processing instructions in the processing instruction holding registers 601 to 606. Instruction supply circuit 1
The subsequent instruction supplied from 0 to the instruction processing circuit 30 is also sent to the processing instruction holding register control circuit 61, and the processing instruction holding register control circuit 61 executes the in-execution flags 601a to 606.
A value 0 is searched from a, 1 is set to the first execution flag found, and the instruction type of the subsequent instruction is newly registered in the corresponding processing instruction type holding register.

When the pipeline processing up to the W stage in the instruction processing circuit 30 is completed, the type information of the processed instruction is sent from the instruction processing circuit 30 to the processing instruction holding register control circuit 61 to control the processing instruction holding register. In the circuit 61, the execution flag is set to 1 from the processing instruction holding registers 601 to 606, and the instruction type registered in the processing instruction type holding register matches the instruction type sent from the instruction processing circuit 30. The first execution flag in the processing instruction holding register found is reset to 0.

The outputs of the in-execution flags 601a to 606a are sent to the OR gate 70, and the OR gate 70 takes the logical sum of all the in-execution flags and outputs it to the AND gate 80. The output of 1 from the OR gate 70 indicates that there is an instruction being processed in the instruction processing circuit 30.

Output from OR gate 55 and OR gate 7
The output from 0 is ANDed by the AND gate 80 and sent to the instruction supply control circuit 20, the instruction processing circuit 30, and the processing instruction holding circuit 60. The fact that the output signal from the AND gate 80 is 1 means that the subsequent instruction supplied from the instruction supply circuit 10 is of the same type as the instruction stored in the instruction storage circuit 40 and is being processed by the instruction processing circuit 30. Indicates that there is a preceding instruction of.

In response to the output from the AND gate 80 being 1, the instruction processing circuit 30 does not store the supplied subsequent instruction in the D stage register 302, shuts off the instruction processing pipeline at the entrance, and supplies the instruction. The control circuit 20 controls the instruction supply circuit 10 so that the instruction is fetched to the same main memory address again.

Further, in response to the output from the AND gate 80 being 1, the processing instruction holding circuit 60
The processing instruction holding register control circuit 61 is the instruction supply circuit 10.
The subsequent instruction supplied from the processing instruction type holding register 6
01b to 606b are controlled not to be newly registered.

FIG. 5 is a time chart of instruction processing in the advance-on mode, which is the normal operation, and FIG.
In the configuration of FIG.
The following is a time chart for the case of registering in and setting to the advanced off mode.

In the case of FIG. 6, the instruction 3 of the succeeding instruction holds the fuetch address stored in the F stage register 301 until the processing of the instruction 1 and the instruction 2 of the preceding instruction in the instruction processing circuit 30 is completed. After the processing of the instruction 2 in the instruction processing circuit 30 is finished and there are no more instructions being processed in the instruction processing circuit 30, the processing of the instruction 3 is met again, and at the same time, the pipeline processing is also performed for the instruction 4 and subsequent instructions that follow. Since the execution of the instruction 4 is not continued until the end of the instruction 3 as in the conventional case, performance degradation is prevented, and detection / evaluation of undiscovered logical illegality after the instruction 4 may not be possible. Disappear.

FIG. 2 is a block diagram showing a main part of a second embodiment of the information processing system of the invention.

The second embodiment of FIG. 2 has a configuration in which an instruction storage circuit 90 and a processing instruction comparison circuit 100 are added to the first embodiment of FIG.

The instruction storage circuit 90 is an instruction storage register 90.
1 to 904, it is possible to register four instruction types by initial setting.

The detailed logic of the processing instruction comparison circuit 100 is shown in FIG.
Shown in.

The comparators 1001 to 1004 respectively compare the processing instruction type holding register 601b with the instruction types stored in the instruction storage registers 901 to 904, and output the comparison result to the OR gate 1005. OR gate 1
005 takes the logical sum of these four comparison results and outputs it to the AND gate 1006. The AND gate 1006 takes the logical product of the above-mentioned logical sum and the output of the in-execution flag 601a and outputs it to the OR gate 70. The output of 1 from the AND gate 1006 indicates that the instruction of which the type is registered in the instruction storage circuit 90 is being executed by the instruction processing circuit 30.

The processing instruction comparison circuit 100 has a total of six circuits having the same configuration as the above-mentioned circuits. In each circuit, the instructions registered in the processing instruction type holding registers 601b to 606b are the same as the instruction storage register 901. .. to 904, and whether or not they match the type of the instruction registered, and the output results of the AND gate 1006,
1016, 1026, 1036, 1046 and 105
The logical product of the output of 6 and the output of the subsequent instruction comparison circuit 50 is ANDed, so that the output of the AND gate 80 has 1 because the instruction processing is performed when an instruction having the same instruction type as that registered in the instruction storage circuit 90 is processed. It is shown that the subsequent instruction being executed by the circuit 30 and supplied from the instruction supply circuit 10 is the same as the instruction type registered in the instruction storage circuit 40.

In response to the output from the AND gate 80 being 1, the instruction supply control circuit 20, the instruction processing circuit 30, and the processing instruction holding circuit 60 operate in the same manner as the embodiment of FIG.

FIG. 7 is a time chart when the instruction type of the instruction 2 is registered in the instruction storage register 901 and the instruction type of the instruction 4 is registered in the instruction storage register 401 in the configuration of FIG. Show. In this case, for the instruction 4, the processing of the instruction 4 is restarted immediately after the processing of the instruction 2 of the preceding instruction in the instruction processing circuit 30 is completed.

That is, in the first embodiment, the succeeding instruction is not input until after the completion of the pipeline processing of all the preceding instructions, but in the second embodiment, even the pipeline processing of the preceding specific instruction is completed. Then, the subsequent instruction can be immediately input, and the debugging efficiency can be further improved in a specific case as compared with the first embodiment.

FIG. 4 is a diagram showing the configuration of the processing instruction comparison circuit 110 and the advance-off mode register 120 in the essential parts of the third embodiment of the information processing system of the invention. The other configurations are the same as those of FIG. Is.

The internal logic of the processing instruction comparison circuit 110 is the same as that of the processing instruction comparison circuit 100 of FIG. 3 except for the portion shown in FIG.

The advance off mode register 120 is a 1-bit register whose value can be set by initial setting. When the value of the advance-off mode register 120 is set to 0, the selectors 1007 to 1057 select the outputs of the OR gates 1005 to 1055 to select the AND gate 1
Output to 006 to 1056. In this case, the processing instruction comparison circuit 110 operates in the same manner as the processing instruction comparison circuit 100 in FIG. 3, and the entire apparatus operates in the same manner as in FIG.

When the value of the advance off mode register 110 is set to 1, the selectors 1007 to 1057 select the output value 1 of the advance off mode register to select A.
ND gates 1006, 1016, 1026, 1036,
Output to 1046 and 1056. In this case, the values output from these AND gates to the OR gate 70 are equal to the values output from the in-execution flags 601a to 606a, respectively, and the operation of the entire apparatus is the same as that of FIG.

That is, in the third embodiment, the first
The debugging operation can be performed in multiple ways by switching between the operation according to the second embodiment and the operation according to the second embodiment.

[0044]

As described above, in the advance-off mode, the information processing apparatus of the first invention specifies a particular type of instruction until all the pipeline processing of instructions preceding the instruction is completed. By suspending the supply of the instruction of the type to the pipeline and performing the pipeline processing of the subsequent instruction including the instruction of the specific type immediately after the completion of all the pipeline processing of the preceding instruction,
This has the effect of improving the debugging efficiency.

Further, in the second invention, the first
Second of the instructions preceding the particular type of instruction
Supply of the instruction of the first specific type to the pipeline is suspended until the pipeline processing of the instruction of the specific type is finished, and immediately after the pipeline processing of the instruction of the second specific type is finished. By performing the pipeline processing of the subsequent instruction including the instruction of the specific type, it is possible to further improve the debugging efficiency as compared with the first invention.

The third aspect of the invention has the effect that the debugging operation can be performed in multiple ways by providing the function of switching between the first aspect and the second aspect.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a first embodiment of an information processing apparatus of the invention.

FIG. 2 is a block diagram showing a main part of a second embodiment of the information processing system of the invention.

FIG. 3 is a block diagram showing a processing instruction comparison circuit 100 of FIG.

FIG. 4 is a block diagram showing a processing instruction comparison circuit 110 and an advance off mode register 120 of a third embodiment of the information processing system of the invention.

FIG. 5 is a time chart of instruction processing in advance mode.

FIG. 6 is a time chart of instruction processing in the advance off mode according to the first embodiment.

FIG. 7 is a time chart of instruction processing in the advance off mode according to the second embodiment.

[Explanation of symbols]

10 Instruction Supply Circuit 20 Instruction Supply Control Circuit 30 Instruction Processing Circuit 40 Instruction Storage Circuit 50 Subsequent Instruction Comparison Circuits 51-54, 1001-1004, ..., 1041-10
44, 1051 to 1054 Comparator 55, 70, 1005, 1015, to 1045, 10
55 OR gate 60 Processing instruction holding circuit 61 Processing instruction holding register control circuit 80, 1006, 1016, ..., 1046, 1056
AND gate 90 Instruction storage circuit 100, 110 Processing instruction comparison circuit 120 Advance off mode register 301 F (instruction etch) stage register 302 D (instruction decode) stage register 303 R (register read) stage register 304 A (operand address generation) stage Register 305 B (operand data read) stage register 306 W (execution result storage) stage register 401-401, 901-904 Instruction storage register 601-606 Processing instruction holding register 601a-606a Execution flag 601b-606b Processing instruction type holding register 1007 , 1017, ~, 1047, 1057 Selector

Claims (3)

[Claims] 1. An information processing apparatus for performing instruction execution pipeline processing, comprising: an instruction supply means for supplying an instruction to an instruction processing pipeline; and an instruction supply control means for controlling instruction supply to the instruction supply means. Instruction processing means for performing pipeline processing of the instruction supplied from the instruction supply means, one or a plurality of first instruction storage means that can be set to store an arbitrary instruction, and processing in the instruction processing means Processing instruction storage means for storing the instruction in
Any of the comparison results in the first comparison means, which has a first comparison means for comparing each instruction stored in the first instruction storage means with the instruction supplied from the instruction supply means. If the values match, the supply of the instruction from the instruction supply means to the instruction processing means is interrupted, and after all the instructions stored in the processing instruction storage means have been processed by the instruction processing means, An information processing apparatus, characterized in that the instruction supply means and the instruction processing means are controlled so as to restart supply and continue pipeline processing. 2. An information processing apparatus for executing instruction execution pipeline processing, comprising: an instruction supply means for supplying an instruction to the instruction processing pipeline; and an instruction supply control means for controlling instruction supply to the instruction supply means. Instruction processing means for performing pipeline processing of the instruction supplied from the instruction supply means, one or a plurality of first instruction storage means that can be set to store an arbitrary instruction, and processing in the instruction processing means Processing instruction storage means for storing the instruction in
First comparison means for comparing each instruction stored in the first instruction storage means with the instruction supplied from the instruction supply means, and one or a plurality of which can be set to store an arbitrary instruction Second instruction storage means, and the second
Of the comparison result in the first comparison means, the second comparison means for comparing the instruction stored in the instruction storage means with the respective instructions stored in the processing instruction storage means. And if any of the comparison results in the second comparing means match, the supply of the instruction from the instruction supplying means to the instruction processing means is interrupted and the comparison result in the second comparing means is matched. An information processing apparatus, characterized in that the instruction supply means and the instruction processing means are controlled so that instruction supply is resumed and pipeline processing is continued after there is nothing left to do. 3. A control mode holding means capable of setting switching designation between the instruction processing control of the information processing apparatus according to claim 1 and the instruction processing control of the information processing apparatus according to claim 2, and the control mode holding means. 3. The information processing apparatus according to claim 2, further comprising a selection unit that performs switching selection to one of the two instruction / command processing controls according to the stored value.