JPH03250221A - Branch predicting system - Google Patents

Abstract

PURPOSE:To improve the performance of calculation by defining the updating condition of a branch predicting table when the condition of a condition branching instruction is established and the branching destination is on the back of the instruction itself. CONSTITUTION:When the contents of an address branching instruction address (BIA) 1001 as a second instruction are coincident at time t2, an instruction address selector (IASEL) 105 sends the contents of a branching destination address (BTA) 1002 to an instruction address register (IAR) 106 as the address to be next read and in order to calculate the address to be next read, the contents are sent to an incrementer (INC) 104 as well. Further, for recovery in the case of failing prediction, the contents [(a)+4] of a program counter (PC) 103 are saved in a saving register (PCS) 108. In such a manner, reading is started from an predicted branching destination address (b) at time t3 and reading occurs from an address (b+4) at time t4. When the condition is established as the executed result of the second instruction at the time t4 and it is confirmed that branching occurs, the prediction is made successful. Thus, the condition branching is executed without useless waiting time and the performance of a computer is improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a branch processing method in pipeline computers that execute machine instructions by dividing them into multiple stages, and is particularly applicable to l-chip microprocessors that cannot have many branch prediction tables. Regarding speeding up branch processing.

[Conventional technology]

In a pipeline computer, one machine instruction is divided into multiple stages such as instruction reading, decoding, calculation, and writing, and is executed in a flow-like manner to reduce processing time. For this reason, pipeline computers can execute consecutive instructions at high speed, but when a branch instruction occurs, the pipeline stage must be canceled and execution must be restarted from the instruction loading, which is a factor in reducing performance. Among 0-branch instructions, unconditional branch instructions are known in advance to take a branch, so the instruction can be read as soon as the branch destination address is calculated, but for conditional branch instructions, the condition is satisfied based on the operation result. If one condition is not satisfied, the instruction at the next address is executed without branching. Therefore, branch processing cannot be started until the condition is determined based on the calculation result.

Therefore, when the conditions are met, the performance deteriorates significantly.

Therefore, a method called one-branch prediction was devised to speed up conditional branching. Regarding the branch prediction method, please refer to i.
E.E., Computer, (January 1984)
Pages 6 to 22 (IEEE.

COMPUTER, (Jan, 1984) p p 6
-22).

In the conventional branch prediction method, branch instruction address 4 branch destination address 9
A branch prediction table with three fields of branch prediction judgment bits has tens to hundreds of entries, and when the address of the branch instruction being executed matches the branch instruction address in the table, the branch prediction judgment bit field is Depending on the state, it is predicted whether or not to branch. If one branch is predicted, the instruction is read from the branch destination address in the table without waiting for the condition to be satisfied, so if the prediction is successful, the branch is executed. The one-branch prediction determination bit, which alleviates the performance deterioration associated with this and improves the processing performance as a whole, is determined by whether or not a branch was taken in the past.

[Problem to be solved by the invention]

The above-mentioned conventional technology is based on the premise that performance is improved by having a one-branch prediction table with tens to hundreds of entries and registering as many one-conditional branch instructions as possible in the table. For this reason, there is a problem in that when the number of entries in the table cannot be increased as in the case of a 1-chip microprocessor, it is not possible to expect much improvement in performance.

An object of the present invention is to provide a branch prediction method that is effective even when the number of entries in a single branch prediction table is small, and is particularly suitable for a 1-chip microprocessor.

[Means to solve the problem]

Branch prediction works most effectively to achieve the above objective. Conditional branch instructions forming the loop portion of the program may be registered preferentially in the branch prediction table. Therefore, the table registration condition is that the branch destination address is after the branch instruction address.

[Effect]

In the loop part of the program, the conditional branch instruction for determining the end of the loop is at the end of the loop, that is, at the higher address side.
If the condition is satisfied, the process branches backward, that is, to the lower address side. If no other conditional branch instructions appear in the loop, you can simply register the conditional branch instruction, but for example, if there is a conditional statement (IF statement, etc.) in the loop, the conditional branch instruction for that conditional statement will be registered in the table. If the 0 branch destination address is after the branch instruction address is set as a table registration condition, the conditional branch instruction for loop termination may not be registered in the table. Conditional branch instructions are not registered in the table, but conditional branch instructions for loop termination are registered.

〔Example〕

Hereinafter, five embodiments of the present invention will be explained with reference to FIGS. 1 to 11.

FIG. 1 shows the basic structure of an embodiment of the present invention.
A pipeline computer that performs branch prediction includes a branch prediction table (BPT) 100 and a branch prediction table registration selector (
BPSEL) 101, program counter comparator (
GOMP) 102, program counter incrementer (INC) 103. Program counter (PC) 10
4, instruction address selector (IASEL) 105. Instruction address register (IAR) 106, instruction cache (IC) 107, program counter save register (
PC5)108. Instruction code unit (DEC) 200
．． The main component is an instruction execution unit (EXEC) 300. A branch prediction table (BPT) 100 includes branch instruction addresses (BIA) 1001. Branch destination address (BT
A) Contains 1001. Branch prediction table registration selector (BPSEL) 101 includes a program counter buffer (PCB) 1011. Instruction decode unit (D
EC) 200 is a control signal (CONTROL) 201
, displacement minus signal (DISPM) 2
02, including a conditional branch instruction determination signal (BCC) 203.

The instruction execution unit (EXEC) 300 includes an arithmetic logic operation (ALU) 301 and a condition code generation unit (COND).
302 included.

IC107 according to the address that is the content of IAR106
The instructions read from the C
Control EXEC300 from 0NTR0L201 d,
EXEC 300 performs a predetermined operation, PC 104 holds the address of the next instruction to be read, and
lO3 increments the contents of PCI04 according to the word length of the instruction. C0NP102 is PC104 and BIA
looI, and if they match, the contents of BTA 1002 are sent to IASEL 105.

IASEL 105 receives signals 204 and E from DEC 200.
Based on the signal 303 from XEC300 and the signal 1021 from C0NP102, PC104, PC5108,
BTA1021, ALU301 output ALUOUT
305 and sends it to IAR106. At that time, if BTA1021 is selected, BTA10
The contents of PC 103 are sent to INClO4 and the contents of PC 103 are saved to PC 5108. PCBIOII is PC
104 and sends the content to BPTloo at the timing of BPTloo update. B.P.
SELLOL is condition fulfillment signal 3 from C0ND302
DISPM202 and BCC from 04 and DEC200
The contents of PCBIOII and ALU30 depend on the contents of 203.
Branch destination address (ALUOUT305) which is the output of 1
BIAlooI and BTA in BPTloo respectively
1002.

FIG. 2 is a timing chart showing the basic operation of the computer including branch prediction described in this embodiment.

From to to t8 represents a time series, and one time (timing) corresponds to one machine cycle. One command is PC
, IF, D, E, and W pipeline stages. In the PC stage, the PC 104 is incremented and the address of the next instruction to be read is calculated. In this embodiment, the instruction length is fixed at 4 bytes. PC
After the end of the stage, that is, at the same timing as the IF stage, the comparison between BIAlooI and PC104 is C0NP102.
carried out by. If both match, IASEL1
05 sends the contents of BTA10002 to IAR, and next execution starts from the predicted address. If they do not match, PCl is incremented normally.
, 04 are used. At the IF stage, instructions are read from the IC 107 according to the address determined at the PC stage. In the D stage, the read instruction is decoded and EXEC
In this embodiment, branch prediction is performed when the branch destination of a conditional branch instruction is only a program counter relative address, that is, when the branch destination address can be determined statically. Therefore, the displacement minus signal D indicating that the branch destination is backward
The NSPM 202 only needs to look at specific bits of the operands in the instruction, and can make a decision at the D stage. In addition, since whether it is a conditional branch instruction or not can be determined by a combination of specific bits of the opcode in the instruction, the conditional branch instruction determination signal BC
C203 can be determined at the D stage.

The BCC 203 can also be used to limit the types of instructions that perform branch prediction. In the E stage, the EXEC 300 executes the operation instructed in the D stage. In the 6W stage, the result obtained by the execution of the E stage is written back to a register or the like.

FIG. 2 shows a case where the first instruction is a condition generation instruction and the second instruction is a conditional branch instruction. Assume that the address of the first instruction is address a-4 and that it is calculated at time 10. time t
1, reading of the first instruction and calculation of the address of the second instruction are performed. At time t2, the first instruction is decoded, the second instruction is read, and the address of the third instruction is calculated. Similarly below.

Unless control is disrupted due to branching, etc., each instruction flows according to the pipeline stage. In this case, it is assumed that the address (a) of the second instruction does not match BIAlooI.

If the result (condition) of the first instruction calculated at time t3 satisfies the condition of the second instruction (conditional branch instruction) at time t4, the process branches to the address indicated by the second instruction. The branch destination address is calculated at time t4, so 1 time t
Instructions are read from step 5. When it is determined that a branch will occur at time t4, execution is canceled midway since the third and fourth instructions have already been read. After time t5, instructions flow according to the pipeline stages unless a branch occurs again.In this way, if branch prediction does not work, if a condition is met with a conditional branch instruction,
Two cycles of idle time occur.

When it is known that a branch will occur at time t4, it is known at the D stage of the second instruction, that is, at time t3, whether the branch destination is after the own instruction (a < b), so
If the branch destination is after the own instruction, the address (a) of the second instruction and the branch destination address (b) are transferred to BPTl at time t5.
Register on oo. That is, the condition fulfillment signal 304 is at time t4.
If output with .

BPSELIOI is set to P according to BCC203 and DISPM202 output at the previous timing (time t3).
The contents of CBIOII are transferred to BIAlooI at time t5, and A
Each LUOUT 305 is stored in the BTA 1002.

FIG. 3 shows a case where branch prediction is successful. As in FIG. 2, the first instruction is a condition generation instruction and the second instruction is a conditional branch instruction. At time t2, the address of the second instruction and B
Assume that the contents of IAlooI match. In this case, IA
The SEL 105 sends the contents of the BTA 1002 to the IAR 106 as the next address to read, and also sends it to the 1NClO4 to calculate the next address to read. Further, the content (a+4) of the PC 103 is saved to the PC 510g for recovery when prediction fails.

In this way, at time t3, reading starts from the predicted branch destination address (b), and at time t4, reading starts from the predicted branch destination address (b).
Reading occurs from +4. If it is confirmed that the condition is satisfied and a branch occurs as a result of the execution of the second instruction at time t4, the prediction is successful, and the conditional branch is executed without unnecessary waiting time, improving the performance of the computer. do.

FIG. 4 shows a case where branch prediction fails. As in FIG. 2, the first instruction is a condition generation instruction and the second instruction is a conditional branch instruction. Assume that the address of the second instruction and the contents of BIAlooI match at time t2 as in FIG. 3.

At time t2, reading starts from the predicted address (b). At time t3, reading occurs from address b+4. If it is found that the first condition is not satisfied as a result of the execution of the second instruction at time t4 and the instruction at address a+4 should be executed, IASEL 105 returns the contents of PC 104 (b+s).
Instead, the saved content (a+4) of the PC 5108 is sent to the IAR 106 as the address to be read next. Third
and the fourth instruction is canceled. The contents of PC5108 are also sent to INClO4. In this way, when branch prediction fails, two cycles of idle time occur, similar to when 5-branch prediction does not work. If branch prediction fails frequently, more free time is wasted, and in the worst case, the performance of the computer decreases, but generally the loop portion where branch prediction is performed is executed many times, so there is a higher possibility that branch prediction will succeed. Therefore, branch prediction improves computer performance on average.

FIG. 5 shows BPTloo and BPSE in this example.
This shows the details of LIOI. Valid bit (V) 1003 in BPT 100 indicates whether the data in the branch prediction table is valid. V6O13 is the reset signal li! at reset time! Cleared by 1004. Furthermore, if the instruction address is a logical address in a computer that supports virtual memory, it is also cleared by process switching. However, in this case, if BIAlooI holds the process number as part of the address, there is no need to clear V6O13.

PCBIOII in BPSELIOI is latch 1011
, 1012°1013. These latches are 1
In the case of the embodiment shown in FIG. 2, data is sent every cycle.

The data entered into PCBIOII at time t2 is at time t
5 is output. Latches 1012 and 1013 each have DISPM202. Holds the data of BCC203.

In the embodiment of FIG. 2, the signal latched at time t3 becomes the conditional branch established signal 304 and the AND gate 10 at time t4.
14 results in a branch prediction table registration signal (BPTS) of 1.017.

BPTS1017 opens gates 1015.1016;
Send the contents of PCBIOIl and ALUOUT305 to BPTloo, respectively.

BPTS1017 is also used as a set signal for V6O13 to enable the branch prediction table.

Figure 6 shows the branch prediction table registration selector (BPSEL)
This is another example. This embodiment uses a displacement minus signal (DISP) when the branch destination of a conditional branch instruction is not only a program counter relative address but can be statically determined, for example, an absolute address.
M) is not known at the D stage. P
The output of CBIOII and the contents of ALUOUT 305 are subtracted by a subtracter (SOB) 101g to determine the magnitude relationship.

If it is determined that the content of ALUOUT 305 is smaller, a displacement minus signal 1019 is output. Other movements are the same as in the previous embodiment.

FIG. 7 is another embodiment of the branch prediction table (BPT) and program counter comparator (COMP). In this embodiment, the branch prediction table has four entries. 4
The table of entries is divided into two sets of two separated by a portion of the branch instruction address (PCB). A set determiner (SETI) 4 uses part of the address to determine which set an address is classified into.
Determined by 00. The replacement priority determiner (RE) determines which entry in one set should be registered.
PR) 500. REPR500 is
Replacement priority bit (R
The older entry is determined by P), and that entry is determined as the target to be registered, and the replacement priority bit is changed to invert the previous priority order. 5ET1400 and REPR500 determine one entry to be registered.

In the case of reading from the branch prediction table, a set determiner (SET2) 600 is used for the address (pc) to be compared.
A set is selected by , and two entries in one set are compared simultaneously by two comparators. By increasing the number of entries in the branch prediction table, more instructions can be registered, which increases the effect of branch prediction and further improves computer performance.

FIG. 8 shows a different embodiment from FIG. 7 of a branch prediction table (BPT) and a program counter comparator (COMP'). Which set an address is classified into is determined by the set determiner (SET3) 700 based on whether the branch destination is forward or backward using the displacement minus signal (DISPM) when reading from the 0 branch prediction table. In this case, the addresses (pc) to be compared are compared simultaneously by four comparators.

FIGS. 9 through 11 are program examples and flowcharts illustrating the effective use of embodiments of the present invention. For the program in Figure 9, the first
In instruction expansion as shown in Figure 0, that is, in expansion where the condition is judged only at the beginning of the loop and the end of the loop is an unconditional branch to the beginning of the loop, branch prediction does not work, so the effect of the present invention is not effective. It doesn't appear. In contrast, instruction expansion as shown in Figure 11, that is, condition judgment, is not only performed at the beginning of the loop.
Branch prediction works when the expansion is performed even at the end of the loop.
The effects of the present invention are evident. Therefore, in a computer system using the present invention.

A compiler that translates a computer language into machine language may perform expansion as shown in FIG. 11 for a program as shown in FIG. 9, rather than as shown in FIG. 10.

〔Effect of the invention〕

According to the present invention, branch prediction can reduce unnecessary idle time of conditional branch instructions, improving computer performance. In particular, even if there are only a few branch prediction tables, conditional branch instructions that make up a loop can be selected and registered in the table, making it possible to achieve the effect of branch prediction with less hardware.

According to the present invention, even if the branch prediction table has only one entry, for a program having a loop as shown in FIG. 12, the first conditional branch (1201) is not registered in the branch prediction table and the condition shown in FIG. Since only the branch (1202) is registered in the branch prediction table, the effect of branch prediction can be exhibited, but unless the restriction that the branch destination is backward is added, the first. Since both of the second conditional branches are registered in the branch prediction table, branch prediction fails and single branch prediction is not effective.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Figs. 2 to 4 are time charts of basic operations according to the embodiment of Fig. 1, and Fig. 5 is a detailed diagram of the elements in Fig. 1. Figure 6 is the 5th
Detailed view of another embodiment of the same part as in the figure, FIG.
Detailed view of another embodiment of the elements in the figures, FIG.
Detailed diagrams of the same parts as in the figure in another embodiment, Figures 9 to 11 are compiler expansion methods for effectively using the present invention, and Figure 12 is an explanatory diagram to show the effects of the present invention. It is. 100... Branch prediction table, 101... Branch prediction table registration selector, 102... Program counter comparator, 103... Program counter, 105...
...Instruction address selector, 200...Instruction decode Fig. 4 Fig. 5 Fig. 06 Fig. 9 Fig. 9 while 1e (a<b) begin Processing 1 Processing 1 Processing 1 LABEL2: Processing 2 Fig. 2 /”LABELLllllk branching rate/Figure/”a-b calculation $7

Claims (1)

[Scope of Claims] 1. In a pipeline computer that executes a machine instruction in multiple stages, one or more sets of a machine address of a conditional branch instruction and a branch destination machine address of the conditional branch instruction are held as a pair. When a branch instruction appears, it compares its machine address with the instruction machine address in the branch prediction table, and if they match, it starts reading instructions from the branch destination machine address in the branch prediction table. A branch prediction method, characterized in that the condition for updating the branch prediction table is set when a condition of a conditional branch instruction is satisfied and the branch destination is after the own instruction. 2. In claim 1, if the machine address of the branch instruction and the machine address of the instruction in the branch prediction table do not match, the processing of the instruction following the conditional branch instruction is prioritized over the processing of the branch destination instruction. branch prediction method. 3. In claim 1, if the machine address of the branch instruction and the instruction machine address in the branch prediction table do not match, if the branch destination of the branch instruction is after the own instruction, the branch destination instruction is Branch prediction that gives priority to the processing of the instruction following the conditional branch instruction, and if the branch destination of the branch instruction is not after the own instruction, the processing of the instruction following the conditional branch instruction is given priority over the processing of the branch destination instruction. method. 4. In claim 1, if the machine address of the branch instruction and the machine address of the instruction in the branch prediction table do not match, the processing of the branch destination instruction is given priority over the processing of the instruction following the conditional branch instruction. branch prediction method. 5. A branch prediction method according to claim 1, in which a partial combination of an opcode and an operand in an instruction is used as an update condition for a branch prediction table. 6. Has a set of branch prediction tables that store the machine address of a conditional branch instruction and the branch destination machine address of that conditional branch instruction as a pair, and when a branch instruction appears, the machine address and the instruction in the branch prediction table are In a computer that compares machine addresses and, if they match, starts reading instructions from the branch destination machine address in the branch prediction table, when executing a program that constitutes one loop, there are two or more conditional branches in the loop. instructions, two or more conditions are met and a branch occurs, and if there is only one conditional branch instruction whose branch destination is later than the own instruction, the branch destination is later than the own instruction. A branch prediction method characterized by registering a later conditional branch instruction in a branch prediction table. 7. A branch prediction method according to claim 1, in which a loop structure in a program is expanded by placing a conditional branch instruction used to determine a loop end condition at the end of the loop.