JPH0731724A - Random number generator - Google Patents

Abstract

PURPOSE:To decrease the burden on software by independently executing generation of random numbers by hardware separately form the software by a CPU. CONSTITUTION:This random number generator has a counter circuit 2 which consists of counters C1 to Cn, a set register 3 for setting the period of the count up of this counter circuit 2 and the upper limit value of the count up of each of the respective counters, a means 4 for outputting count operation signals, a means 5 for initializing the counter circuit which respectively initializes the values of the respective counters and a memory section 6 which has plural sets of memory regions 601 equal to the counter circuit 2. The values of the respective counters in the counter circuit 2 are transferred and stored as random number data to and in the memory regions which are not in the memory state. The memory sequence of the random number is also stored therein. On the other hand, the generator is provided with a control circuit 7 which nullifies trigger signals and outputs the random number stored in the memory regions in order of the older memory sequence in a means for storing the random number memory sequence every time a reading out signal is received.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a random number generator which is attached to a control means having a built-in CPU and outputs a random number to the control means.

[0002]

2. Description of the Related Art Conventionally, it has been widely known that a random number is used to determine a game operation in, for example, a pachinko game machine, but a CPU (Central Processing Unit) executes it as a means for obtaining the random number. As a random number generation process by software, the value of the specific storage area is incremented at regular intervals, and when the trigger signal is detected, the value of the specific storage area is read and used as a random number.

However, in the case where all the random number generation is processed by software by the CPU, the C
The PU performs a plurality of processes other than the random number generation process, and if there is a constraint that the random number generation process for one cycle must be completed within the specific time, the random number that can be generated within the specific time There is a limit to the range of numbers and random numbers.

When the random number generation range is large or a plurality of random number values are required at the same time, the CPU
Including a random number generation process in a series of processes by means of system design is difficult.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide a random number generation device capable of reducing the load on software by generating random numbers by hardware independently of software by a CPU. To do.

[0006]

In order to solve the above-mentioned problems, the random number generator of the present invention has each counter having a bit width corresponding to the required number of each random number and the generation range of each random number. And a setting register for setting the count-up period of the counter circuit and the upper limit value of the count-up for each counter, and the count-up of the counter circuit based on the set period in the setting register. Count operation signal output means for outputting a signal for performing an operation, and a count for initializing the value of each counter based on the set upper limit value corresponding to each counter of the count circuit set in the setting register Circuit initialization means, a storage section having a plurality of sets of storage areas equivalent to the counter circuit, and A random number storage order storage unit that determines the storage state of each storage area in the storage unit, transfers and stores the value of each counter in the counter circuit as random number data in a storage area that is not in the storage state, and stores the storage order of the random number data. While storing the storage order of the random number data in, while all storage areas of the storage unit is in the storage state, the trigger signal is invalidated, and each time the read signal is received, in the random number storage order storage means. A control circuit for outputting the stored random number data from the storage area in the storage state of the storage unit in the order of the oldest storage order.

[0007]

The count operation signal output means outputs a signal for performing the count-up operation of the counter circuit based on the set cycle which defines the count-up cycle of the counter circuit in the setting register, and the counter circuit counts. Upon receiving a signal from the operation signal output means, each counter having a bit width corresponding to the number of required random numbers and a generation range of each random number is counted up. On the other hand, the count circuit initialization means initializes the value of each counter based on the set upper limit value corresponding to each counter of the count circuit set in the setting register.

Each time the control circuit receives the trigger signal,
The storage state of each storage area in the storage unit including a plurality of storage areas equivalent to the counter circuit is determined, and the value of each counter in the counter circuit is transferred and stored as random number data in the storage area that is not in the storage state. While the storage order of the random number data is stored in the storage order storage means, the trigger signal is invalidated when all the storage areas of the storage section are in the storage state.

When the control circuit receives the read signal, the control circuit outputs the random number data stored in the storage areas in the storage state of the storage unit in the order of the oldest storage order in the random number storage order storage means.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of essential parts of a random number generator according to the present invention. The random number generation device 1 is roughly composed of a counter circuit 2 including a plurality of counters, a setting register 3 for setting a count-up period of the counter circuit 2, and a count-up upper limit value of each counter, and a setting register 3.
Based on the set value in, the count operation signal output means including the frequency divider 4 for dividing the clock signal from the outside to generate the count-up operation signal and outputting it to the counter circuit 2 and the setting register 3 are set. A comparator 5 that compares the set upper limit value corresponding to each counter of the count circuit 2 with the count value of each counter, and outputs a clear signal that sets the value of the counter whose count value has reached the set upper limit value to 0 in the comparison result. And a storage area 6-1 to 6-k equivalent to the counter circuit 2.
A storage unit 6 including a plurality of sets, a setting register 3, a counter circuit, according to input of a write signal (hereinafter referred to as a WR signal), a data read signal (hereinafter referred to as an RD signal) and a trigger signal from the outside of the device 2 and a control circuit 7 for controlling the data input / output operation of the storage unit 6.

Each of the counter circuit 2, the storage unit 6 and the setting register 3 is connected to a data bus 8 for data input / output, and data is input / output to / from the outside of the device via a bidirectional buffer 9.

The counter circuit 2 has a required number N of random numbers.
, N sets of counters are provided corresponding to each of the above, and each counter has a bit width m corresponding to the generation range of each random number. For example, if the number of required random numbers is nine, there are nine counters and the range of required random numbers is 0-16.
If so, it is composed of 5 bits.

The setting register 3 comprises a setting code for setting the count-up cycle of the counter circuit 2 and each register for setting the upper limit value of the count-up for each counter in the count circuit 2.

The storage unit 6 has a storage area of the same size as the counter circuit 2 and k sets of storage areas 6-1 to 6-k are set. Each storage area 6-1 of the storage unit 6
To 6-k, the count values of the n sets of counters in the counter circuit 2 are stored as random number data in any of the storage areas 6-1 to 6-k that are not in the storage state.

The data bus 8 is a transmission path for inputting / outputting data to / from the outside of the apparatus, and transfers random number data to each storage area in the counter circuit 2 and the storage unit 6 and to a setting register from the outside. The set value and the data input for setting the upper limit value of each counter in the counter circuit 2 and the random number data output to the outside of the random number data stored in each of the storage areas 6-1 to 6-k of the storage unit 2 are the data. It takes place via the bus 8.

The bidirectional buffer 9 is set to be valid for input by the control circuit 7 when data is input, valid for output when data is output, and invalid for input / output when data is not input or output. It

A CPU (not shown) supplies the WR signal, the RD signal, the trigger signal, and the clock signal, the setting data for setting the setting register, and the random number data in the storage area of the storage unit 6. To do.

FIG. 2 is a block diagram showing the signal system of the control circuit 7 and the storage unit 6. As shown in FIG. 2, the control circuit 7 generally includes a data writing / reading control circuit 11 for receiving and writing a signal from an external CPU and a selection signal 1 depending on the value of an address signal. To the address decoder 12 that outputs 5 to 5, and the random number data of m bits n sets output from the counter circuit 2 to the storage unit 6 is written in any of the storage areas 6-1 to 6-k of the storage unit 6, Alternatively, the storage areas 6-1 to 6-
and a random number writing / reading control circuit 20 for reading the random number data stored in any one of k.

Further, the control circuit 7 includes a read counter 13 that is incremented by 1 when reading the random number data stored in the random number storage order storage means, that is, the random number data stored in the storage unit 6, and a count circuit for the storage unit 6. Write counter 14 and write counter 1 that are incremented by 1 when writing random number data from 2.
Subtractor 15 that subtracts the data from the read counter 13 from the data from 4 and outputs the subtraction result
The output buffer 18 for outputting the subtraction result from the data bus 8 to the data bus 8, the subtraction result from the subtracter 15 and the maximum value held in the maximum storage number setting register 19 are compared, and the subtraction result is the maximum in the comparison result. When the value is smaller than the value, the input permission signal is output to the trigger buffer 17, while when the subtraction result is equal to or larger than the maximum value, the input permission signal is input from the comparator 16 and the comparator 16 which output the input inhibition signal to the trigger buffer 17. If
A random number write signal and a write counter + 1 signal are output to the random number write control circuit 20 and the write counter 14 in accordance with a trigger signal from the outside, and the maximum value used by the trigger buffer 17 and the comparator 16 is stored and held. The maximum storage number setting register 19 for

The data write / read control circuit 11 is a CPU
Random number write / read circuit 2 according to the CE signal and the RD signal
0, a maximum storage number setting register 19, a frequency division ratio setting register 21 and a maximum value setting register 22 shown in FIG.
The read signal is output to the output buffer 18. At the same time, the direction control signal is validated on the output side to the bidirectional buffer 9, and the counter + 1 signal is output to the read counter 13.

Further, the data write / read control circuit 11 is
A write signal is output to the maximum storage number setting register 19, the division ratio setting register 21 and the maximum value setting register 22 shown in FIG. 3 according to the CE signal and the WR signal from the CPU,
At the same time, the direction control signal for the bidirectional buffer 9 is validated on the input side. Further, the data write / read control circuit 11
Disables the input / output of the direction control signal to / from the bidirectional buffer 9 when there is no CE signal, RD signal, or WR signal from the CPU.

The CE signal is a chip enable signal, and includes a random number writing / reading circuit 20, a maximum memory number setting register 19, a frequency division ratio setting register 21 and a maximum value setting register 22 shown in FIG. 3, an output buffer. This is a signal for designating any of the eighteen.

The count-up values of the write counter 14 and the read counter 13 shown in FIG.
Since the number of sets of storage areas that make up the storage area, that is, the storage unit 6 is composed of k sets of storage areas 6-1 to 6-k, it is automatically cleared to 0 at the time when it becomes k.

FIG. 3 is a block diagram showing a signal system of the setting register 3, frequency divider 4, comparator 5 and counter circuit 2 in FIG. Setting register 3 in FIG.
3, the frequency division ratio setting register 21 for setting the count-up cycle of the counter circuit 2 and the maximum value setting for setting the upper limit value of the count-up of each counter in the count circuit 2 are shown in FIG. It is composed of a register 22.

The frequency division ratio setting register 21 is composed of n sets of registers, and the respective frequency division ratios for setting the count-up cycle of the counter circuit 2 are set and held in the respective registers.

The maximum value setting register 22 is composed of n sets of registers having an m-bit width equivalent to that of the counter circuit 2, and sets and holds the respective upper limit values for counting up in the counters C1 to Cn used by the comparator 5.

The frequency divider 4 is composed of n sets of frequency dividers corresponding to the n sets of counters C1 to Cn in the counter circuit 2, and is externally input according to each division ratio in the division ratio setting register 21. The clock signal is divided and supplied to each of the counters C1 to Cn in the counter circuit 2.

The comparator 5 is composed of n sets of comparators having the same m-bit width as the counter circuit 2, and compares each upper limit value set in the maximum value setting register 22 with each counter C1 to Cn. As a result of the comparison, a clear signal that sets the count value to 0 is output to the counter whose count value is equal to or larger than the upper limit value.

The counter circuit includes the counters C1 to Cn.
The current count value of is output to each of the comparator 5 and the random number writing / reading control circuit 20 in FIG.

Next, the operation of the random number generator 1 will be described. In FIG. 2, when the power is turned on, the read counter 1
3 and the write counter 14 are automatically cleared to 0.

After that, when an address signal is input from a CPU (not shown), the address decoder 12 outputs any one of the selection signals 1 to 5 depending on the value of the address signal.

Next, when a data signal, a CE signal, and a WR signal are input from the CPU, the data writing / reading control circuit 11 outputs the direction control signal to the bidirectional buffer 9 as the input side is effective, and the maximum. Memory number setting register 19,
By outputting a write signal to the frequency division ratio setting register 21 and the maximum value setting register 22 shown in FIG. 3, the registers 19 and 2 designated by the selection signals 1 to 5 are output.
Data is written to either one of 1 and 22.

For example, when the maximum storage number setting register 19 is designated by the address signal, the address decoder 12 outputs the selection signal 1 to the maximum value storage register 19. Further, the data write / read control circuit 11 includes
When the CE signal and the WR signal are input, the write signal is output, and the bidirectional buffer 9 is enabled on the input side. Therefore, the setting data from the CPU is transferred to the bidirectional buffer 9.
The data is written to the maximum storage number setting register 19 via the data bus 8 via, and the initial setting to the maximum storage number setting register 19 for setting the number of storable storage areas in the storage unit 6 is completed. For example, if there are 10 storage areas in the storage unit 6, the maximum storage number setting register 1
When the initial setting value to 9 is 5, among the k sets of storage areas 6-1 to 6-k in the storage unit 6, the maximum number of storage areas in the storage state is 5.

After the writing to the maximum storage number setting register 19 is completed, the CE signal and the WR signal from the CPU are turned off, so that the data writing / reading control circuit 11 invalidates the input / output to / from the bidirectional buffer 9. Output the direction control signal and the input / output of data by the data bus 8 is prohibited.

Thereafter, the address signal, the data signal, the CE signal, and the WR signal are input from the CPU in the order of, for example, the frequency division ratio setting register 21 and the maximum value setting register 22, so that the address decoder 12 operates as an address decoder. The selection signal 4 or the selection signal 5 is output to the division ratio setting register 21 or the maximum value setting register 22 according to the value of the signal, and the data write / read control circuit 11 outputs the direction control signal and the write signal. The frequency division ratio setting register 21 or the maximum value setting register 22 is designated by, and the setting data to be written is sequentially written by corresponding to the designation made by the data writing / reading control circuit 11. After the initial setting to 21 and 22 is completed, the CE signal and the WR signal are turned off, so that Input and output of data between the data bus 8 is prohibited.

In FIG. 3, after the writing of the setting data to the frequency division ratio setting register 21 and the maximum value setting register 22 is completed, a clock signal is output from the CPU and input to the frequency divider 4. The frequency divider 4 divides the input clock signal by each frequency division ratio set in the frequency division ratio setting register 21, and each counter C1 in the counter circuit 2 is divided.
To cn, and increments the count value of each counter C1 to cn.

Further, the comparator 5 compares the respective upper limit values set in the maximum value setting register 22 with the respective counters C1 to Cn, and in the comparison result,
A clear signal is output to the counter whose count value is equal to or higher than the upper limit value, and the count value of the counter whose count value is equal to or higher than the upper limit value is set to zero.

When a trigger signal is output from the CPU,
The trigger signal is the trigger buffer 1 as shown in FIG.
Input to 7. After the power is turned on, the values of the write counter 14 and the read counter 13 are both 0, so the subtractor 15
Becomes 0, one of the outputs of the subtracter 15 is input to the comparator 16, and the other is output buffer 18
Has been entered in. Therefore, in the output buffer 18,
Since 0 is set and the comparison result by the comparator 16 has not reached the maximum value, the input enable signal is output from the comparator 16 and input to the trigger buffer 17.

When the trigger signal is first input after the power is turned on, the trigger buffer 17 is operated by the comparator 1
The random number write signal is output in response to the input permission signal and the trigger signal from 6, and one of the random number write signals is input to the random number write control circuit 20, and the other of the random number write signals is
The write counter + 1 signal is input to the write counter 14, and the value of the write counter 14 is incremented by one. The current value 1 of the write counter 14 is input as write position data to the random number write control circuit 20 and the subtractor 15.

When the random number write signal from the trigger buffer 17 is input, the random number write / read control circuit 20 stores the random number write / read control circuit 20 in the storage area of the storage unit 6 designated by the value 1 of the write position data of the write counter 14. That is, in this case, the storage area 6-1
Then, each of the m-bit and n-group count values sent from the counter circuit 2 is written as random number data.

The current value 1 of the write counter 14 input to the subtractor 15 is compared with the current value 0 of the read counter 13, and the subtraction result becomes 1, and the result is input to the output buffer 18 and output buffer 18. The current value of 18 is updated to 1.

The subtraction result 1 of the subtractor 15 is also input to the comparator 16 and is compared with the maximum value held in the maximum storage number setting register 19 by the comparator 16 to reach the maximum value. If not, the input permission signal is continuously output to the trigger buffer 17.

After that, while the input permission signal is being input to the trigger buffer 17, the trigger buffer 17 outputs a random number write signal each time the trigger signal is input. 4 is output, the value of the write counter 14 is incremented by 1, and the write position of the random number data in the storage unit 6 is increased by 1 as shown by the solid arrow in FIG. The random number data sent from the counter circuit 2 is sequentially written and stored in and after the storage area 6b of the storage unit 6 designated by the insertion position data.

In FIG. 5, the storage area in the storage state is indicated by the diagonal lines. When the value of the write counter 14 reaches k, the value k is output and is cleared to 0 at the time when the random number is written in the storage area 6-k.

Whenever the trigger buffer 17 outputs a random number write signal, the value of the write counter 14 is incremented by one, but if the value of the read counter 13 remains 0, the subtracter The subtraction result in 15 increases by one, and the subtraction result of the subtracter 15 in the comparison result in the comparator 16 is the maximum storage number setting register 1
The maximum value held at 9 is reached. In this case, the comparator 16 outputs an input prohibition signal to the trigger buffer 17, and when the trigger buffer 17 inputs the input prohibition signal, it stops outputting the random number write signal even if the trigger signal is input. This prevents the random number data from being stored in the storage unit 6 even if the trigger signal is input.

As a result, the random number data is stored in the storage unit 6 up to the number corresponding to the value set in the maximum storage number setting register 19 under the storage area designated by the write position data. It will be.

Next, reading of random number data will be described. When the random number data is read, first, the CPU
The present value of the output buffer 18 is read by the address signal, CE signal, and RD signal. The CPU designates the output buffer 18 by the value of the address signal and outputs the CE signal and the RD signal. The output address signal is input to the address decoder 12, and the CE signal and the RD signal are input to the data write / read control circuit 11.

In response to this, the data write / read control circuit 11 outputs a read signal to the output buffer 18, and at the same time,
The bidirectional buffer 9 sets the direction control signal to be valid on the output side. Further, the address decoder 12 has a CE signal and an R signal.
The address signal is input substantially in synchronization with the D signal. The value of the address signal is a value corresponding to the output buffer 18, the address decoder 12 outputs the selection signal 2 to the output buffer 18, and the subtraction result of the subtracter 15 held and stored in the output buffer 18, that is, Data representing the difference between the number of times of writing random number data and the number of times of reading random number data, which is the value obtained by subtracting the value of the reading counter 13 from the value of the writing counter 14, is output from the output buffer 18 and passed through the data bus 8. , Is transmitted and received to and from the external CPU side via the bidirectional buffer 9. After that, since the CE signal and the RD signal from the CPU are turned off, the data write / read control circuit 11 outputs an input / output invalid direction control signal to the bidirectional buffer 9, and the data bus 8 outputs the data. I / O is prohibited.

When the value of the output buffer 18 is 0, since the number of written random number data is the same as the number of read random number data, the random number data is not stored.

When the value of the output buffer 18 is not 0, the number of written random number data exceeds the number of read random number data, so that the random number data is stored. The CPU side determines whether or not the value of the output buffer 18 is 0, and when the random number data is stored, the CPU side outputs a signal for reading the random number data.

Address signal, CE signal, R from CPU
The random number data in the storage unit 6 is read by the D signal. The storage area of the storage unit 6 read at this time is determined by the value of the read counter 13. The CPU designates the random number write / read control circuit 20 by the value of the address signal and outputs the CE signal and the RD signal. The output address signal is sent to the address decoder 12 by the CE signal and RD.
The signal is input to the data write / read control circuit 11.

In response to this, data write / read control circuit 11 outputs a read signal to random number write / read control circuit 20 and at the same time outputs a counter + 1 signal to read counter 13 and, at the same time, bidirectional buffer 9 Set the direction control signal to output side valid. Further, the address decoder 12 has
The address signal is input substantially in synchronization with the CE signal and the RD signal. The value of the address signal is a value corresponding to the random number write / read control circuit 20, and the address decoder 12 outputs the selection signal 3 to the random number write / read control circuit 20.

The counter + 1 signal from the data writing / reading control circuit 11 is input to the reading counter 13 and increments the value of the reading counter 13 by one, that is, in the case of the first reading after the power is turned on. 1 and the read counter 13
The current value 1 of is input to the random number write / read control circuit 20 as read position data.

The random number write / read control circuit 20 reads the read signal, the read position data from the read counter 13, and the selection signal 3.
By inputting and, random number data of m bits and n sets stored and held in the storage area of the storage unit 6 designated by the read position data is sent out onto the data bus 8. The random number data sent on the data bus 8 is sent and received to the CPU side via the bidirectional buffer 9. After that, since the CE signal and the RD signal from the CPU are turned off, the data write / read control circuit 11 outputs an input / output invalid direction control signal to the bidirectional buffer 9, and the data bus 8 outputs the data. I / O is prohibited.

The value of the read counter 13 which is incremented by the output of the read signal is input to the subtractor 15, and the value of the read counter 13 is subtracted from the value of the write counter 14, and the subtracter 15 subtracts the value. The result is input to the output buffer 18 and the comparator 16. While the subtraction result of the subtracter 15 input to the output buffer 18 does not become 0, that is, until the value of the read counter 13 reaches the value of the write counter 14, the random number data is read from the CPU. After that, every time the CE signal, the RD signal, and the address signal are input, the value of the read counter 13 is incremented by 1, and a random number is sequentially output from the storage area of the storage unit 6 designated by the read position data of the read counter 13. Data is sent out on the data bus 8.

Then, the write counter 1 by the subtractor 15
When the result of subtracting the value of the read counter 13 from the value of 4 becomes 0, the value held in the output buffer 18 becomes 0,
By reading this value 0 into the CPU, the CPU
Side determines that no random number data is stored, so C
The reading of the random number data by the E signal, the RD signal and the address signal is completed.

Each time a read signal from the storage section 6 based on the CE signal, the RD signal and the address signal is output from the data write / read control circuit 11, the value of the read counter 13 is incremented by +1.
By doing so, the reading position in the storage unit 6 is increased by one, as indicated by the dotted arrow in FIG.
In FIG. 5, the storage areas in the storage state, that is, the storage areas 6-3, 6-4, 6-5 are indicated by diagonal lines. Further, in FIG. 5, a storage area in which both a solid-line arrow indicating writing and a dotted-line arrow indicating reading are described, that is, the storage areas 6-1 and 6- where the reading is performed after the writing is performed. In No. 2, random number data is not stored.

Writing / reading operation of random number data is performed because the writing position always precedes the reading position and the number of writing operations is up to the value set by the maximum value setting register 19. As the difference between the number of read operations and the number of read operations does not exceed the set value of the maximum value setting register,
5, the read position designated by the read counter 13 is the oldest stored position in the storage area in the storage unit 6 in the storage state, for example, the write counter 14 in the example in FIG. The value is sequentially updated from 1 and writing to the storage areas 6-1 to 6-5 is completed, and the write position for the next writing is 6, that is, the storage area 6-6, while the read counter The value of 13 is updated from 1 and the reading is completed in the order of the storage area 6-1 and the storage area 6-2, and the storage area 6-3 is pointed to corresponding to the read position data 3 of this time.

As a result, the random number data stored in the storage section 6 is sequentially read out by updating the reading position designated by the reading counter 13 in the order of oldest writing order. The value of the read counter 13 is k
When it reaches, the value k is output and the value is cleared to 0 at the time when the random number data is read to the storage area 6-k.

Next, a usage example of the random number generator 1 will be described.

FIG. 6 shows a display unit 26 of a liquid crystal display device, which is composed of a total of nine symbol display units 26a to 26i which are vertically and horizontally partitioned. The nine symbol display portions 26a
To 26i, each of which has 17 kinds of symbols, has nine random numbers in order to make the symbols appearing in each of the symbol display parts 26a to 26i random, and the liquid crystal display device to a gaming board of a pachinko gaming machine not shown. A special winning opening (not shown) provided on the game board is set as a starting opening for the symbol variation in the liquid crystal display device, and a symbol starting switch SW1 is provided in the specific winning opening.

As shown in FIG. 7, as in the conventional case, the CPU 23 for controlling the respective parts of the pachinko gaming machine is configured to perform the symbol variation process and the drive process for the electric auditors not shown. The ROM 24 stores a program for controlling a liquid crystal display device (not shown) and each drive unit of a pachinko gaming machine and various data necessary for processing, and the RAM 25 is used for temporary storage of data. It

When the game ball wins the specific winning opening, the CPU 23 outputs a trigger signal, R
After the random number data from the random number generator 1 for the output of the D signal is input, the hit / miss determination in the pachinko game is performed by the combination of the symbols displayed on the respective display portions which are determined by the respective random number values. And

In the random number generator 1, the symbol display section 2
6a to 26i corresponding to the counting circuit 2 in FIG.
Of the counters C1 to Ci are set, and the maximum value of the count up of each of the counters C1 to Cn is set to a range of 0 to 16 and the value set in the maximum value setting register 22 in FIG. 3 is set to 16 respectively. To configure. Depending on the setting on the pachinko game, the maximum memory number setting register shown in FIG. 2 can be stored up to 5 including the number of start-ups related to the variation of the symbol due to winning at the specific winning opening, including during the symbol variation. The set value for 19 is set to 5.

After the power of the pachinko gaming machine is turned on, the CPU 23
The address signal, the data signal, the WR signal, and the clock signal are input to the random number generator 1 by the count circuit 2
Cycle of counting up and counters C1 to C
The upper limit value of the count up to i is set, and based on this, in the count circuit 2, the counters C1 to Ci are
Is counted up.

In the gaming board of the pachinko gaming machine, when a winning of a gaming ball occurs in a specific winning port, each symbol display portion 26a
From 26i to 26i, the fluctuation of the symbol is started. Also, every time a game ball is won in the specific winning opening, a trigger signal is input from the CPU 23 to the random number generator 1, and in the random number generator 1, the count circuit 2 is sequentially read from the storage area 6-1 in the storage unit 6. The random number data of is stored.

On the pachinko game board side, the CPU 23 carries out a process for confirming the symbol to be stopped and displayed on the symbol display portions 26a to 26i during the symbol fluctuation. An RD signal is output from the CPU 23 to the random number generator 1, and the random number generator 1 receives the RD signal and stores the random number data stored in the storage unit 6, that is, the symbol display units 26a to 26a in this example.
Nine random numbers (values from 0 to 16) for determining the symbols to be stopped and displayed on each of 6i are output via the data bus 8.

The CPU 23 of the pachinko gaming machine inputs this random number data, and the random number value of the random number data corresponding to each of the symbol display parts 26a to 26i causes the symbol display part 26 to be displayed.
The types of symbols to be stopped and displayed in each of a to 26i are sequentially determined, and the symbols are stopped and displayed in a predetermined order. Then, the symbols that are stopped and displayed are determined by a combination of random numbers, and each process of hit / miss is performed.

FIG. 8 is a block diagram showing an example in which the random number generating device 1 is applied to an automatic vending machine. The vending machine controller 27 includes a money insertion detector 30 and a plurality of product selection buttons. 29 is connected, and the control unit 27 individually detects the insertion of money and the pressing operation of each product selection button, and a trigger signal is output to the random number generator 1 by the insertion of money.

In addition, the control unit 27 has a hit display device 2
When 8 is connected and the random number data read from the random number generator 1 is a hit, the fact is displayed. Further, the control unit 27 stores and holds the hit determination number set for each of the product selection buttons 29a to 29i.

The number of sets of the counter circuit 2 shown in FIG. 1 is determined corresponding to the number of the plurality of product selection buttons 29a to 29i, that is, the counters C1 to Ci of the counter circuit 2 are set. Further, the upper limit value of the respective count-ups of the respective counters C1 to Cn is set to be smaller than the upper limit value of the counter corresponding to the product selection button of the product desired to be purchased a lot. For example, the upper limit of the count-up of the counter C1 corresponding to the product selection button 29a is set to 3, and the counters C2 to C corresponding to the remaining product selection buttons 29b to 29i.
The upper limit value of the count-up corresponding to i is all 10.

When coins are thrown in, the control section 27 outputs a trigger signal to the random number generator 1 to write random number data first, and then outputs an RD signal to write and store the random number. Read the data. The control unit 27 determines whether or not the hit determination number related to the product selection button that has been pressed this time and the random number value corresponding to the pressed product selection button of the read random number data are inconsistent. If there is a hit,
A hit is displayed on the hit display device 28, and the purchaser is given a value to the hit.

For example, when the merchandise selection button 29a is selected, there are four random numbers read from 0 to 3 and 11 random numbers from 0 to 10 related to other merchandise selection buttons. The probability of is high.

The random number generator of the present invention is, for example,
When a character is randomly moved in a puzzle game, or a trigger signal is generated by key operation, the display pattern in the screen display of a game or the operation of each part of the character is randomized according to each value of the random number stored at this time. Also, in a match-up game, when hitting an enemy etc., the enemy will detect with a sensor etc. and output a trigger signal, and each value of the stored random number data Can also be read later and used to determine the next enemy action.

[0075]

According to the random number generator of the present invention, a counter circuit including counters each having a bit width corresponding to the required number of random numbers and corresponding to the generation range of each random number, and a counter circuit for counting up. A setting register for setting the cycle and the upper limit value of the count-up for each counter, and a count operation signal output means for outputting a signal for performing the count-up operation of the counter circuit based on the set cycle in the setting register. And a plurality of sets of storage areas equivalent to the counter circuit and a count circuit initialization means for respectively initializing the value of each counter based on the set upper limit value corresponding to each counter of the count circuit set in the setting register. Storage unit that is not in the storage state, by determining the storage state of each storage area in the storage unit each time the trigger signal is received. The value of each counter in the counter circuit is transferred and stored as random number data, and the storage order of the random number data is stored in a random number storage order storage unit that stores the storage order of the random number data, while all storage areas of the storage section are in the storage state. In some cases, disable the trigger signal,
When the read signal is received, the random number data stored in the uppermost storage area in the storage unit is output, and each time the read signal is received, the random number storage order storage means is in the storage state in the storage unit in the oldest storage order. Since the control circuit for outputting the random number data stored in the storage area is provided, the random number is generated by hardware independent of the software executed by the CPU. Therefore, each process must be completed within a specific time in the software. With the restriction that the software must be used, the load on the software can be reduced, and the processing time for generating the reduced random number of this software can be used for other processing.

Further, the generation range of random numbers is large,
Even if multiple random number values are required at the same time and the number of combinations of each random number becomes huge and the random number generation process by software becomes difficult in design, the counter circuit can handle the required number of each random number. Moreover, since it has a bit width corresponding to the generation range of each random number, it is possible to generate a plurality of random numbers at the same time.

Further, since the count-up cycle of the count circuit in the setting register and the count-up upper limit value of each counter are externally changed,
The generated random number characteristic can be changed arbitrarily.

Furthermore, even when a plurality of external trigger signals are input, the random number values for the respective trigger signals can be stored respectively, and the random number storage order storage means ensures the writing order of the random number data. Since the random number data is stored, the random number data stored in the oldest order of the stored random number data can be transmitted at the time of reading the random number.

[Brief description of drawings]

FIG. 1 is a block diagram of essential parts of a random number generator according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a signal system of a control circuit and a storage unit.

FIG. 3 is a block diagram showing a signal system of a setting register, a frequency divider, a counter circuit, and a comparator.

FIG. 4 is a diagram showing a writing state of random number data in a storage unit.

FIG. 5 is a diagram showing a relationship between random number data stored in a storage unit and read random number data.

FIG. 6 is a front view showing a symbol display portion of the liquid crystal display device.

FIG. 7 is a block diagram showing an outline of a pachinko gaming machine equipped with the random number generation device of the present invention.

FIG. 8 is a block diagram schematically showing a vending machine equipped with the random number generation device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 random number generator 2 counter circuit 3 setting register 4 frequency divider 5 comparator 6 storage section 6-1 storage area 6-2 storage area 6-k storage area 7 control circuit 8 data bus 9 bidirectional buffer 11 data write / read control Circuit 12 Address decoder 13 Read counter 14 Write counter 15 Subtractor 16 Comparator 17 Trigger buffer 18 Output buffer 19 Maximum value setting register 20 Random number write / read control circuit 21 Dividing ratio setting register 22 Maximum value setting register 23 CPU (Pachinko game) 24) ROM 25 RAM 26 display unit 26a symbol display unit 26b symbol display unit 26c symbol display unit 26d symbol display unit 26e symbol display unit 26f symbol display unit 26g symbol display unit 26h symbol display unit 26i symbol display unit 27 control unit per 28 Display device 2 Product selection button 30 money-on detection unit C1 counter C2 counter C3 counter Cn counter

Claims (1)

[Claims] 1. A counter circuit comprising counters each having a bit width corresponding to the required number of random numbers and corresponding to the generation range of each random number, a count-up cycle of the counter circuit and a count for each counter. A setting register for setting an upper limit value of up, a count operation signal output means for outputting a signal for performing a count up operation of the counter circuit based on a setting cycle in the setting register, and the setting register A counter circuit initialization unit that initializes the value of each counter based on the set upper limit value corresponding to each counter of the counter circuit that is set to Each time the memory and the trigger signal are received,
A random number storage order memory that determines the storage state of each storage area in the storage unit, transfers and stores the value of each counter in the counter circuit as random number data in a storage area that is not in the storage state, and stores the storage order of the random number data. While storing the storage order of the random number data in the means, when all storage areas of the storage section are in the storage state, the trigger signal is invalidated, and the random number storage order storage means is received every time a read signal is received. And a control circuit for outputting the random number data stored in the storage area in the storage state of the storage unit in the order of the oldest storage order.