JPH07311707A - Memory access controller - Google Patents

Abstract

PURPOSE:To provide a memory access controller, which can operate fast while suppressing the power consumption, even for a ROM and a RAM. CONSTITUTION:The high-order address of an address outputted so as to access a ROM 102 by a CPU 101 is halved into 1st and 2nd address parts 11b and 11c. A circuit 105 generates chip-enable signals CE-N1 and CE-N2 on the basis of the 1st address part. A circuit 110 generates an output-enable signal OE-N on the basis of a read command from the CPU, the signal CE-N2, and the 2nd address part 111c. Consequently, the chip-enable signal is validated even in a specific address area other than a ROM address area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control device, and more particularly, it divides address information for generating a memory control signal into two parts, and a read-only read-only memory is used as the memory. The present invention relates to a memory access control device that can use a writable random access memory.

[0002]

2. Description of the Related Art Conventionally, as a memory control circuit (memory IC control circuit), for example, as disclosed in JP-A-4-109498, the pulse width of a chip select signal occupied during a memory cycle period is shortened. Therefore, a technique for reducing power consumption is known.

FIG. 9 is a block diagram of a memory IC control circuit disclosed in Japanese Patent Laid-Open No. 4-109498.

In FIG. 9, 901 is a central processing unit (hereinafter referred to as CPU), and 902 is a clock signal (CL
K), 903 is a CPU address, 904 is a read signal (READ), 905 is an address decoder (ADR),
Reference numeral 906 is an address signal (DEC), and 907 is a chip select signal (CS). 908 is a logic circuit (L
GC), 909 is an inverter (G1), 910 is an inverted C
LK, 911, 912 are flip-flops (FF1, F
F2), 913 are output data (Q1) of FF1, 914
Is output data (Q2) of FF2, 915 is an AND gate (G2), and 916 is a short chip select signal (CS).
1) and 917 are memories (MRY).

The general operation of the conventional memory access control circuit shown in FIG. 9 will be described below.

First, the clock signal (CLK) 902 is input to the inverter (G1) 909, and its inverted CLK9.
10 is a flip-flop (FF1) 911, (FF2)
It is applied to each clock terminal CL of 912. The chip select signal (CS) 907 is applied to the data terminal D of the flip-flop (FF1) 911, and the clock (CLK) 9
Data (Q1) 9 corresponding to the state of the chip select signal (CS) 907 applied to the data end D in synchronization with 02.
13 is output to the output terminal Q. Further, at the data terminal D of the flip-flop (FF2) 912, the data (Q1) 9 appearing at the output terminal Q of the flip-flop (FF1) 911.
13 is applied, and data (Q1) 913 corresponding to the state of the data terminal D is output to the output terminal Q as data (Q2) 914 in synchronization with the clock signal (CLK) 2. These chip select signal (CS) 907, data (Q
1) 913 and data (Q2) 914 are both AND gate (G2) 915 (because they are active-low input / output,
It is applied to the input end of a mere OR gate), the logical sum of these is calculated, and a short chip select signal (CS1) 916 is output from the output end of the memory (MRY) 917.
Is output to the chip select terminal (CS). These inverter (G1) 909, flip-flop (FF1,
FF2) 911 and 912, AND gate (G2) 915
A logic circuit (LGC) 908 is configured by the above.

Next, the operation of the embodiment configured as described above will be described with reference to the waveform chart shown in FIG.

FIG. 10A shows a clock signal (CLK) 9
02, (b) is a read signal (READ) 904,
(C) is the chip select signal (CS) 907, (d) is the data (Q1) 913, and (e) is the data (Q2) 91.
4 and (f) are short chip select signals (CS1) 916
Are shown respectively. Address decoder (ADR) 905 is CP
Read signal (READ) 904 from U901 (see FIG. 10).
(B)) is read, a chip select signal (CS) 907 (FIG. 10C) is created from this and an address signal (DEC) 906 composed of the CPU address 903, and this is generated at the data end of the flip-flop (FF1) 911. Output to D. The flip-flop (FF1) 911 synchronizes with the falling edge of the clock signal (CLK) 902 (FIG. 10A) and the chip select signal (CS) 907 (FIG. 10).
The state of (c)) is output to the output terminal Q as data (Q1) 913 (FIG. 10D). Further, the flip-flop (FF2) 912 synchronizes with the falling edge of the clock signal (CLK) 902 (FIG. 10A), and the data (Q1) 913 (FIG. 10) of the flip-flop (FF1) 911.
The state of (d)) is output to the output terminal Q as data (Q2) 914 (FIG. 10 (e)). And Gate (G2) 9
Reference numeral 15 is the chip select signal (CS) 907 (FIG. 10C), the data (Q1) 913 (FIG. 10D) of the flip-flop (FF1) 911, and the data (Q2) of the flip-flop (FF2) 912. 914 (FIG. 10)
(E)) is calculated and the short chip select signal (C) during the active low period t2 as shown in FIG.
S1) 916 is obtained and this is used as the chip select signal of the memory (MRY) 917. In this way, the chip select signal (CS1) having a short active low period t2
If 916 is used, current consumption can be significantly reduced.

[0009]

However, in the above-mentioned conventional technique, a special circuit such as the logic circuit 908 is required to generate the short chip select signal (CS1) 916, which increases the circuit scale and It is possible that the power consumption will increase. Also, the memory (MRY) 91
Although it is possible to reduce the power consumption of No. 7, no consideration is given to speeding up access. That is, as can be seen from FIG. 10, since CS1 which is actually given to the memory is outputted in the latter half of the CS signal output period, this conventional technique does not contribute to the speeding up of access.

Further, although the prior art corresponds to a read-only read-only memory (hereinafter referred to as a ROM), a writable random access memory (hereinafter referred to as a RAM) should be considered. Not done.

An object of the present invention is to provide a memory access control device for ROM and RAM that can operate at high speed while suppressing power consumption.

Another object of the present invention is to provide a memory access control device capable of suppressing the circuit scale and realizing power saving and high speed operation.

[0013]

In order to achieve the above object, a memory access control device according to the present invention includes at least a first control signal for enabling a memory chip, and a first control signal for enabling output of data. In an access control device for a memory having two control signal, address and data terminals, an upper address for selecting the memory from among the addresses from the central processing unit is a first address.
And a first control circuit unit that divides into a second address portion and generates the first control signal based on the first address portion, and a signal for instructing output of memory data from the central processing unit. An output signal of the first control circuit unit,
And a second control circuit section for generating the second control signal based on the second address portion.

In this device, the first control circuit unit is, for example, a decoder that decodes the first address portion, and the decoder unit by a latch clock generated immediately after the change of the address from the central processing unit. And a latch circuit that latches the output signal of.

A switching circuit unit for switching at least one bit of the upper address from inputting the one bit to the first control circuit unit or the second control circuit unit, and the switching circuit unit. And a register holding data for instructing switching of the above.

[0016]

The typical operation of the present invention is as follows.

That is, the upper address of the memory address output from the central processing unit (CPU) is the first address of the memory.
Control signal, such as a chip enable signal (hereinafter CE
-N) and a second control signal, for example, an output enable signal (OE-N), is divided into two and decoded to generate first and second control signals. With this configuration, the CE-N signal is also valid in a specific memory address area (speed-up address area) other than the area of the memory, and therefore, when the addresses in these address areas are continuously accessed, High-speed access is possible. At the same time, when accessing an address other than these address areas, the CE-N signal can be disabled so that power consumption can be reduced.

The position and size of the speed-up address area can be changed by changing the mode of dividing the upper address into two. Also, by making this switchable by software, speeding up and power saving can be selected according to the application.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment to which the present invention is applied.
It is a block diagram which shows the schematic structure of the information processing apparatus which used ROM for memory. In FIG. 1, 101 is a CPU, 1
02 is a ROM, 103 is a memory control circuit unit that controls the ROM 102, 104 is a CE-N1 signal for enabling the ROM 102 in the memory control circuit unit 103,
Reference numeral 105 denotes a generation circuit for generating the CE-N1 signal 104, 1
Reference numeral 06 is a holding circuit for the CE-N1 signal 104 (hereinafter referred to as a latch circuit), 107 is a latch clock for the latch circuit 106, and 108 is a latched CE-N1 signal (hereinafter, CE).
-N2 signal), 109 is an OE-N signal for outputting data from the ROM, and 110 is an OE-N signal 10
9 generation circuit, 111 CPU address, 112 CP
A read signal (hereinafter referred to as a read command) output from U101 and 113 indicate data output from the ROM 102, respectively.

The information processing apparatus according to this embodiment has the above-mentioned configuration, and in particular, a C for generating the CE-N2 signal 108 and the OE-N signal 109 for the ROM 102.
By dividing the PU address 111 into two, a control circuit configuration that consumes less power and can operate at high speed is provided.

The outline of the operation of the information processing apparatus of this embodiment will be described below with reference to FIG.

As shown in FIG. 1, first, when the CPU 101 requests access to the ROM 102, the CPU 1
01 is a CPU address 111 indicating an area of the ROM 102
Is output. Of these, the lower address 111a is the ROM
Provided to ROM 102 directly to select cells in 102. On the other hand, the upper address of the CPU address 111 is the CE-N signal generation circuit 10 in the memory control unit 103.
5 and a portion 111c given to the OE-N signal generation circuit 110. The CE-N generation circuit 105 decodes the bits A3 and A4 of the input CPU address 111 to obtain CE-N.
The N1 signal 104 and the CE-N2 signal 108 are set to the valid state, and the OE-N generation circuit 110 receives the input CPU address 111, read command 112, and CE-N2.
Based on the signal 108, the OE-N signal 109 is activated. These valid signals and CPU address 1
11, the specified memory cell is determined by the lower address directly given to the ROM 102, and the ROM data 113
Is output.

In order to make it easier to understand the effect of this embodiment, the CPU address width will be described as 5 bits (A0 to A4). However, this is for convenience of description, and in reality, the address width having a larger number of bits may be used. Figure 2
Shows an address map when the CPU address width is 5 bits.

In FIG. 2, of the entire address space, the address area of the ROM 102 is (00100B-0).
0111B). Here is a bit representation, for example,
(B) at the end of (00100B) indicates a binary display, and the same applies thereafter.

FIG. 3 shows a detailed configuration example of the memory control unit 103 corresponding to the address map of FIG. The upper address is determined by an address portion that can uniquely represent the ROM address area, and in this example, it is 3 bits of bits A4, A3 and A2 having a common value "001". Of the bits forming the high-order address, A2 is supplied to the OE-N generation circuit, and A3 and A4 are supplied to the CE-N generation circuit 105. In addition, bits A0 and A that form the lower address
1 is a CP for confirming the memory cell in the ROM 102.
It is directly supplied from U101 to the ROM102. CE-N
Inside the generation circuit 105, when the addresses A3 and A4 are both at L level (“0”), the CE-N1 signal 104 is valid (L
1 gate (hereinafter, OR1)
It is called a gate) 301. Further, inside the OE-N generation circuit 110, the CE-N2 signal 108 is valid and
When the bit A2 is H level (“1”) and the read command 112 is valid (L level), the OE-N signal 109 is made valid (L level), and a logical sum 2 gate (hereinafter, referred to as OR2 gate). ) 302 and an inverting gate (hereinafter referred to as an inverter) 303.

In the above configuration, the next five addresses are (01010B) →
(00101B) → (00111B) → (00001
Consider an example of sequentially accessing B) → (00110B) → (11101B). In the memory map of Figure 2,
The access sequence numbers (1) to (5) are shown associated with each corresponding address.

FIG. 4 shows a timing chart for the above series of accesses.

First, a read access to the address (01010B) is performed. Since this is not the address area of the ROM 102, the CE-N2 signal 108, OE-
Both N signals 109 are in an invalid state (H level).

Next, as the second access (0010
1B) is read-accessed. This is R
Since the access is to the address area of the OM 102, the CE-N2 signal is enabled at the timing of the latch clock 107, the OE-N signal 109 is enabled during the read command period, and the memory data 113 is output from the ROM 102. In the waveform of memory data in FIG. 4, "Hi-z" indicates that the bus is in a high impedance state.

Next, as the third access (0011
1B) is read-accessed. This is also RO
This is an access to the address area of M102. (001
CPU address 11 from 01B) to (00111B)
The CE-N1 signal 104 temporarily becomes an indefinite state when the value of 1 changes, but due to the action of the latch circuit 106, the ROM 1
The CE-N2 signal 108, which is the output signal to 02, does not change. Further, at the time of latching by the latch clock 107 in the latch circuit 106, the addresses A3 and A4 are the same as in the immediately preceding cycle (00101B), so CE-N2
The signal 108 remains valid (L level). Therefore,
The data 113 is read from the ROM 102 by OE-
It is determined by the access time from the N signal 109. Generally, the data read time from the ROM is about half that of the output enable signal (OE-N) as compared with that of the chip enable signal (CE-N). Therefore, (0
When the ROM 102 is continuously accessed like the access from (0101B) to (00111B), the CE-N
By leaving the 2 signal 108 valid, the data 113
Can be read faster than usual.

The fourth access is (00001
Read access to B) is performed. This is ROM
This is an address area other than the 102 area. In this case, since the address bits A3 and A4 are the same (L level) as in the immediately preceding cycle, the CE-N2 signal 108 remains valid, but the OE-N signal 109 is invalid because the address A2 is (L level). It becomes a state (H level). As a result, RO
The data 113 is not output from M102.

Next, as the fifth access, R
An address (00110) in the address area of the OM 102
Read access to B) is performed. In this case 3
As with the second (00111B) access, CE-
Since the N2 signal 108 is still in the valid state from the immediately preceding access, the OE-N signal 109 is accessed and high-speed reading is possible. That is, CE-N2 signal 1
By making the address A2 irrelevant to the control of 08, the CE-N2 signal 108 is generated even when an address area (00000B) to (00011B) other than the address area of the ROM 102 (hereinafter, referred to as a speed-up address area) is accessed. The state becomes valid (L level). This allows
After accessing the address area of the ROM 102,
Even if the access to the ROM 102 is interrupted, if the high-speed address area is accessed before the ROM 102 is accessed again, the high-speed access becomes possible when the ROM 102 is subsequently accessed. .

Finally, as the sixth access, (11
101B) is read-accessed. This is neither the address area of the ROM 102 nor the speed-up address area described above. In this case, address bits A3, A
Since 4 becomes (H level), both the CE-N2 signal 108 and the OE-N signal 109 are in an invalid state (H level).

As described above, the CE-N generation circuit 1
05 and the CPU upper address (A2 to A4 in the above embodiment) for the OE-N generation circuit 110 is divided into two, so that the high-speed address area can be set, and RO
Even if the access to M102 is interrupted, high-speed access is possible. Further, when the address area other than the address area and the speed-up address area of the ROM 102 is accessed, the CE-N2 signal 108 and the OE-N signal 109 are in an invalid state, so that the power consumption by the ROM 102 can be suppressed. .

In addition, this configuration reduces the change in the memory control signal, and has the effect of reducing the occurrence of noise.

It will be apparent to those skilled in the art that the position setting of the speed-up address area can be arbitrarily set by the address to be assigned. For example, in the example of FIG. 3, bits A2 and A3
Can be replaced (the inverter 303 can also be moved to the gate 301 side). In this case, unlike the case of FIG. 2, the speed-up address area is an area (01100B) to (01111B) apart from the ROM address area. Generally, it is preferable to make the speed-up address area adjacent to the ROM address area from the viewpoint of locality of memory access, but it is preferable to place it at a distant position for programs in which discrete address access frequently occurs. It is useful to set a speed-up address area.

It is also possible to change the number of bits to be divided into two parts from the case of FIG. For example, if bit A3 is OE-N
It can be transferred to the generation circuit 110 side. As will be easily guessed by those skilled in the art, in this case, the effect of power saving is reduced but the speed-up address area is expanded.

By the way, in a portable information processing device driven by a battery, power saving may be required more than speeding up.

FIG. 5 shows a memory control unit 1 which emphasizes power saving.
03 shows the details.

To generate the CE-N2 signal 108, the CE
The OR gate 501 and the inverter 502 are used in the -N signal generation circuit 105 to decode the addresses A2 to A4. Further, in order to generate the OE-N signal 109, the OE-
An OR gate 503 is used for the N signal generation circuit 110, and C
The E-N2 signal 108 and the read command 112 are decoded. As a result, the acceleration address area is not set, and the areas ((00100B) to (001) of the ROM 102 are set.
11B)) only when accessing the CE-N2 signal 108
Is effective, it is possible to save power.

FIG. 11 shows the characteristics of a ROM having an access time of 200 ns, 512 kwords × 16 bits, as an example of a ROM to be used in order to express the effect of this embodiment by using concrete numerical values. According to this, for speeding up, when accessing from the OE-N signal 109, CE-
The access time is shortened to 50% as compared with the access from the N2 signal 108. Regarding power consumption, RO
When the CE-N2 signal 108 is set to the invalid state when the M is not accessed, 0.2% of the electric power required when the CE-N2 signal 108 is set to the valid state is required.

The memory control unit 103 receives the CPU upper address 111 (A2, A3, A) as its input signal.
4), latch clock 107, and read command 11
2 is received, and the CE-N2 signal 108 and the OE-N signal 109 are output as output signals. Therefore, by configuring the memory control unit 103 with a programmable logic device (hereinafter, referred to as PLD), whether to set a speed-up address area and whether to set a speed-up address area depend on whether speeding up or power saving is important as an information processing device. It is possible to deal with the setting position (setting area) only by changing the PLD internal logic without changing the board.

Further, it is possible to arbitrarily control the presence / absence of setting and the setting position of the speed-up address area by software. FIG. 6 shows a schematic configuration example of the memory control unit 103 that enables control by software.

In FIG. 6, presence / absence of setting of the speed-up address area shown in FIGS. 3 and 5 is controlled by software. The speed-up address setting register (hereinafter referred to as the speed-up register) 601 is set to "1" to set the speed-up address area (the same as in FIG. 3), and when "0" is set to the speed-up address area. Is not set (same as FIG. 5). The speed-up address setting circuit 602 includes an OR circuit 603, a NAND circuit 604, and an inverter 605. Speed-up register 60
When "1" is set to 1, the gate 604 is opened, and this reflects the state of the address A2 to the OE-N generation circuit 110 via the speed-up address setting circuit output 1 signal 606. On the contrary, when "0" is set in the speed-up register 601, the gate 603 is opened, which reflects the state of the address A2 in the CE-N generation circuit 105 via the speed-up address setting circuit output 2 signal 607. To do.

In the above embodiments, the read-only ROM is used as the memory, but the memory access control device according to the present invention is not limited to this, and the writable static random access memory (hereinafter, SRA
It is also applicable to M).

FIG. 7 is a block diagram showing a schematic configuration example of an information processing apparatus using SRAM as a memory. In this schematic configuration example, the control for the ROM shown in FIG.
The control condition is replaced with the control for the, and the setting conditions of the address area of the SRAM and the speed-up address are the same as those in the embodiment for the ROM. The SRAM 701 is a readable / writable memory, and the memory data 702 is bidirectional data. Memory write pulse generation circuit 70
3 is a write command 704, OE from the CPU 101
Based on the memory write pulse permission signal 705 and the CE-N2 signal 108 from the -N generation circuit 110, the memory write pulse 706 (hereinafter referred to as the MWE-N signal).
To generate. Other configurations are similar to those of the information processing apparatus shown in FIG.

FIG. 8 shows a detailed configuration example of the memory control unit 103 in the information processing apparatus of FIG. The memory write pulse generation circuit 703 is composed of an OR circuit 801. Regarding the memory read cycle, the same control as the circuit shown in FIG. 3 is performed. For memory write cycle, OE
Read command signal 112 to -N generation circuit 110
By providing the memory write pulse generation circuit 703 whose input is the write command signal 704, control similar to the memory read cycle becomes possible.

As can be seen from the description of this embodiment, by devising the method of allocating the CPU address for generating the memory control signal, the speed of memory access and the power saving can be easily increased according to the application. Can be realized.

[0050]

As described above, according to the present invention, the following effects can be obtained.

(1) By dividing the address from the central processing unit required to generate the memory control signal into two, a wider address area including the address area allocated to the memory is operated at high speed during continuous access. be able to.

(2) In dividing the CPU address into two,
Depending on the mode of address division, it is possible to arbitrarily change the address area in which the speed can be increased.

(3) When an address area other than the wider address area is accessed, the power consumption of the memory can be suppressed, and the memory access can be speeded up and power can be saved.

(4) PLD control circuit for realizing the present invention
Alternatively, by providing a dedicated register and enabling software control, it is possible to realize a control circuit in which speeding up or power saving is enhanced according to the application without changing the substrate.

(5) The control circuit according to the present invention can be used not only for read-only ROM but also for writable RAM.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an information processing apparatus to which the present invention has been applied.

FIG. 2 is a memory address map of the embodiment.

FIG. 3 is a block diagram showing a configuration of a memory control circuit unit of an embodiment corresponding to speeding up.

FIG. 4 is an operation timing chart of the embodiment.

FIG. 5 is a block diagram showing a configuration of a memory control circuit unit of an embodiment corresponding to power saving.

FIG. 6 is a block diagram showing a configuration of a memory control unit of an embodiment corresponding to switching by software.

FIG. 7 is a block diagram showing the configuration of an embodiment of another information processing apparatus to which the present invention has been applied.

FIG. 8 is a block diagram showing a configuration of a memory control unit according to another embodiment.

FIG. 9 is a block diagram showing a configuration of an example of a memory control circuit according to a conventional technique.

FIG. 10 is an operation timing chart of a memory control circuit according to a conventional technique.

FIG. 11 shows an access time of 200 ns, 512 kwords × 16 bits R as an example of a memory applicable to the present invention.
It is explanatory drawing of the electrical characteristic of OM.

[Explanation of symbols]

101 ... CPU, 102 ... ROM, 103 ... Memory control section, 104 ... CE-N1 signal, 105 ... CE-N generation circuit, 106 ... Latch circuit, 107 ... Latch clock, 1
08 ... CE-N2 signal, 109 ... OE-N signal, 110
... OE-N generation circuit, 111 ... CPU address, 112
... Memory read command, 113 ... Memory data, 30
1 ... OR1 gate, 302 ... OR2 gate, 303 ... inverter, 601 ... acceleration address setting register, 60
2 ... High-speed address control circuit, 701 ... SRAM, 70
3 ... Memory write pulse generation circuit, 704 ... Memory write command, 705 ... Memory write pulse enable signal, 7
06 ... MWE-N signal

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Atsuhiro Higa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Hitachi Imaging Information Systems (72) Inventor Toshiyuki Tsunemoto 810 Shimoimaizumi, Ebina-shi, Kanagawa Stock Association (72) Inventor, Yoshio Watanabe, 810 Shimoimaizumi, Ebina, Kanagawa Stock Company, Hitachi, Ltd. Office Systems Division

Claims (3)

[Claims] 1. A memory access control device having at least a first control signal for enabling a memory chip, a second control signal for enabling the output of data, and an address and data terminal. A first address for dividing the upper address for selecting the memory among the addresses from the processing device is divided into first and second address parts and generating the first control signal based on the first address part. A control circuit section, a signal for instructing output of memory data from the central processing unit, an output signal of the first control circuit section, and a second control signal generated based on the second address section. 2. A memory access control device comprising: a second control circuit unit. 2. The first control circuit section outputs an output signal of the decoder section by a decoder for decoding the first address section and a latch clock generated immediately after a change of the address from the central processing unit. The memory access control device according to claim 1, wherein the memory access control device comprises a latch circuit for latching. 3. A switching circuit unit for switching at least one bit of the upper address from inputting the one bit to the first control circuit unit or the second control circuit unit, and the switching circuit unit. 3. The memory access control device according to claim 1, further comprising a register that holds data instructing switching of the circuit unit.