KR100491861B1 - memory control method for realizing zero wait accessing to synchronous memory buit-in MCU with ARM core - Google Patents

Abstract

Transition to the third state when the selection signal and the write signal are each 1 in the first state; and transition to the fifth state when the selection signal and the write signal are each 1 in the third state; Transition to the fourth state when 0 and the write signal is X; transition to the second state when the selection signal is 1 and the write signal is 0 in the fourth state; A transition to the first state in the case of X, and a transition to the fourth state in the case where the selection signal is 0 and the write signal is X in the fifth state. It is a zero weight state that does not add the weight state by using the memory. It is a zero weight state that can improve the performance of the system by enabling both read and write operations to the memory without glitches or timing problems. It provides a way to access the memory.

Description

Memory control method for realizing zero weight access to synchronous memory embedded in the ARM core embedded microcontroller unit {memory control method for realizing zero wait accessing to synchronous memory buit-in MCU with ARM core}

The present invention relates to a method of accessing a synchronous memory as a zero weight. More specifically, the present invention relates to a method of accessing a synchronous memory as a zero weight state. The present invention relates to a method of accessing synchronous memory as a zero weight, which can improve performance of a system by allowing all to be done without a timing problem.

Microcontroller units (Micro Controller Units, MCUs) incorporating ARM cores proposed by ARM have been used to control many systems due to low power characteristics and cost advantages of the arm cores.

The microcontroller unit with an arm core implements an internal bus system using an AMBA bus proposed by ARM.

In addition, the above-described female core built-in microcontroller unit generally uses synchronous memory as its internal memory. As the synchronous memory, a ROM is used to store a code and a RAM is used to store data.

However, in the case of using such a synchronous memory in the built-in female core microcontroller unit, it is difficult to implement both the read operation and the write operation in the zero weight state, which is difficult due to the characteristics of the AMBA bus.

1 shows the timing operation of a typical AMBA bus. As shown in FIG. 1, in the case of a memory write operation, one system cycle is applied into the memory controller later than the selection signal DSELMem indicating the selection of the memory controller. That is, in the case of the memory write operation, since the data to be written is supplied to the memory after the control signal such as the address signal BA is finished, in the case of the synchronous memory, the selection signal (synchronized with the address signal BA) is applied. In the positive edge state of the section in which the DSELMem is 1, the valid data signal BD is not supplied. Therefore, under this AMBA bus structure, it is not possible to write a synchronous memory that operates the memory operation at the positive edge as a zero weight.

In order to solve this problem, even when a synchronous memory using a negative edge is used, the operation of the zero weight state in the read operation cannot be guaranteed. This is because the valid data signal BD in the read operation must be supplied to the memory external bus at the same timing as in the write operation.

Therefore, when the synchronous memory is used in the built-in female core microcontroller unit, when the positive edge is used, the write operation cannot be performed in the zero weight state, and when the negative edge is used, the read operation is performed in the zero weight state. It becomes impossible.

In FIG. 1, if the weight signal BWAIT is 0, and if it is not zero weight, the memory controller applies the weight signal BWAIT for one clock period to extend a signal such as the selection signal DSELMem by one clock longer. shall. After all, either a write or read operation must be implemented with a weighted state.

In the related art, a female core embedded microcontroller unit is constructed by using a structure for applying one weight state in a memory write operation.

However, when the write operation is performed by applying one weight state to the write operation of the memory, the weight state is added, thereby degrading the operation performance of the female core embedded system. In particular, there is a problem in that the performance penalty imposed on the system becomes larger when writing a lot of data in a row.

In addition, there is a problem that it is difficult to guarantee the normal operation of the memory due to the glitch or timing occurring between the signals.

Even if the zero weight state can be implemented, there are many implementation limitations due to the glitches or the setup or hold time.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems in view of the above situation, and uses a synchronous memory operating at a forward edge to perform a read operation and a write operation in the memory as a zero weight state without adding a weight state. The present invention provides a memory control method for realizing zero weight access to the synchronous memory embedded in an arm core microcontroller unit, which can improve the performance of the system by allowing all to be done without glitches or timing problems.

According to an aspect of the present invention for achieving the above object, the third state-the synchronous memory when the selection signal and the write signal are each 1 in the first state-the access to the synchronous memory is not present in the current bus section; Transitioning to a state from which a control signal for writing a signal is input from the outside; In the third state, when the selection signal and the write signal are each 1, a transition is made to the fifth state, in which the write operation to the synchronous memory occurs continuously and the synchronous memory write operation is internally pipelined once. Transitioning to a fourth state in which the selection signal is 0 and the write signal is X (don't care)-a state in which a synchronous memory write operation does not occur continuously but a write operation to an actual memory occurs; In the fourth state, when the selection signal is 1 and the write signal is 0, the second state transitions to a read operation state for the synchronous memory, and the first selection signal is 0 and the write signal is X. Transition to a state; And transitioning to a fourth state when the selection signal is 0 and the write signal is X in the fifth state. A memory control method is provided.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. . Other objects, features, and operational advantages, including the object, operation, and effect of the present invention will become more apparent from the description of the preferred embodiment.

For reference, the embodiments disclosed herein are only presented by selecting the most preferred examples to help those skilled in the art from the various possible examples, the technical spirit of the present invention is not necessarily limited or limited only by this embodiment. However, various changes and modifications are possible within the scope without departing from the technical spirit of the present invention, as well as other equivalent embodiments.

FIG. 2 is a state diagram illustrating an algorithm of a memory controller for implementing zero weight access to a synchronous memory embedded in an arm core embedded microcontroller unit according to an exemplary embodiment of the present invention. As shown in Fig. 2, the configuration of the method of accessing the synchronous memory as the zero weight according to the embodiment of the present invention is selected in the first state BIDLE indicating that there is no access to the synchronous memory in the current bus section. When the signal DSELMem and the write signal BWRITE are each 1, the process transitions to the third state WRDDY and the third state WRRDY indicating a state in which a control signal for writing the synchronous memory is input from the outside. When the signal DSELMem and the write signal BWRITE are each 1, the signal transitions to the fifth state WRSEQ, when the selection signal DSELMem is 0 and the write signal BWRITE is X (don't care). The selection signal DSELMem is 1 and the write signal BWRITE is in the process of transitioning to the four-state WRNOS and in the fourth state WRNOS indicating a state in which the synchronous memory write operation does not occur continuously but the write operation to the real memory occurs. ) Is 0 When the transition to the second state RDMEM, the selection signal DSELMem is 0, and the write signal BWRITE is X, the process transitions to the first state BIDLE, and the write operation to the synchronous memory occurs continuously. In the fifth state WRSEQ representing a state in which the synchronous memory write operation is internally pipelined once, the process transitions to the fourth state WRNOS when the selection signal DSELMem is 0 and the write signal BWRITE is X. It is made to include.

With the above configuration, the operation of the method of accessing the synchronous memory as the zero weight according to the embodiment of the present invention is as follows.

Basically, synchronous memory should operate at positive edge. If the memory running on the negative edge is given in the form of IP, it can be used by reversing the clock of the memory.

The read operation for synchronous memory is no different from the conventional method. However, the write operation to the synchronous memory occurs through the state transition as shown in FIG.

In FIG. 2, the first state BIDLE indicates that access to the synchronous memory is not present in the current bus section, the second state RDMEM indicates a read operation to the synchronous memory, and the third state WRRDY indicates a synchronous memory. The fourth state WRNOS indicates a state in which a control signal for writing is input from the outside, and the fourth state WRNOS indicates a state in which a write operation to the real memory does not occur continuously, and the fifth state WRSEQ indicates to the synchronous memory. This is a case where the write operation is continuously performed, and the synchronous memory write operation is internally pipelined once.

When a write access to the synchronous memory is attempted, the memory controller internally signals the system bus that the write operation to the synchronous memory has been completed, although the write operation to the synchronous memory has not yet been completed. That is, the weight signal BWAIT is made zero.

In fact, the write operation to the internal memory block occurs in the fourth state WRNOS or the fifth state WRSEQ. If access to the memory block occurs continuously, in this case, the write operation of the memory block is pipelined once.

The reason why the synchronous memory can be accessed with the state transition characteristic as shown in FIG. 2 is due to the characteristic of the AMBA bus. In the structure of the AMBA bus, continuous access to each peripheral is possible only if the signals controlling the bus (BWRITE, BSIZE, etc.) are the same as before. Therefore, it is impossible to access continuously while writing and reading memory blocks. As a result, the write operation to the synchronous memory is late internally for this reason, but the next read operation can read valid data.

In the case of using the state transition characteristic proposed in the present invention for the AMBA bus, in the case of reading and writing the synchronous memory, it is possible to access the memory without adding an additional weight state. In addition, in this case, the glitch problem that may occur when accessing the synchronous memory can also be solved, and thus it can be applied to many cancer core embedded systems.

As described above, in the embodiment of the present invention, the zero-weight state without adding the weight state by using the synchronous memory operating at the positive edge so that both the read operation and the write operation in the memory can be performed without glitches or timing problems. Therefore, it is possible to provide a method of accessing the synchronous memory as a zero weight having an effect of improving the performance of the system. Such an effect of the present invention can be used in various applications within the scope of the technical concept of the present invention in the field of memory access.

1 is a timing diagram of a typical AMBA bus.

2 is a state diagram illustrating an algorithm of a memory controller for implementing zero weight access according to an embodiment of the present invention.

 Explanation of symbols for the main parts of the drawings *

BIDLE: First state RDMEM: Second state

WRDDY: third state WRNOS: fourth state

WRSEQ: fifth state

Claims (6)

delete delete delete delete delete Transitioning from the first state-the state in which access to the synchronous memory is not present in the bus section-to the third state-the state in which the control signal for writing the synchronous memory comes from outside-when the selection signal and the write signal are each 1 ; In the third state, when the selection signal and the write signal are each 1, a transition is made to the fifth state, in which the write operation to the synchronous memory occurs continuously and the synchronous memory write operation is internally pipelined once. Transitioning to a fourth state in which the selection signal is 0 and the write signal is X (don't care)-a state in which a synchronous memory write operation does not occur continuously but a write operation to an actual memory occurs; In the fourth state, when the selection signal is 1 and the write signal is 0, the second state transitions to a read operation state for the synchronous memory, and the first selection signal is 0 and the write signal is X. Transition to a state; And Transitioning to the fourth state when the selection signal is 0 and the write signal is X in the fifth state; The memory control method for implementing a zero weight access to the synchronous memory embedded in the female core embedded microcontroller unit comprising a.