JPH04337666A - Semiconductor nonvolatile memory and its writing method - Google Patents

Abstract

PURPOSE:To achieve both a high-speed writing and a long-time data retention by transferring and then writing a data to a memory block consisting of a memory element with a second film-thickness gate insulating film which is thicker than a first film thickness by a memory block consisting of a memory element with a gate insulating film with a first film thickness. CONSTITUTION:A semiconductor nonvolatile memory 10 consists of a first memory block 1, a second memory block 2, and a transfer block 3 which controls their input and output and performs transfer and writing of data between them. A memory element used for a second memory element 21 within a second memory block 2 has a thicker gate insulating film than a memory element which is used for a first memory element array 11 within the first memory block 1, where the first memory block 1 can write data at high speed and the second memory block 2 has a long data-retention time. thus enabling an application range of the semiconductor nonvolatile memory to be expanded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable semiconductor nonvolatile memory and a writing method therefor.

0002

[Background Art and its Problems] Conventional semiconductor non-volatile memory is composed of memory elements each having a gate insulating film made to have the same film thickness, and is composed of a single or multiple memory element blocks. It is made up of blocks.

[0003] In a conventional semiconductor nonvolatile memory constructed of memory elements having gate insulating films of the same thickness, thinning the gate insulating film shortens the data write time but also shortens the data retention time. On the other hand, if the thickness of the gate insulating film is increased, the data retention time will be increased, but the data writing time will also be increased. Therefore, it is impossible to achieve both high-speed writing and long-term data retention.

The present invention aims to provide a structure of a semiconductor non-volatile memory that has both high-speed writing performance and long-term data retention, which are impossible to achieve at the same time as described above, and a writing method therefor. The purpose is

[0005]

[Means for Solving the Problems] In order to achieve the above object, the present invention employs the configuration and method described below.

[0006] The semiconductor nonvolatile memory according to the present invention includes:
A first memory block constituted by a memory element having a gate insulating film having a first thickness, and a second memory block constituted by a memory element having a gate insulating film having a second thickness thicker than the first thickness. and a transfer block for transferring and writing data from the first memory block to the second memory block.

The semiconductor nonvolatile memory writing method according to the present invention writes data into a first memory block from the outside, and then transfers and writes the data from the first memory block to a second memory block.

[0008]

[Embodiments] Examples of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a semiconductor nonvolatile memory according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor nonvolatile memory 10 includes a first memory block 1 and a second memory block 1.
memory block 2 and these first memory blocks 1
and a transfer block 3 that controls input/output between the first memory block 1 and the second memory block 2, and transfers and writes data between the two first memory blocks 1 and the second memory block 2. .

Furthermore, the first memory block 1 and the second memory block 2 each include a first memory element array 11 and a second memory element array 21, and a first Y decoder 12 and a second Y decoder 22. , first X decoder 1
3, second X decoder 23, and first I/O buffer 14
and a second I/O buffer 24, a first address buffer 15 and a second address buffer 25, and a first control circuit 16 and a second control circuit 26. Of these, the first memory element array 11 and the second memory element array 21 are constituted by memory elements having gate insulating films of different thicknesses. That is, the first
Compared to the memory element used in the first memory element array 11 in the memory block 1, the gate insulating film of the memory element used in the second memory element array 21 in the second memory block 2 is thicker. I'm trying to make it happen.

In this embodiment, the first memory element array 1
1 and the second memory element array 21 are both MONO
It is configured using an S-structure memory element.

The cross-sectional view of FIG. 2 schematically shows the structure of the gate insulating film of this MONOS structure memory element. The gate insulating film is composed of a three-layer insulating film including, from the gate electrode 41 side, a top oxide film 42, a silicon nitride film 43, and a tunnel oxide film 44.

In a memory element with a MONOS structure, the writing speed and data retention time differ depending on the thickness of the gate insulating film, as shown in FIG. It has been experimentally proven that the length can be shortened. Therefore, the first memory block 1 shown in FIG. 1, which includes a memory element with a thin gate insulating film, can perform high-speed writing but has a short data retention time. On the other hand, the second memory block 2, which includes memory elements whose gate insulating films are thicker than the memory elements in the first memory block 1, cannot perform high-speed writing but has a long data retention time.

[0013] In a specific experimental example, in a memory element in which the thickness of the gate insulating film was reduced in order to provide high-speed writing performance, the writing time was about 10 microseconds and the data retention time was about 500 hours. On the other hand, in a memory element in which the thickness of the gate insulating film is increased in order to give priority to data retention, a data retention time of 10 years or more is obtained with a writing time of about 10 milliseconds.

The transfer block 3 also connects a data bus with the outside, the first I/O buffer 14, and the second I/O buffer 24, and provides a data I/O buffer for controlling data input/output.
/O control circuit 31 and a reference clock generation circuit 3 that generates a basic clock that determines the timing of transfer writing.
2, an address signal generation circuit 33 for determining the address for transfer writing, and an external address bus, the first address buffer 15, and the second address buffer 25, which select the address and select the output destination. The address control circuit 34 performs the following operations, and the control signal generation circuit 35 generates clock signals such as write enable signals.

Next, a method of writing to the semiconductor nonvolatile memory having the above structure will be described. First, external data is written to the first memory block 1. At this time, an external address signal is transmitted to the first address buffer 16 by the address control circuit 34, and the first A portion of the first memory element array 11 is selected by the decoder 13 and the first Y decoder 12. Similarly, an external control signal is transmitted to the first control circuit 16 by the control signal generation circuit 35,
Data is also input to the first I/O buffer 14 through the data I/O control circuit 31 and written to the selected memory element of the first memory element array 11. The write time at this time can be fast because the gate insulating film used in the memory elements of the first memory element array 11 is relatively thin.

Next, using the time when this semiconductor nonvolatile memory is not being accessed from the outside, transfer writing is performed from the first memory block 1 to the second memory block 2. Whether or not it is being accessed from the outside can be determined using a chip enable signal or the like.

Transfer writing uses the transfer block 3 to read data from the first memory block 1 and writes this data to the second memory block 2. At this time,
The read timing from the first memory block 1,
The timing of writing to the second memory block 2 is determined by the control signal generation circuit 34 based on the basic clock generated by the reference clock generation circuit 32 in the transfer block 3. Since writing to the second memory block 2 does not need to be performed at high speed, power consumption can be suppressed by slowing down the basic clock. The address signal generation circuit 33 is
It is sufficient to simply generate a signal that increases from address zero to the maximum address of the memory, and can be realized with a simple counter circuit. Address control circuit 34 outputs the address generated by address signal generation circuit 33 to both first address buffer 15 and second address buffer 16.

The data stored in the memory element at the selected address of the first memory block 1 is
The data is transferred to the second I/O buffer 24 through the /O buffer 14 and the data I/O control circuit 31, and written into the selected memory element of the second memory block 2. At this time, the data I/O control circuit 31 puts the data output to the outside into a high impedance state.

Data transferred and written to the memory element array 21 of the second memory block 2 is transferred for a very long period of time because the gate insulating film of the memory elements constituting the second memory element array 21 is thick. Data can be retained.

Normal reading from this semiconductor nonvolatile memory is performed from the second memory block 2. In this case, the address signal and control signal given from the outside are the address control circuit 34 and the control signal generation circuit 3, respectively.
5, the data is transmitted only to the second address buffer 25 and the second control circuit 26, and the data I/O control circuit 31 outputs the output of the second I/O buffer 24 to the external data bus.

[0021] When used in a system in which reading for data confirmation is performed immediately after data writing, or when reading is performed before transfer writing, data is transferred from the first memory block 1 to the first memory block 1. The data is read out through the I/O buffer 14 and the data I/O control circuit 31.

[0022] Furthermore, if an access occurs during a transfer write, the transfer write is immediately interrupted, and if this access is for reading data, the address being transferred is held pending until the transfer write continues, and the write is suspended. In this case, the address is cleared to zero.

[0023] Is transfer writing not yet performed?
The status of execution, suspension, or termination is stored in the control signal generation circuit 35, and based on the memory, control signals are generated in accordance with the various cases described above.

In this embodiment, a memory element having a MONOS structure has been described as a memory element constituting a memory element array, but a memory element having an MNOS (metal-nitride-oxide-semiconductor) structure can also be applied.

[0025]

[Effects of the Invention] As explained above, according to the present invention,
In electrically rewritable semiconductor non-volatile memory, we have achieved high-speed write performance and long-term data retention, which are impossible to achieve with conventional memories that are composed of memory elements with gate insulating films all of the same thickness. By having both, the range of applications of semiconductor nonvolatile memory can be greatly expanded.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a semiconductor nonvolatile memory in one embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the structure of memory elements constituting a memory element array in the semiconductor nonvolatile memory of the present invention.

[Explanation of symbols]

1 First memory block 2 Second memory block 3 Transfer block 11 First memory element array 21 Second memory element array 31 Data I/O control circuit 32 Reference clock generation circuit 33 Address signal generation circuit 34 Address control circuit 35 Control signal generation circuit

Claims (3)

[Claims] 1. A first memory block constituted by a memory element having a gate insulating film with a first thickness, and a memory element having a gate insulating film with a second thickness thicker than the first thickness. a second memory block configured by;
A semiconductor nonvolatile memory comprising a transfer block for transferring and writing data from the first memory block to the second memory block. 2. The semiconductor nonvolatile memory according to claim 1, wherein the memory element is an element having a MONOS (metal-oxide film-nitride film-oxide film-semiconductor) structure. 3. A method for writing a semiconductor non-volatile memory, comprising writing data into a first memory block from the outside, and then transferring and writing the data from the first memory block to a second memory block.