JPH0730011A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0730011A
JPH0730011A JP5153247A JP15324793A JPH0730011A JP H0730011 A JPH0730011 A JP H0730011A JP 5153247 A JP5153247 A JP 5153247A JP 15324793 A JP15324793 A JP 15324793A JP H0730011 A JPH0730011 A JP H0730011A
Authority
JP
Japan
Prior art keywords
heat
semiconductor element
substrate
heat conducting
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5153247A
Other languages
Japanese (ja)
Inventor
Masahisa Aoyanagi
正久 青柳
Kazuyasu Satou
和恭 佐藤
Takanori Shindo
孝徳 眞藤
Koji Touchi
孝治 戸内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5153247A priority Critical patent/JPH0730011A/en
Publication of JPH0730011A publication Critical patent/JPH0730011A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To efficiently transfer the heat generated by a semiconductor element to the back side of a substrate by inserting a heat-conducting member into a through hole. CONSTITUTION:A heat conducting material is inserted into a copper-plated through hole 7 in a substrate 2, and the heat conducting material 8 is directly connected to fins 9 which are formed by cooling material. As a result, the through hole 7 is almost filled up by the heat conducting material 8, and the heat of a semiconductor element can be introduced to the fins 9 efficiently by the heat conducting material 8. Also, when heat conducting grease 10 is interposed between the back side of the semiconductor element 1 and the heat conducting material 8, the heat of the semiconductor element 1 is transferred to the heat conducting material 8 by the heat conducting grease 10, and heat can be transferred effectively even when the surface, where the back side of the semiconductor element 1 and the heat conducting material 8 are brought into contact with each other, is poorly processed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、基板上に直接半導体素
子を搭載する半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor element directly mounted on a substrate.

【0002】[0002]

【従来の技術】基板上に直接半導体素子を搭載する半導
体装置において、半導体素子によっては素子の発熱によ
る電気特性の劣化が問題となる。そこで、半導体素子の
冷却が必要となり、方法としては特開昭64−80032 号公
報に記載のように、半導体素子をTAB(Tape Automete
d Bonding System)でフェース・アップに接続し、半導
体素子裏面を基板に接触させて半導体素子の熱を基板に
逃がす方式をとっていた。ここで、熱伝導が悪い基板の
場合、たとえば、ガラス・エポキシ基板等の場合には文
献(電子情報通信学会技報,ICD92ー133,19
92年12月号,53〜58頁)記載のように、半導体
素子をTABでフェース・アップに接続し、半導体素子
裏面の基板にスルーホールを多数設け、半導体素子の発
熱をスルーホール内の銅メッキを介して基板裏面の銅メ
ッキ部に熱を伝達し、さらに、基板裏面を強制空冷する
ことにより半導体装置を冷却する方式等を用いていた。
これらの方式では、TABテープの弾性により半導体素
子を基板に当接させることが可能であり、半導体素子と
基板をはんだ付け等せずに接触を保てる。このため、半
導体素子と基板の熱膨張係数を合わせる必要がなく、比
較的簡単に半導体装置を構成できる。
2. Description of the Related Art In a semiconductor device in which a semiconductor element is directly mounted on a substrate, depending on the semiconductor element, deterioration of electric characteristics due to heat generation of the element poses a problem. Therefore, it is necessary to cool the semiconductor element. As a method, as described in Japanese Patent Laid-Open No. 64-80032, the semiconductor element is TAB (Tape Automete
d Bonding System) is used for face-up connection, and the back surface of the semiconductor element is brought into contact with the substrate to release the heat of the semiconductor element to the substrate. Here, in the case of a substrate having poor heat conduction, for example, in the case of a glass / epoxy substrate, etc., reference is made to the literature (IEICE Technical Report, ICD92-133, 19).
As described in the December 1992 issue, pp. 53-58), the semiconductor elements are connected face-up by TAB, a large number of through holes are provided in the substrate on the back surface of the semiconductor elements, and the heat generated by the semiconductor elements is generated by the copper in the through holes. A method has been used in which heat is transferred to a copper-plated portion on the back surface of the substrate via plating, and the back surface of the substrate is forcibly air-cooled to cool the semiconductor device.
In these methods, the elasticity of the TAB tape can bring the semiconductor element into contact with the substrate, and the semiconductor element and the substrate can be kept in contact without soldering or the like. Therefore, it is not necessary to match the thermal expansion coefficients of the semiconductor element and the substrate, and the semiconductor device can be configured relatively easily.

【0003】[0003]

【発明が解決しようとする課題】このような構造の場
合、以下に示すような問題がある。すなわち、基板に熱
を伝える方式であるため、基板の材料としては熱伝導性
が高いほど良いが、基板の加工性,実装性,価格等の点
から限界がある。また、熱伝導性が低い安価なガラス・
エポキシ基板等を用いてスルーホールから熱を逃がす方
式では、基板の表側から裏側への熱伝達は主にスルーホ
ール内の銅メッキ部分だけであり、放熱特性を大幅に向
上することは期待できない等の問題があった。
In the case of such a structure, there are the following problems. That is, since it is a method of transferring heat to the substrate, the higher the thermal conductivity is, the better the material of the substrate is, but there is a limit in terms of workability, mountability, price, etc. of the substrate. In addition, inexpensive glass with low thermal conductivity
In the method of releasing heat from the through holes using an epoxy board, etc., heat transfer from the front side to the back side of the board is mainly limited to the copper plating part in the through holes, and it is not expected to greatly improve heat dissipation characteristics. There was a problem.

【0004】[0004]

【課題を解決するための手段】本発明の目的は、半導体
素子の発熱を基板の裏側に効率良く伝達することが可能
な半導体装置を提供することにある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of efficiently transmitting the heat generated by a semiconductor element to the back side of a substrate.

【0005】[0005]

【作用】すなわち、半導体素子の発熱を基板に設けたス
ルーホールから基板の裏側に放熱する半導体装置におい
て、スルーホール空間部に熱伝導部材を挿入することに
より、基板内での熱伝達を向上する。この熱伝導部材を
半導体素子裏面と直接接触させることにより、熱移動を
速やかに行う。さらに、スルーホール空間部に挿入した
熱伝導部材と半導体素子裏面との間に粘性状態の熱伝導
部材を介在させることにより、基板とスルーホール空間
部に挿入した熱伝導部材の熱膨張差によるひずみを除去
できる等の特徴がある。
That is, in a semiconductor device in which the heat generated by the semiconductor element is radiated from the through hole provided in the substrate to the back side of the substrate, the heat transfer in the substrate is improved by inserting the heat conducting member into the through hole space. . By directly contacting this heat conducting member with the back surface of the semiconductor element, heat is transferred quickly. Further, by placing a heat conducting member in a viscous state between the heat conducting member inserted in the through hole space and the back surface of the semiconductor element, distortion due to the difference in thermal expansion between the substrate and the heat conducting member inserted in the through hole space is caused. There is a feature that can be removed.

【0006】[0006]

【実施例】以下、本発明の一実施例について図面を参考
にして説明する。図1は半導体素子1を基板2にTAB
方式で実装した例で、TABリード3は基板側端子4と
半導体素子側端子5に接続されている。半導体素子1は
素子の保護のため、封止樹脂6で封止されている。そし
て、基板2には銅メッキされたスルーホール7の空間部
には熱伝導部材8が挿入されている。さらに、熱伝導部
材8は本実施例では冷却部材であるフィン9と直接接続
している。なお、フィン8は基板2の裏面に図示しない
接着材で係合されている。本実施例によれば、スルーホ
ール7内部は熱伝導部材8でほぼ満たされているため、
半導体素子1の発熱を熱伝導部材8によって効率良くフ
ィン9に導くことができる。このため、基板2の表と裏
の電気的な接続が必要な場合以外はスルーホール7内部
の金メッキを省略することも可能である。さらに、図1
において熱伝導部材8の厚さを基板2の厚さより若干厚
くし、TABリード3の弾性力で熱伝導部材8を半導体
素子1の裏面に押圧した例を図2に示す。本方式をとる
ことで半導体素子1から熱伝導部材8の接触状態を良好
に保てるため、熱伝達特性をさらに改善することができ
る。また、図3は本発明の別な実施例を示したもので、
半導体素子1の裏面と熱伝導部材8とは熱伝導グリース
10が介在した構成をとる。なお、フィン9は図示しな
い接着材によって基板2に接続されている。本実施例で
は、半導体素子1の発熱は熱伝導性グリース10によっ
て熱伝導部材8に伝わるため、半導体素子1の裏面と熱
伝導部材8とが当接する面の加工精度が悪くても熱伝達
を効率良く行うことができる。さらに、図4はワイヤボ
ンディング方式による実施例を示したもので、半導体素
子1と基板2の電気的接続はここでは金ワイヤ11を用
い、機械的な接続は弾性接着材12を用いた。ここで使
用した弾性接着材12はシリコーン樹脂である。そし
て、半導体素子1の発熱は熱伝導性グリース10を介し
て熱伝導部材8に伝達され、フィン9で放熱される。フ
ィン9は接着材13によって基板2に固定されている。
本実施例でも半導体素子1の発熱は熱伝導性グリース1
0によって効率よく熱伝導部材8に伝達される。また、
半導体素子1と基板2の熱膨張差は弾性接着材12によ
って緩和されるため、半導体素子1の破壊を防止するこ
とができる。さらに、熱伝導部材8と基板2の熱膨張差
は熱伝導性グリース10によって吸収されるため、半導
体素子1が破壊することがない。なお、接着材13は弾
性接着材12を用いてもよく、この場合は基板2とフィ
ン9の熱膨張差を吸収することが可能となる。図5は複
数個の半導体1を基板2にワイヤボンディング方式によ
り実装した実施例を示したもので、半導体素子1の気密
封止と熱応力の低減を目的としてシリコーン・ゲル14
による封止を行った。そして、半導体素子1を外力から
保護するため、複数個の半導体素子1全体をキャップ1
5で固定用接着材16を介して覆ったもので、他の構成
は実施例の図4と同様である。本実施例によれば、複数
個の半導体素子1を高密度に実装でき、放熱特性が良
く、かつ強度が高い安価な半導体装置を提供することが
できる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor device 1 on a substrate 2 which is TAB.
In the example mounted by the method, the TAB lead 3 is connected to the board-side terminal 4 and the semiconductor element-side terminal 5. The semiconductor element 1 is sealed with a sealing resin 6 to protect the element. A heat conductive member 8 is inserted in the space of the copper-plated through hole 7 in the substrate 2. Further, the heat conducting member 8 is directly connected to the fin 9 which is a cooling member in this embodiment. The fins 8 are engaged with the back surface of the substrate 2 by an adhesive material (not shown). According to this embodiment, the inside of the through hole 7 is almost filled with the heat conducting member 8,
The heat generation of the semiconductor element 1 can be efficiently guided to the fins 9 by the heat conducting member 8. Therefore, the gold plating inside the through hole 7 can be omitted except when the front and back of the substrate 2 need to be electrically connected. Furthermore, FIG.
2 shows an example in which the thickness of the heat conducting member 8 is made slightly thicker than the thickness of the substrate 2 and the heat conducting member 8 is pressed against the back surface of the semiconductor element 1 by the elastic force of the TAB lead 3. By adopting this method, the contact state between the semiconductor element 1 and the heat conducting member 8 can be kept good, and therefore the heat transfer characteristics can be further improved. Further, FIG. 3 shows another embodiment of the present invention.
The back surface of the semiconductor element 1 and the heat conducting member 8 have a structure in which a heat conducting grease 10 is interposed. The fin 9 is connected to the substrate 2 by an adhesive material (not shown). In the present embodiment, the heat generated by the semiconductor element 1 is transferred to the heat conducting member 8 by the heat conductive grease 10. Therefore, even if the processing accuracy of the surface where the back surface of the semiconductor element 1 and the heat conducting member 8 abut is poor, the heat transfer can be prevented. It can be done efficiently. Further, FIG. 4 shows an embodiment by the wire bonding method, in which the semiconductor element 1 and the substrate 2 are electrically connected by using the gold wire 11 here, and the mechanical connection is made by using the elastic adhesive material 12. The elastic adhesive material 12 used here is a silicone resin. Then, the heat generated by the semiconductor element 1 is transmitted to the heat conductive member 8 via the heat conductive grease 10 and radiated by the fins 9. The fin 9 is fixed to the substrate 2 with an adhesive material 13.
Also in this embodiment, the heat generated by the semiconductor element 1 is generated by the heat conductive grease 1.
0 is efficiently transmitted to the heat conducting member 8. Also,
Since the difference in thermal expansion between the semiconductor element 1 and the substrate 2 is mitigated by the elastic adhesive material 12, it is possible to prevent the semiconductor element 1 from being broken. Further, since the difference in thermal expansion between the heat conductive member 8 and the substrate 2 is absorbed by the heat conductive grease 10, the semiconductor element 1 is not destroyed. The adhesive material 13 may be the elastic adhesive material 12, and in this case, the difference in thermal expansion between the substrate 2 and the fin 9 can be absorbed. FIG. 5 shows an embodiment in which a plurality of semiconductors 1 are mounted on a substrate 2 by a wire bonding method. For the purpose of hermetically sealing the semiconductor element 1 and reducing thermal stress, a silicone gel 14 is used.
It was sealed by. Then, in order to protect the semiconductor element 1 from an external force, the whole of the plurality of semiconductor elements 1 is capped.
5 is covered with the fixing adhesive 16 and the other structure is the same as that of FIG. 4 of the embodiment. According to the present embodiment, a plurality of semiconductor elements 1 can be mounted at high density, a heat dissipation characteristic is good, and an inexpensive semiconductor device having high strength can be provided.

【0007】[0007]

【発明の効果】本発明によれば半導体素子を、直接、基
板に実装する半導体装置において、比較的単純な構成で
良好な放熱特性を得ることができる。また、スルーホー
ル内に挿入された熱伝導部材によって十分な熱伝達が得
られるため、電気特性で必要な場合を除き、スルーホー
ル内の銅メッキを省略することができる。さらに、基板
材料としてガラス・エポキシ基板等が使えるため、装置
を安価に提供することが可能である。
According to the present invention, in a semiconductor device in which a semiconductor element is directly mounted on a substrate, good heat dissipation characteristics can be obtained with a relatively simple structure. Further, since the heat conducting member inserted in the through hole can obtain sufficient heat transfer, copper plating in the through hole can be omitted unless it is necessary for electrical characteristics. Furthermore, since a glass / epoxy substrate or the like can be used as the substrate material, the device can be provided at low cost.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明を用いたTAB方式の半導体装置の一実
施例を示す断面図。
FIG. 1 is a sectional view showing an embodiment of a TAB type semiconductor device using the present invention.

【図2】本発明を用いたTAB方式の半導体装置の第二
の実施例を示す断面図。
FIG. 2 is a sectional view showing a second embodiment of a TAB semiconductor device using the present invention.

【図3】本発明を用いたTAB方式の半導体装置の第三
の実施例を示す断面図。
FIG. 3 is a sectional view showing a third embodiment of a TAB semiconductor device using the present invention.

【図4】本発明を用いたワイヤ・ボンディング方式の半
導体装置の一実施例を示す断面図。
FIG. 4 is a sectional view showing an embodiment of a wire bonding type semiconductor device using the present invention.

【図5】本発明を用いたワイヤ・ボンディング方式の半
導体装置の他の実施例を示す断面図。
FIG. 5 is a sectional view showing another embodiment of a wire bonding type semiconductor device using the present invention.

【符号の説明】[Explanation of symbols]

1…半導体素子、2…基板、3…TABリード、7…ス
ルーホール、8…熱伝導部材、10…熱伝導性グリー
ス。
DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Substrate, 3 ... TAB lead, 7 ... Through hole, 8 ... Thermal conductive member, 10 ... Thermal conductive grease.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 戸内 孝治 神奈川県横浜市戸塚区戸塚町216番地 株 式会社日立製作所情報通信事業部内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koji Touchi 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi Ltd. Information & Communication Division

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】スルーホールを有する基板の片側の面に半
導体素子の裏面を、前記基板の反対側の面に冷却部材を
接合した半導体装置において、前記スルーホールの空間
部に熱伝導部材を設けたことを特徴とする半導体装置。
1. A semiconductor device in which a back surface of a semiconductor element is bonded to one surface of a substrate having a through hole and a cooling member is bonded to a surface on the opposite side of the substrate, and a heat conducting member is provided in a space of the through hole. A semiconductor device characterized by the above.
JP5153247A 1993-06-24 1993-06-24 Semiconductor device Pending JPH0730011A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5153247A JPH0730011A (en) 1993-06-24 1993-06-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5153247A JPH0730011A (en) 1993-06-24 1993-06-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0730011A true JPH0730011A (en) 1995-01-31

Family

ID=15558285

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5153247A Pending JPH0730011A (en) 1993-06-24 1993-06-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0730011A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008099554A1 (en) * 2007-02-15 2008-08-21 Nec Corporation Structure for mounting semiconductor package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008099554A1 (en) * 2007-02-15 2008-08-21 Nec Corporation Structure for mounting semiconductor package
US7983048B2 (en) 2007-02-15 2011-07-19 Nec Corporation Structure for mounting semiconductor package

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