JPH0729975A - Semiconductor element and its manufacture - Google Patents
Semiconductor element and its manufactureInfo
- Publication number
- JPH0729975A JPH0729975A JP17027493A JP17027493A JPH0729975A JP H0729975 A JPH0729975 A JP H0729975A JP 17027493 A JP17027493 A JP 17027493A JP 17027493 A JP17027493 A JP 17027493A JP H0729975 A JPH0729975 A JP H0729975A
- Authority
- JP
- Japan
- Prior art keywords
- film
- sio
- forming
- gas
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】この発明は、半導体素子とその製
造方法のうち、絶縁膜、特に配線間を電気的に絶縁する
層間絶縁膜の形成に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element and a method of manufacturing the same, and more particularly to the formation of an insulating film, particularly an interlayer insulating film for electrically insulating between wirings.
【0002】[0002]
【従来の技術】従来、半導体素子の絶縁膜は、プラズマ
化学気相成長(PE−CVD)法を用いたシリコン酸化
膜(SiO2 )が広く使用されてきた。しかしながら、
素子の微細化、高集積化が進み、配線間の容量が増加し
て回路としての素子の駆動力に影響を与えるようになっ
てきた。そこで、誘電率の低い絶縁膜の要求が高まって
おり、そのような低誘電率の絶縁膜の形成方法として
は、筆者らが先に出願した特願平5−89891号明細
書などにも記載してあるように、PE−CVD法による
SiO2 膜形成の際、F原子を含むエッチングガス(例
えば、C2 F6 ,CF4 ,NF3 ,HFなど)を添加し
て、組成がSiOx Fy である膜を形成する方法が実施
されている。このSiOx Fy 膜の形成方法は、例え
ば、電源周波数13.56MHzの平行平板型PE−C
VD装置を用い、生成ガスとして、TEOS(テトラエ
チルオルソシリケートまたはテトラエトキシシランとも
言う)400cc/min,O2 400cc/min,
C2 F6 200cc/min,RF(Radio Fr
eqency)パワー2W/cm2 、圧力10Tor
r、温度350℃、電極間距離5mmという条件で実現
できる。なお、前述したようにC2 F6 ガスはFを含む
他のガスでもよい。2. Description of the Related Art Conventionally, a silicon oxide film (SiO 2 ) using a plasma chemical vapor deposition (PE-CVD) method has been widely used as an insulating film of a semiconductor device. However,
With the progress of miniaturization and high integration of elements, the capacitance between wirings has increased to affect the driving force of elements as a circuit. Therefore, there is an increasing demand for an insulating film having a low dielectric constant, and a method for forming such an insulating film having a low dielectric constant is described in Japanese Patent Application No. 5-89891 filed by the present inventors. As described above, when the SiO 2 film is formed by the PE-CVD method, an etching gas containing F atoms (for example, C 2 F 6 , CF 4 , NF 3 , HF, etc.) is added to make the composition SiO x. A method of forming a film that is F y is practiced. This SiO x F y film is formed by, for example, a parallel plate PE-C having a power supply frequency of 13.56 MHz.
TEOS (also called tetraethyl orthosilicate or tetraethoxysilane) 400 cc / min, O 2 400 cc / min, as a product gas using a VD device
C 2 F 6 200 cc / min, RF (Radio Fr
power) 2 W / cm 2 , pressure 10 Tor
r, temperature 350 ° C., distance between electrodes 5 mm. As described above, the C 2 F 6 gas may be another gas containing F.
【0003】このSiOx Fy 膜の比誘電率は3.0〜
3.8であり、PE−CVD法によるSiO2 (以下、
P−SiO2 と記すが、要するにSiO2 の一種であ
る)膜の比誘電率3.9〜5.0と比較すると明らかに
小さく、配線間の容量を低減することができる。The relative dielectric constant of this SiO x F y film is 3.0 to
3.8, and SiO 2 (hereinafter,
Referred to as P-SiO 2, but in short, which is a kind of SiO 2) is clear when compared with the dielectric constant from 3.9 to 5.0 of the film small, it is possible to reduce the capacitance between wirings.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、以上述
べたSiOx Fy なる組成の絶縁膜は、吸湿性が高く、
膜中に多量の水分を吸蔵するため、金属配線の腐食の原
因となるとともに、半導体素子の構成要素の一つである
トランジスタの寿命を劣化させる。However, the above-mentioned insulating film having a composition of SiO x F y has a high hygroscopic property,
Since a large amount of water is occluded in the film, it causes corrosion of the metal wiring and deteriorates the life of the transistor which is one of the constituent elements of the semiconductor element.
【0005】この発明は、以上述べたSiOx Fy 膜が
吸湿性が高く半導体素子の信頼性を損なうという問題を
解消するため、P−SiO2 膜形成時、F原子(以下単
にFと記載)を含むガスを作用させて(後述するように
2通りの方法による)、SiO2 膜とSiOx Fy 膜と
を積層的に形成するようにすることにより、絶縁膜全体
の吸湿性を低減し、信頼性の高い半導体素子を得ること
を目的とする。The present invention solves the above-mentioned problem that the SiO x F y film has a high hygroscopic property and impairs the reliability of the semiconductor element. Therefore, when the P-SiO 2 film is formed, an F atom (hereinafter referred to simply as F) is used. ) Is applied (by two methods as described later) to form the SiO 2 film and the SiO x F y film in a laminated manner, thereby reducing the hygroscopicity of the entire insulating film. The purpose is to obtain a highly reliable semiconductor element.
【0006】[0006]
【課題を解決するための手段】前記目的達成のため、本
発明は絶縁膜(主として層間絶縁膜)形成において、以
下に述べる2通りの方法で、P−SiO2 膜とSiOx
Fy 膜とを積層的な構造とするようにしたものである。In order to achieve the above object, the present invention uses two methods described below in forming an insulating film (mainly an interlayer insulating film) by a P-SiO 2 film and a SiO x film.
The F y film has a laminated structure.
【0007】(1)第1の実施例として、P−SiO2
膜形成中に、Fを含むガスを断続(パルス)的に添加し
て、前記積層構造を形成する。(1) As a first embodiment, P-SiO 2
During the film formation, a gas containing F is intermittently (pulsed) added to form the laminated structure.
【0008】(2)第2の実施例として、P−SiO2
膜を薄く形成した後に、同一装置内でFを含むガスだけ
を流してプラズマ放電し、P−SiO2 膜表面をSiO
x Fy化させ、これを繰り返すことにより、前記積層的
構造とする。(2) As a second embodiment, P-SiO 2
After forming a thin film, only a gas containing F is caused to flow in the same device for plasma discharge, and the surface of the P-SiO 2 film is changed to SiO 2.
It is x F y of, by repeating this, and the laminated structure.
【0009】[0009]
【作用】前述したように、本発明は絶縁膜をP−SiO
2 膜とSiOx Fy 膜との積層構造としたので、吸湿性
の低い(後述するようにSiOx Fy 膜のみの場合の半
分以下)の絶縁膜(勿論、誘電率も従来同様低い)が実
現でき、半導体素子の信頼性の向上が図れる。As described above, according to the present invention, the insulating film is made of P-SiO.
Insulating film with low hygroscopicity (less than half of the case of only SiO x F y film as described later) because of the laminated structure of 2 films and SiO x F y film (of course, the dielectric constant is also low as before) Can be realized, and the reliability of the semiconductor element can be improved.
【0010】[0010]
【実施例】本発明の第1の実施例の絶縁膜形成工程を、
模式的な断面図で図1に、また、その絶縁膜形成の際の
PE−CVD装置内への各種ガス導入のタイミングチャ
ートを図2に示し、以下に説明する。EXAMPLE The insulating film forming process of the first example of the present invention
A schematic cross-sectional view is shown in FIG. 1, and a timing chart for introducing various gases into the PE-CVD apparatus at the time of forming the insulating film is shown in FIG. 2, which will be described below.
【0011】まず、図1(a)に示すように、基板11
を平行平板型PE−CVD装置内にセットし、TEOS
とO2 ガスのみを導入(図2の領域A)し、基板11上
にPE−CVD法によりP−SiO2 膜12を形成す
る。First, as shown in FIG. 1A, the substrate 11
Is set in a parallel plate PE-CVD apparatus, and TEOS
And O 2 gas are introduced (region A in FIG. 2) to form a P-SiO 2 film 12 on the substrate 11 by PE-CVD.
【0012】その後、図1(b)に示すように、前記装
置内で、前記TEOSとO2 ガスが連続して流れている
間に、断続的にC2 F6 (前述したように、このガスは
Fを含む他のガス、例えばCF4 ,NF3 ,HFなどで
もよい)ガスを添加(図2の領域Bに示すように断続的
に添加)することにより、SiOx Fy 膜13を前記P
−SiO2 膜12の上に形成する。Thereafter, as shown in FIG. 1B, while the TEOS and the O 2 gas are continuously flowing in the apparatus, the C 2 F 6 (as described above, The gas may be another gas containing F, such as CF 4 , NF 3 , or HF.) By adding (intermittently adding as shown in region B of FIG. 2) the SiO x F y film 13 is added. The P
It is formed on the —SiO 2 film 12.
【0013】前述したように、C2 F6 ガスは断続的に
導入されるので、該ガスが流れない時点(図2の領域
A)ではP−SiO2 膜12が生成され、図1(c)に
示すように、F−SiO2 膜12とSiOx Fy 膜13
とが交互に形成されていき、結果として前記両膜12と
13との積層構造ができる。As described above, since the C 2 F 6 gas is intermittently introduced, the P-SiO 2 film 12 is formed at the time when the gas does not flow (region A in FIG. 2), and the P-SiO 2 film 12 is generated as shown in FIG. ), The F-SiO 2 film 12 and the SiO x F y film 13 are
Are alternately formed, and as a result, a laminated structure of the both films 12 and 13 is formed.
【0014】図3に本発明の第2の実施例の絶縁膜形成
工程を模式的な断面図で示し、また、その絶縁膜形成時
のガス導入のタイミングチャートを図4に示し、以下に
説明する。FIG. 3 shows a schematic cross-sectional view of an insulating film forming step of the second embodiment of the present invention, and FIG. 4 shows a timing chart of gas introduction at the time of forming the insulating film, which will be described below. To do.
【0015】まず、図3(a)に示すように、基板21
を第1の実施例同様、PE−CVD装置内にセットし
て、TEOSとO2 ガスを導入して(図4の領域C)、
基板21上にP−SiO2 膜22を形成する。First, as shown in FIG. 3A, the substrate 21
Is set in the PE-CVD apparatus as in the first embodiment, TEOS and O 2 gas are introduced (region C in FIG. 4),
A P-SiO 2 film 22 is formed on the substrate 21.
【0016】その後、前記TEOSとO2 ガスの導入を
止めると同時に、C2 F6 ガスを導入してプラズマ放電
する(図4の領域D)。すると、図3(b)に示すよう
に、前記P−SiO2 膜22は若干エッチングされる
が、表面はSiOx Fy 化された層(膜)23となる。
従って、前述したガス導入を図4に示すCとDの領域の
ように交互に繰り返すと、図3(c)に示すように、P
−SiO2 膜22とSiOx Fy 膜23との積層構造が
できる。After that, the introduction of the TEOS and the O 2 gas is stopped, and at the same time, the C 2 F 6 gas is introduced to perform plasma discharge (region D in FIG. 4). Then, as shown in FIG. 3B, the P-SiO 2 film 22 is slightly etched, but the surface becomes a layer (film) 23 made into SiO x F y .
Therefore, when the above-mentioned gas introduction is alternately repeated as in the regions C and D shown in FIG. 4, as shown in FIG.
A laminated structure of the —SiO 2 film 22 and the SiO x F y film 23 is formed.
【0017】以上述べた実施例の方法で、P−SiO2
膜12,22とSiOx Fy 膜13,23との積層構造
を、前記両膜の膜厚比1:1で形成したとき、比誘電率
4.2のP−SiO2 膜と3.0のSiOx Fy 膜を用
いた場合、前記積層膜の比誘電率は約3.5となり、誘
電率の低下は効果として十分である。By the method of the above-mentioned embodiment, P-SiO 2
When a laminated structure of the films 12 and 22 and the SiO x F y films 13 and 23 is formed with a film thickness ratio of the both films of 1: 1, a P-SiO 2 film having a relative dielectric constant of 4.2 and 3.0 When the SiO x F y film is used, the relative dielectric constant of the laminated film is about 3.5, and the reduction of the dielectric constant is sufficient as an effect.
【0018】図5(a)および(b)に、SiOx Fy
膜のみの場合と本実施例の積層膜の場合の、形成直後と
150時間大気に放置させた後とのFTIR(フーリエ
変換赤外分光法:周知のようにこれはスペクトル分析の
代表的な手法である)吸収スペクトルを参考のために示
す。図5(a)に示すように、前記形成直後では、前記
両膜ともにH2 O(即ち水分、波数3400cm-1付
近)、SiOH(3650cm-1付近)のピークは小さ
く膜中に吸蔵された水分は殆どない。大気中に放置され
ている間にともに水分を吸収するが、図5(b)に示す
ように、150時間経過後のスペクトルでは、本実施例
の積層膜の吸湿性がSiOx Fy 膜だけの場合に比べ、
半分以下になっていることが分かる。つまり、本実施例
の積層膜は、誘電率も十分低く、かつ吸湿性も低い絶縁
膜が実現できる。In FIGS. 5A and 5B, SiO x F y is shown.
FTIR (Fourier Transform Infrared Spectroscopy: As is well known, this is a typical method of spectrum analysis, in the case of only the film and in the case of the laminated film of this example, immediately after formation and after being left in the atmosphere for 150 hours. The absorption spectrum is shown for reference. As shown in FIG. 5 (a), immediately after the forming, the both films both H 2 O (i.e. moisture, wavenumber of around 3400 cm -1), the peak of SiOH (3650 cm around -1) occluded in the small film There is almost no water. Both of them absorb water while being left in the atmosphere, but as shown in FIG. 5B, the hygroscopicity of the laminated film of this example is only the SiO x F y film in the spectrum after the lapse of 150 hours. Compared to
You can see that it is less than half. That is, the laminated film of this embodiment can realize an insulating film having a sufficiently low dielectric constant and a low hygroscopicity.
【0019】なお、前述した本実施例では、形成装置と
して平行平板型PE−CVD装置を用いたが、勿論他の
型のPE−CVD装置でも可能であり、また、前述の実
施例でPE−CVD装置でのガス導入の切り替えなどの
方法は特に説明しなかったが、このような手段は同装置
では従来もこの記載以前何年来と行なわれていたことで
あるので、その説明は割愛した。さらに、P−SiO2
膜形成ガスとしては、前述したガス以外のSiH4 とN
2 Oなど他のガスでもよい。さらに蛇足ながら、SiO
2 膜とSiOx Fy 膜とを非連続的に形成しても構わな
いが、形成工程に時間がかかり、実際的ではないであろ
う。Although the parallel plate type PE-CVD apparatus is used as the forming apparatus in the above-described embodiment, it is of course possible to use another type of PE-CVD apparatus. Although the method of switching the gas introduction in the CVD apparatus was not particularly described, such a means has been practiced in the apparatus for many years before this description, so the description thereof is omitted. Furthermore, P-SiO 2
As the film forming gas, SiH 4 and N other than the above-mentioned gases are used.
Other gas such as 2 O may be used. Furthermore, it is SiO
The 2 film and the SiO x F y film may be formed discontinuously, but it is not practical because the forming process takes time.
【0020】[0020]
【発明の効果】以上説明したように、本発明は、絶縁膜
をP−SiO2 膜とSiOx Fy 膜との積層構造とした
ので、吸湿性の低い(SiOx Fy 膜のみの場合の半分
以下)の絶縁膜(勿論、誘電率も従来同様低い)が実現
でき、金属配線の腐食、トランジスタの寿命劣化という
問題点が解消でき、誘電率も低く素子の駆動力も高い信
頼性の高い半導体素子の実現が可能となる。As described above, according to the present invention, since the insulating film has the laminated structure of the P-SiO 2 film and the SiO x F y film, the hygroscopic property is low (in the case of only the SiO x F y film). (Less than half of that of conventional products) (of course, the permittivity is also low as in the past), the problems of corrosion of metal wiring and deterioration of transistor life can be solved, and the permittivity is low and the driving force of the device is high. A semiconductor device can be realized.
【図1】本発明の第1の実施例の形成工程断面模式図FIG. 1 is a schematic sectional view of a forming process according to a first embodiment of the present invention.
【図2】第1の実施例における生成ガスの導入タイミン
グチャートFIG. 2 is a timing chart of introduction of generated gas in the first embodiment.
【図3】本発明の第2の実施例の形成工程断面模式図FIG. 3 is a schematic sectional view of a forming process according to a second embodiment of the present invention.
【図4】第2の実施例における生成ガスの導入タイミン
グチャートFIG. 4 is a timing chart of introduction of generated gas in the second embodiment.
【図5】SiOx Fy と本実施例の積層膜とのFTIR
吸収スペクトル比較図FIG. 5: FTIR of SiO x F y and the laminated film of this example
Absorption spectrum comparison chart
11 基板 12 P−SiO2 膜 13 SiOx Fy 膜11 substrate 12 P-SiO 2 film 13 SiO x F y layer
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/316 X 7352−4M 21/3205 8826−4M H01L 21/88 K ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H01L 21/316 X 7352-4M 21/3205 8826-4M H01L 21/88 K
Claims (3)
とSiOx Fy 膜との積層膜としたことを特徴とする半
導体素子。1. A semiconductor device comprising a laminated film of a SiO 2 film and a SiO x F y film as an insulating film of the semiconductor device.
して、半導体基板を前記絶縁膜を形成するための装置内
にセットして、同装置内にSiO2 膜を形成するガスを
導入し、該ガスを連続して導入している間に、SiOx
Fy 膜を形成するガスを断続的に導入し、前記SiO2
膜とSiOx Fy 膜との積層膜を前記半導体基板上に形
成することを特徴とする半導体素子の製造方法。2. A method of forming an insulating film in a semiconductor device, wherein a semiconductor substrate is set in an apparatus for forming the insulating film, and a gas for forming a SiO 2 film is introduced into the apparatus, and the gas is introduced. During continuous introduction of SiO x
A gas for forming the F y film is intermittently introduced to produce the SiO 2 film.
A method of manufacturing a semiconductor device, comprising: forming a laminated film of a film and a SiO x F y film on the semiconductor substrate.
して、半導体基板を前記絶縁膜を形成するための装置内
にセットして、同装置内にSiO2 膜を形成するガスを
導入し、該ガスの導入を止めると同時に、前記SiO2
膜表面をSiOx Fy 化するガスを導入し、該ガス導入
を止めると同時に再び前記SiO2 膜を形成するガスを
導入する手順を繰り返すことにより、前記SiO2 膜と
該膜の表面が前記手段で化学変化したSiOx Fy 膜と
の積層膜を前記半導体基板上に形成することを特徴とす
る半導体素子の製造方法。3. A method for forming an insulating film in a semiconductor device, wherein a semiconductor substrate is set in an apparatus for forming the insulating film, and a gas for forming a SiO 2 film is introduced into the apparatus, and the gas is used. At the same time stopping the introduction of said SiO 2
By introducing a gas for converting the film surface into SiO x F y , stopping the gas introduction, and at the same time introducing a gas for forming the SiO 2 film again, the SiO 2 film and the surface of the film are A method of manufacturing a semiconductor device, comprising: forming a laminated film with a SiO x F y film chemically changed by means on the semiconductor substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17027493A JP3283344B2 (en) | 1993-07-09 | 1993-07-09 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17027493A JP3283344B2 (en) | 1993-07-09 | 1993-07-09 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0729975A true JPH0729975A (en) | 1995-01-31 |
JP3283344B2 JP3283344B2 (en) | 2002-05-20 |
Family
ID=15901911
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17027493A Expired - Fee Related JP3283344B2 (en) | 1993-07-09 | 1993-07-09 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3283344B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0822585A2 (en) * | 1996-08-02 | 1998-02-04 | Applied Materials, Inc. | Stress control by fluorination of silica film |
US6451686B1 (en) | 1997-09-04 | 2002-09-17 | Applied Materials, Inc. | Control of semiconductor device isolation properties through incorporation of fluorine in peteos films |
JP2009117821A (en) * | 2007-10-18 | 2009-05-28 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device, semiconductor device, and electronic appliance |
-
1993
- 1993-07-09 JP JP17027493A patent/JP3283344B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0822585A2 (en) * | 1996-08-02 | 1998-02-04 | Applied Materials, Inc. | Stress control by fluorination of silica film |
EP0822585A3 (en) * | 1996-08-02 | 1999-01-13 | Applied Materials, Inc. | Stress control by fluorination of silica film |
US6451686B1 (en) | 1997-09-04 | 2002-09-17 | Applied Materials, Inc. | Control of semiconductor device isolation properties through incorporation of fluorine in peteos films |
JP2009117821A (en) * | 2007-10-18 | 2009-05-28 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device, semiconductor device, and electronic appliance |
Also Published As
Publication number | Publication date |
---|---|
JP3283344B2 (en) | 2002-05-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH07312368A (en) | Method to form even structure of insulation film | |
JP3148183B2 (en) | Method for manufacturing semiconductor device | |
JPH06177120A (en) | Deposition of interlayer dielectric film | |
JP3666106B2 (en) | Manufacturing method of semiconductor device | |
JPH11233513A (en) | Method and equipment for manufacturing device using ferroelectric film | |
US6607963B2 (en) | Method for forming capacitor of semiconductor device | |
JPH0729975A (en) | Semiconductor element and its manufacture | |
JPH0831825A (en) | Production of semiconductor device | |
US6169023B1 (en) | Method for making semiconductor device | |
JPH0817174B2 (en) | Method of modifying insulating film | |
JP2001077192A (en) | Semiconductor device and manufacture thereof | |
JPH05121572A (en) | Manufacture of semiconductor device | |
JPH07161705A (en) | Method of forming interlayer insulating film of multilayered wiring of semiconductor device | |
JP4986661B2 (en) | Insulating film forming method and semiconductor device using the same | |
JPH0897199A (en) | Forming method for insulating film | |
KR100253578B1 (en) | Method of manufacturing planation layer of semiconductor device | |
JPS62172732A (en) | Manufacture of semiconductor device | |
KR100459686B1 (en) | Fabrication method of contact hole for semiconductor device | |
JPH08203890A (en) | Formation of interlayer insulation film in semiconductor device | |
JP4986660B2 (en) | Insulating film forming method and semiconductor device using the same | |
JPH08321499A (en) | Silicon compound film and forming method thereof | |
JP4250209B2 (en) | Manufacturing method of semiconductor device | |
JPH05198690A (en) | Manufacture of semiconductor device | |
JPH07221176A (en) | Method of manufacturing semiconductor device | |
JP3373705B2 (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20020219 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080301 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090301 Year of fee payment: 7 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090301 Year of fee payment: 7 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100301 Year of fee payment: 8 |
|
LAPS | Cancellation because of no payment of annual fees |