JPH07298638A - Output circuit for pwm inverter - Google Patents

Abstract

PURPOSE:To provide a low-cost output circuit for a PWM inverter with low power consumption and a small voltage control error at a winding terminal of a motor. CONSTITUTION:In an output circuit, a current control means 1 includes an N-ch junction FET, a P-ch junction, FET and a current output terminal. At the same time, a current control means 2 with a current input terminal is provided. A current from the current output terminal of the current control means 1 and an input current to the input terminal of the current control means 2 are controlled in a given method so as to control the N-ch junction FET and the P-ch junction FET.

Description

Detailed Description of the Invention

[0001]

The present invention relates to the coil voltage of an electric motor,
The present invention relates to a power circuit of a PWM inverter for WM control.

PWM is a Pulse Width Mo
The abbreviation of "duration" is a technique widely used in the field of motor control.

[0003]

2. Description of the Related Art In recent years, PWM inverters have rapidly spread and are widely used for motor control.

FIG. 12 is a schematic diagram showing the structure of a general PWM inverter, and shows a three-phase PWM inverter as an example. Generally, in the PWM inverter, the number of output circuits 53 for the PWM inverter differs depending on the number of phases of the motor used, but the basic operation is the same.

The configuration of a general three-phase PWM inverter will be described with reference to FIG. First, the frequency voltage setting means 58
The basic frequency and the effective voltage value of the three-phase AC voltage waveform supplied to the electric motor 60 are set at. Next, the PWM control circuit 59
Generates a three-phase PWM signal internally based on the information set in the frequency voltage setting means 58 and outputs it as switching command signals 42, 61 and 62. The switching command signals 42, 61 and 62 are applied to the motor winding terminal 5
It is a binary signal for instructing whether 2, 63 and 64 are connected to the positive terminal or the negative terminal of the DC main power supply 14, respectively. The frequency of the switching command signal 42, 61, or 62 is called the PWM carrier frequency, and takes a value 10 times or more the basic frequency of the three-phase AC voltage waveform normally supplied to the electric motor 60. Generally, the fundamental frequency of the three-phase AC voltage waveform supplied to the motor is about 0 Hz to 200 Hz, and the PWM carrier frequency is 2 kHz.
Many are about -20 kHz. Motor release signal 156
Command whether to put the motor in the free-run state 2
It is a value signal. What is a free run state? Motor winding terminal 5
It is general to protect the electric motor and the control device by setting this state in the case where some trouble occurs in a state in which all 2, 63 and 64 are not connected to the positive terminal or the negative terminal of the DC main power supply 14. is there. PWM
The output circuit 53 for the inverter uses the switching command signal 4
Motor winding terminal 5 according to 2 or 61 or 62
This is a semiconductor switch circuit for controlling connection of 2 or 63 or 64 to the positive or negative terminal of the DC main power supply 14. When the motor release signal 156 commands the free-run state, the motor winding terminal 52 or 63 or 64 is also applied to the plus terminal of the DC main power source 14 regardless of the switching command signal 42, 61 or 62. It is configured not to connect to the terminals either. Generally, the main DC power supply is DC1 which is rectified and smoothed AC100V.
About 40V or DC with rectified and smoothed AC200V
Most of them are about 280V.

A conventional output circuit for a PWM inverter will be described below. FIG. 13 shows the configuration of a conventional PWM inverter output circuit.

In FIG. 13, a logic inverting means 65 inverts the positive / negative logic of the switching command signal 42 and outputs an inverted switching signal 80. 157 and 158 are AND means, which are the motor release signal 156 and the switching command signal 4
The result of logical product of 2 is the upper arm switching signal 1
59, and the result of taking the logical product of the motor release signal 156 and the inverted switching signal 80 is output as the lower arm switching signal 160. On-delay circuits 66 and 67 delay the rising edges of the upper arm switching signal 159 and the lower arm switching signal 160 by the on-delay time TD and output the upper arm control signal 81 or the lower arm control signal 82. 68 and 69 are base drive circuits, and 68 is a power transistor 70 which is turned on or off in response to the upper arm control signal 81.
FF, and 69 is configured to turn on or off the power transistor 71 in response to the lower arm control signal 82. That is, when the upper arm control signal 81 becomes the “H” level, the output transistor of the photocoupler 72 is turned on, which turns on the transistor 74, which turns off the transistor 76, turning on the power transistor 70. On the contrary, when the upper arm control signal 81 becomes the “L” level, the output transistor of the photocoupler 72 is turned off, which causes the transistor 74 to be turned off.
The power transistor 70 is turned off when the transistor 76 is turned on.

[0008] This base drive circuit is also used in the actual development 5
There are those disclosed in Japanese Patent Application Laid-Open No. 7-42589 and Japanese Patent Application Laid-Open No. 59-178980, but basically they can be replaced by performing the same operation as the base drive circuits 68 and 69 shown in FIG.

The operation of the PWM inverter output circuit configured as described above will be described below.

First, considering the case where the motor release signal 156 is instructing the "L" level, that is, the free running state, the power transistor 70 and the power transistor 70 are in both the "L" level and the "H" level of the switching command signal 42. It can be seen that 71 is in the OFF state.

Hereinafter, a case where the motor release signal 156 commands the "H" level, that is, the state where the motor is not free running will be described.

FIG. 14 is a diagram showing signals inside the output circuit for the PWM inverter of FIG. 13. First, when the switching command signal 42 changes from the "L" level to the "H" level,
The on-delay circuit 66 changes the upper arm control signal 81 from the “L” level to the “H” level with a delay of the on-delay time TD. The power transistor 70 is turned on when the upper arm control signal 81 is set to the “H” level, but the base drive circuit 68 and the power transistor 70 are in between.
Operation delay time TX1 exists. This operation delay time T
X1 varies depending on the temperature of the power transistor 70 and changes in the value of the current flowing through the collector, and also changes due to variations in components forming the base drive circuit and power transistors, and changes over time.

Further, the switching command signal 42 is'L '.
When the level changes to the'H 'level, the inverted switching signal 80 changes from the'H' level to the'L 'level,
The on-delay circuit 67 sets the lower arm control signal 82 to the'L 'level with almost no time delay. When the lower arm control signal 82 is set to the “L” level, the power transistor 71
Is turned off, but there is an operation delay time TY2 of the base drive circuit 69 and the power transistor 71 in the meantime. This operation delay time TY2 depends on the power transistor 71.
Fluctuates due to changes in the temperature of the
It also changes due to variations and aging of the components that make up the base drive circuit and power transistors.

Next, when the switching command signal 42 changes from the "H" level to the "L" level, the on-delay circuit 66 sets the upper arm control signal 81 to the "L" level with almost no time delay, and the power transistor 70 is turned off. However, there is an operation delay time TY1 of the base drive circuit 68 and the power transistor 70 between them.

Further, the switching command signal 42 is "H".
When the level changes to the'L 'level, the inverted switching signal 80 changes from the'L' level to the'H 'level,
The on-delay circuit 67 changes the lower arm control signal 82 from the “L” level to the “H” level with a delay of the on-delay time TD. When the lower arm control signal 82 is set to the'H 'level, the power transistor 71 is turned on, but there is an operation delay time TX2 between the base drive circuit 69 and the power transistor 71 in the meantime.

When the operation delay time TX1 or the operation delay time TX2 is compared with the operation delay time TY1 or the operation delay time TY2, the operation delay time TY1 or TY2 is generally longer than the operation delay time TX1 or TX2. Tend. The shortest value of the operation delay time TX1 and the operation delay time TX2 considering the worst condition is TXW, and the operation delay time TY1 and the operation delay time T are set.
When the longest value of Y2 in consideration of the worst condition is TYW, the normal on-delay time TD is set to a value obtained by subtracting TXW from TYW with some margin.
Normally, the on-delay time TD is set to about 10 to 50 microseconds using a bipolar type power transistor, and is set to about 5 to 30 microseconds using an IGBT.
-Using FET, it is set to about 2 to 10 microseconds. As a result, when the switching command signal 42 changes from the “H” level to the “L” level or from the “L” level to the “H” level, the power transistor 70 and the power transistor 71 are turned on at the same time. The positive terminal and the negative terminal of the power supply 14 are prevented from being short-circuited.

From the above, considering the switching command signal 42 and the state of the motor winding terminal voltage 51,
First, when the switching command signal 42 is fixed at the “L” level, the power transistor 70 is in the OFF state and the power transistor 71 is in the ON state, so the motor winding terminal 52 is connected to the negative terminal of the DC main power supply 14. In addition, when the switching command signal 42 is fixed at the "H" level, the power transistor 7
Since 0 is ON and the power transistor 71 is OFF, the motor winding terminal 52 is connected to the positive terminal of the DC main power supply 14.

[0018]

However, in the above-mentioned conventional configuration, when the motor release signal 156 is instructing the "H" level, that is, the state in which the motor is not free running, the switching command signal 42 changes from the "L" level to the "L" level. When the H'level is changed or the'H 'level is changed to the'L' level, both the power transistor 70 and the power transistor 71 are turned off for a certain period of time, which causes voltage control of the motor winding terminal 52. Control error. This control error has a problem in that it causes fluctuations in torque and rotational speed of the electric motor, and also increases noise and vibration of the electric motor.

This will be described in more detail. 13 and 14, the switching command signal 42 is'L '.
When the level changes to the “H” level or when the “H” level changes to the “L” level, the power transistor that has been turned on is first turned off and then the power transistor that has been turned off is turned on. Therefore, both the power transistor 70 and the power transistor 71 are turned off for a certain period of time. This state is called a floating state, and this time is called a floating time TZ. Generally, the floating time TZ is often about 1/2 to 2/3 of the on-delay time TD.

Generally, the PWM control of an electric motor is essentially such that the electric motor winding terminals are alternately connected to the positive terminal and the negative terminal of the DC main power supply, and the ratio of the time for connecting to the positive terminal to the time for connecting to the negative terminal is set. Accordingly, the average voltage of the motor winding terminals is controlled. Therefore,
It is ideal that the average voltage of the motor winding terminal 52 can be uniquely controlled according to the time ratio of the “H” level and the “L” level of the switching command signal 42 when the voltage of the DC main power supply 14 is constant. Is.

However, in the conventional output circuit for the PWM inverter, since the floating state exists, the average voltage of the motor winding terminal varies depending on the direction of the current flowing through the motor winding terminal. That is, the motor winding terminal 5
The diode 78 becomes conductive when the current is flowing in the direction in which the current flows into the PWM inverter output circuit 53 from 2 and the motor winding terminal 52 is connected to the positive terminal of the DC main power supply 14. Becomes
This state is shown by the motor winding terminal voltage 51A in FIG.
On the contrary, when current flows from the PWM inverter output circuit 53 to the electric motor winding terminal 52 in the floating state, the diode 79 conducts and the electric motor winding terminal 52 is connected to the negative terminal of the DC main power supply 14. It will be in the state of being. This state is shown in the motor winding terminal voltage 51B of FIG. Further, in the floating state, when no current flows in the motor winding terminal 52, the voltage of the motor winding terminal 52 becomes a voltage determined by the induced voltage generated inside the motor 60.

As described above, the switching command signal 42 and the motor winding terminal 52 are present because of the floating state.
The average voltage of is not uniquely determined and causes a control error. Normally, the current flowing through the motor winding terminal 52 is an alternating current, and the direction of the current changes. Therefore, the control error also changes accordingly, and the torque generated or the rotation speed of the motor 60 fluctuates. Although this problem can be solved by eliminating the floating state and setting the floating time to 0, in the conventional output circuit for the PWM inverter, a short-circuited state between the plus terminal and the minus terminal of the DC main power supply 14 occurs, which is actually impossible. is there.

Further, electric noise is generated when the power transistor is turned on or off, and particularly in applications where it is desired to reduce this, the switching speed is slowed by connecting a capacitor between the base and emitter of the power transistor. There are cases. However, this causes the operation delay times TX1, TX2, TY1 and TY2.
The fluctuations in the above will become extremely large, and the floating time will have to be further increased. Therefore, the control error becomes large, and as a result, the switching speed cannot be reduced so much.

Further, the power transistor 70 and the power transistor 71 in FIG. 13 are respectively power MOS-FE.
There is a conventional PWM inverter output circuit in which T is replaced with T, and a conventional PWM inverter output circuit in which the power transistor 70 and the power transistor 71 in FIG. 13 are respectively replaced with IGBTs, but the operation is completely shown in FIG. It is the same as the output circuit for the PWM inverter and has a floating state.

An object of the present invention is to solve the above-mentioned problems. The floating state is essentially eliminated, the floating time is zero, and the switching command signal and the average voltage of the motor winding terminals are uniquely determined. Accordingly, it is an object of the present invention to provide a PWM inverter output circuit that does not cause a control error and consumes less power at low cost.

[0026]

To achieve this object, an output circuit for a PWM inverter according to the present invention comprises an N-channel type first junction type FET and a P-channel type second junction type FET. 1st, 2nd, 5th and 6th
A diode, a current control means 1 having a current output terminal for controlling a current flowing out from the current output terminal, a current control means 2 having a current input terminal for controlling a current flowing in from the current input terminal, A direct current main power source, a third direct current power source in which a negative terminal is connected to the positive terminal of the direct current main power source, and a fourth direct current power source in which a positive terminal is connected to the negative terminal of the direct current main power source; Connecting the drain of the FET of the first type, the cathode of the first diode and the positive terminal of the DC main power source, and connecting the drain of the second junction type FET, the anode of the second diode and the negative terminal of the DC main power source, The source of the first junction type FET, the anode of the first diode, the source of the second junction type FET and the cathode of the second diode are connected to each other, and the first junction type F
The gate of ET, the gate of the second junction FET, the current output terminal of the current control means 1, the current input terminal of the current control means 2, the anode of the fifth diode and the cathode of the sixth diode are connected, The positive terminal of the third DC power supply is connected to the cathode of the fifth diode, the negative terminal of the fourth DC power supply is connected to the anode of the sixth diode, and the gate of the first or second junction-type FET is connected. The current control means 1 and the current control means 2 have a configuration in which a resistor is connected between the sources, and the current flowing out from the current output terminal of the current control means 1 is defined as a first current value. In the first state where the current flowing in from the current input terminal is the seventh current value, and the current flowing out from the current output terminal of the current control means 1 is the second current value. A second state in which the current flowing from the child has an eighth current value, and a current flowing out from the current output terminal of the current control means 1 has a fifth current value and flows from the current input terminal of the current control means 2. The third state in which the current to be applied is the third current value, and the current flowing out from the current output terminal of the current control means 1 is the sixth current value, and the current flowing in from the current input terminal of the current control means 2 is A fourth state in which a fourth current value is set, and a current flowing out from the current output terminal of the current control unit 1 is set as a ninth current value, and the current control unit 2 is set.
Has a fifth state in which the current flowing in from the current input terminal is also the ninth current value, the first current value is a current value larger than the seventh current value, and the second current value is Is greater than the eighth current value, the third current value is greater than the fifth current value, and the fourth current value is greater than the fifth current value.
The current value of is larger than the sixth current value,
The difference between the first current value and the seventh current value is made larger than the difference between the second current value and the eighth current value,
The difference between the current value and the fifth current value is larger than the difference between the fourth current value and the sixth current value, and only the second state and the fifth state are shifted from the first state. Possible, and it is possible to transition from the second state to only the third state and the fifth state,
Only the fourth state and the fifth state can be shifted from the third state, only the first state and the fifth state can be shifted from the fourth state, and at least the fifth state can be shifted from the fifth state. The configuration is such that it is possible to shift to the first state and the third state.

[0027]

With this configuration, the first and second junction type FETs are essentially safe from being simultaneously turned on, and the floating time is essentially zero, so that the control error is very small, and A PWM inverter output circuit with low power consumption can be realized.

[0028]

【Example】

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 1 is an N-channel type junction FET, and 2 is a P-channel type junction FE.
T, 3, 4, 5 and 6 are diodes, 125 and 1
26 is a current control means, 109 is a signal processing means, 105 is a resistor, 14 is a DC main power supply, 15, 16, 17 and 18
Is a DC power supply, and the output voltages of the DC power supplies 17 and 18 are determined by the Zener voltages of the Zener diodes 36 and 37.

The operation of the PWM inverter output circuit configured as described above will be described.

Numeral 65 is a logic inverting means, which is the result of logically inverting the switching command signal 42 and an inverting switching signal 8
Output as 0.

Numerals 106 and 107 are logical product negating means.
6 is a motor release signal 156 and an inverted switching signal 80
The result of taking the logical product NOT of is output, and 107 outputs the result of taking the logical product NOT of the motor release signal 156 and the switching command signal 42.

For simplification of explanation, all the cases in which the motor release signal 156 is instructing the "H" level, that is, the state where the motor is not free running, will be described. Finally, the motor release signal 156 will be "L". I will add a description of the case where the level, that is, the free-run state is commanded.

First, the operations of the current control means 125 and the current control means 126 will be described in detail with reference to FIG.

The base signal 123 of the PNP type transistor 119 causes the switching command signal 42 to be generated through the logical product negating means 107, the photocoupler 115 and the logical inverting means 111. The base signal 123 has, for example, the same potential as the plus terminal of the DC power supply 15 when the switching command signal 42 is at the “L” level, and has a potential 5 V lower than the plus terminal of the DC power supply 15 when at the “H” level.

Next, a P-channel type MOS-FE
The gate signal 124 of T120 is the switching command signal 4
2 is generated through the logical product negating means 107, the photocoupler 115, the logical inverting means 112 and 113, and the signal delay means 114. The gate signal 124 is obtained by delaying the switching command signal 42 by the delay time TA,
The "L" level is a voltage that can turn on the MOS-FET 120 sufficiently, and the "H" level is a MOS-FE.
The voltage is set so that T120 can be sufficiently turned off.

The transistor 119 has an emitter follower type circuit configuration, and the potential of the base signal 123 is the DC power supply 1.
When it becomes lower than the potential of the positive terminal of No. 5 by about 0.7 V or more, a current determined by the value of the resistor connected to the emitter and the voltage applied thereto flows as a collector current 49, and the potential of the base signal 123 and the DC power supply 15 are reduced. When the difference from the positive terminal potential is about 0.7 V or less, the collector current 49 becomes zero.

The MOS-FET 120 is the transistor 11
When the MOS-FET 120 is turned on in the state where the potential of the base signal of the transistor 119 is lower than the potential of the plus terminal of the DC power source 15 by about 0.7 V or more, it functions to switch the value of the resistor connected to the emitter of the transistor 9. It has the effect of increasing the collector current 49 of the transistor 119.

Considering the relationship between the switching command signal 42 and the collector current 49, the collector current 49 is 0 when the switching command signal 42 is at the “L” level.
Then, until the delay time TA elapses after the switching command signal 42 changes to the “H” level, the collector current 4
9 has a relatively large current value, then has a relatively small current value, and when the switching command signal 42 becomes the'L 'level, the collector current 49 becomes zero.

Further, the base signal 45 of the NPN type transistor 29 causes the switching command signal 42 to be generated through the logical inversion means 65 and 23 and the logical product negation means 106. The base signal 45 is substantially the same as the signal obtained by logically inverting the switching command signal 42, and the value of the'L 'level is 0V and the value of the'H' level is 5V, for example.

Next, N-channel type MOS-FE
The gate signal 46 of T31 converts the switching command signal 42 to the logical inversion means 65, 24 and 25 and the logical product negation means 1.
06 through the signal delay means 27.

The gate signal 46 is obtained by delaying the switching command signal 42 by the delay time TB. The "L" level is a voltage that can sufficiently turn off the MOS-FET 31, and the "H" level is a MOS-FET 31. Is a voltage that can sufficiently turn on.

The transistor 29 has an emitter follower type circuit configuration, and when the base signal 45 becomes about 0.7 V or more, a collector current 48 determined by the voltage of the base signal 45 and the value of the resistance connected to the emitter flows, and the base signal 45. Is about 0.7 V or less, the collector current 48 becomes zero. The MOS-FET 31 has a function of switching the value of the resistor connected to the emitter of the transistor 29. When the base signal of the transistor 29 is about 0.7 V or more, the MOS-FET 31 is a MOS.
When the FET 31 is turned on, it has the effect of increasing the collector current 48 of the transistor 29.

Considering the relationship between the switching command signal 42 and the collector current 48, the collector current 48 is 0 when the switching command signal 42 is at the “H” level.
Then, until the delay time TB elapses after the switching command signal 42 changes to the “L” level, the collector current 4
8 has a relatively large current value, and then has a relatively small current value. When the switching command signal 42 reaches the'H 'level, the collector current 48 becomes zero.

When these are arranged, the collector current 49 becomes the first current value 1 in accordance with the switching command signal 42.
64 and the collector current 48 has a seventh current value 170, and the collector current 49 has a second current value 165.
And the collector current 48 is the eighth current value 171
And the third state in which the collector current 49 has the fifth current value 168 and the collector current 48 has the third current value 166, and the collector current 49 has the sixth current value 169 and the collector current 48 has the fourth value. It can be seen that there is a fourth state in which the current value is 167, and the fourth state is repeatedly realized in order from the first state.

However, in this embodiment, the fifth current value 168, the sixth current value 169, the seventh current value 170 and the eighth current value 171 are set to 0.

The above is the description of the operation of the current control means 125 and 126. The diode 3 functions to limit the upper limit of the collector voltage of the transistor 119 so that the transistor 119 of the current control means 125 is not saturated at least when the second current value 165 is flowing, and at the same time, the junction FETs 1 and 2 are connected. It works to limit the upper limit of the gate voltage of.

The diode 4 functions to limit the lower limit of the collector voltage of the transistor 29 so that the transistor 29 of the current control means 126 is not saturated at least when the fourth current value 167 is flowing, and at the same time, the junction type. It works to limit the lower limit of the gate voltage of FETs 1 and 2.

The upper limit of the gate voltage of the junction FETs 1 and 2 is a voltage at which the junction FET 1 can be sufficiently turned on, and a voltage at which the junction FET 2 can be sufficiently turned off, and the upper limit of the junction FETs 1 and 2. It must be a value that does not exceed the breakdown voltage between the gate and source. In addition, bonded FE
The lower limit of the gate voltage of T1 and T2 is a voltage at which the junction FET2 can be sufficiently turned on and a voltage at which the junction FET1 can be sufficiently turned off, and the junction FET1 and 2
It is necessary to use a value that does not exceed the withstand voltage between the gate and the source.

Generally, N-channel type junction FE
The breakdown voltage between the gate and the source of T is often about ± 20 V to ± 30 V, and the gate voltage threshold for starting conduction between the drain and the source is +1 V to + with reference to the source voltage.
Most of them are about 5V. On the other hand, the breakdown voltage between the gate and source of the P-channel type junction FET is ± 20 V to ± 30.
Most of them are about V, and the gate voltage threshold for starting conduction between the drain and the source is -1 with respect to the source voltage.
Most of them are about V to -5V.

Here, the relationship between the switching command signal 42 and the gate signal voltage 50 based on the negative terminal of the DC main power supply 14 is shown in FIG. First, when the switching command signal 42 changes from the “L” level to the “H” level, the collector current 49 of the transistor 119 flows, the gate signal voltage 50 suddenly rises, and the voltage is fixed when the diode 3 becomes conductive. The rising time TR required for the gate signal voltage 50 to rise is determined by the relationship between the capacitances contained in the junction FETs 1 and 2, the diodes 3 and 4, and the collector current 49. Further, since the gate signal voltage 50 does not change significantly when the diode 3 is conducting, the collector current 49 can be maintained at that voltage even if it is a very small current, and is actually set to be equal to or higher than the current value flowing through the resistor 105. It is enough. Therefore, if the delay time TA of the signal delay means 114 is set to be slightly larger than the rising time TR, the rising time TR can be made small and the power loss of the transistor 119, the resistor 122 and the like can be minimized.

Next, the switching command signal 42 is "H".
When the level changes to'L 'level, transistor 2
The collector current 48 of 9 flows and the gate signal voltage 50 suddenly drops, and the voltage is fixed when the diode 4 becomes conductive. The time TF required for the gate signal voltage 50 to fall is determined by the relation between the collector current 48 and the electrostatic capacitance contained in the junction FETs 1 and 2, the diodes 3 and 4, and the like. Further, since the gate signal voltage 50 does not change greatly when the diode 4 is conducting, the voltage can be maintained even if the collector current 48 is a very small current, and is actually set to be equal to or higher than the current value flowing through the resistor 105. It is enough. Therefore, if the delay time TB of the signal delay means 27 is set to be slightly larger than the fall time TF, the fall time TF can be made small and the power loss of the transistor 29, the resistor 35, etc. can be minimized.

Next, the operation of the junction FETs 1 and 2 will be described. Since the gates and sources of the junction FETs 1 and 2 are commonly connected, when the gate signal voltage 50 becomes higher than the motor winding terminal voltage 51 by the gate voltage threshold value of the junction FET 1 or more, the junction FET 1 changes from the drain to the source. Current starts to flow toward the gate side, and conversely, the gate signal voltage 50 is higher than the motor winding terminal voltage 51 than the junction type FET2.
When it becomes lower than the gate voltage threshold value of, the junction type FET 2 starts to flow current from the source to the drain. Therefore, the gate signal voltage 50 and the motor winding terminal voltage 51
The potential difference between the two is always within a certain range, and the junction type FET
It is essentially impossible for 1 and 2 to simultaneously pass current and short-circuit the positive and negative terminals of the DC main power supply 14.

Next, Zener diodes 95 and 96
The function of is explained. Considering the potential difference between the gate signal voltage 50 and the motor winding terminal voltage 51, it is always within a certain range in the normal operation as described above.
When it is instantly directly connected to the positive terminal or the negative terminal of No. 4, it becomes a very large value, and there is a possibility of exceeding the breakdown voltage between the gate and the source of the junction type FETs 1 and 2 and causing breakdown. If this protection is needed, Zener diodes 95 and 96 are needed.
The Zener voltages of 5 and 96 are applied to the junction FETs 1 and 2
It can be protected by selecting the breakdown voltage between the gate and the source of the above.

Next, the functions of the diodes 5 and 6 will be described. Generally, a simple equivalent circuit of a motor winding is expressed as a resistance, an inductance, and a voltage source corresponding to an induced voltage connected in series. Therefore, unlike the pure resistance load, the direction of the current flowing through the motor winding terminal 52 is not uniquely determined by the voltage applied to the motor winding terminal 52, and the junction FET 1 is ON and the junction FET 2 is OF.
In the state of F, where current is flowing from the motor winding terminal 52 to the motor, and when the junction FET1 is ON and the junction FET2 is OFF, current flows from the motor to the motor winding terminal 52. B state and junction type FET1 is O
FF and the junction type FET2 is ON, and the current is flowing from the motor to the motor winding terminal 52 in the state of C, and the junction type FET1 is OFF, the junction type FET2 is ON, and the motor winding terminal 52 is the motor. Current is flowing to D
Has four states. First, in the state A, the current flowing through the motor winding terminal 52 is the junction type FET1.
You can see that it flows through. Further, in the state of C, it can be seen that the current flowing through the motor winding terminal 52 flows through the junction FET 2. Further, regarding the state B and the state D, it can be seen that the current flowing through the motor winding terminal 52 flows through the diode 5 and the diode 6, respectively. Here, it can be seen that the motor winding terminal voltage 51 in the state of B rises due to the current flowing through the motor winding terminal 52 and is fixed when the diode 5 becomes conductive.

If the reverse recovery time trr of the diode 5 is long, switching loss increases. Therefore, it is preferable to select the diode 5 having a short reverse recovery time as much as possible.

Similarly, the motor winding terminal voltage 51 in the D state is lowered by the current flowing through the motor winding terminal 52, and is fixed when the diode 6 becomes conductive.

If the reverse recovery time trr of the diode 6 is long, switching loss increases. Therefore, it is preferable to select the diode 6 having a short reverse recovery time as much as possible.

From the above description, the switching command signal 4
It can be seen that when 2 is set to the'H 'level, the motor winding terminal 52 is connected to the plus terminal of the DC main power supply 14. Further, when the switching command signal 42 is set to the “L” level, the motor winding terminal 52 is connected to the negative terminal of the DC main power supply 14, and when the switching command signal 42 is changed from the “H” level to the “L” level, It can be seen that the floating time is essentially 0 even when the level is changed from the “L” level to the “H” level.

Further, by changing the collector current 49 of the transistor 119 and the collector current 48 of the transistor 29, the rising time T of the gate signal voltage 50 is changed.
R and the fall time TF can be freely set within a certain range, and accordingly, the rise time and the fall time of the motor winding terminal voltage 51 can be freely set within a certain range. Normally, the motor winding terminal voltage is 5
The smaller the rise time and fall time of 1
Although this is preferable because the power loss of the ET1 and the junction type FET2 can be reduced, it has a drawback that electric noise increases. Therefore, it is necessary to increase the rising time and the falling time of the motor winding terminal voltage 51 for the purpose of reducing the electrical noise, and the configuration can easily cope with this.

Further, it goes without saying that the rise time and fall time of the motor winding terminal voltage 51 can be significantly lengthened by connecting a capacitor between the gate and source of the junction FETs 1 and 2 in FIG.

The above is the description of the operation of the current control means 125 and 126 when the electric motor release signal 156 is in the “H” level, that is, the state in which the electric motor is not free running. A description will be added to the operation of the current control means 125 and 126 when the "L" level, that is, the free-run state is instructed.

When the motor release signal 156 is at the "L" level, that is, when the free run state is commanded, the output signals of the AND gates 106 and 107 are both at the "H" level regardless of the switching command signal 42. Therefore, the base signal 123 of the PNP type transistor 119 becomes the “H” level and the base signal 45 of the transistor 29 becomes the “L” level.

This state is the so-called fifth state, which is the ninth current value of the collector current 49 and the collector current 48.
Are both 0.

In the fifth state, the gate signal voltage 50 of the junction type FETs 1 and 2 becomes almost the same potential as the electric motor winding terminal voltage 51 by the resistor 105. Therefore, the junction FETs 1 and 2 are both turned off, and the free run state can be realized. The fifth state is mainly used to interrupt the operation of the electric motor and protect the electric motor and the control device when some trouble occurs. The transition to the fifth state is possible from any of the first state, the second state, the third state and the fourth state, and the motor release signal 156 changes to the'L 'level. Transition to the moment. On the contrary, the fifth state is configured to shift to the first state or the third state at the moment when the electric motor release signal 156 changes to the “H” level. This is because when the fifth state shifts to the second state or the fourth state, the time required for raising or lowering the gate signal voltage 50 becomes extremely long, and the junction FETs 1 and 2 generate excessive heat. Is a preventive measure. However, the transition from the fifth state to another state is mainly for the purpose of restarting the operation of the suspended electric motor, and in this case, the frequency is at most once every few seconds. Therefore, if the junction FETs 1 and 2 have sufficient withstand voltage, the fifth
It is also possible to adopt a configuration capable of shifting from the state of to all other states.

The current control means 125 and 126 of this embodiment have the fifth current value 168 and the sixth current value 16 respectively.
9, the seventh current value 170 and the eighth current value 171 to 0
However, the first current value 164 is equal to the seventh current value 17
The current value is larger than 0, and the second current value 165 is the eighth value.
Current value 171 is larger than the current value 171 and the third current value 166 is larger than the fifth current value 168.
The fourth current value 167 is set to a larger current value than the sixth current value 169, and the first current value 164 and the seventh current value 170
Is larger than the difference between the second current value 165 and the eighth current value 171 and the third current value 166 and the fifth current value 168 are
Is larger than the difference between the fourth current value 167 and the sixth current value 169, the fifth current value 168 and the sixth current value 1
It goes without saying that the 69, the seventh current value 170, and the eighth current value 171 can be values other than zero.

FIG. 2B shows an example thereof. Further, the current control means 125 and 126 of the present embodiment also set the ninth current value in the fifth state to 0, but it goes without saying that the ninth current value can be a value other than zero.

That is, if the collector current 49 of the transistor 119 and the collector current 48 of the transistor 29 have the same current value, they can be values other than zero.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

In FIG. 4, reference numeral 1 is an N-channel type junction FET, and 2 is a P-channel type junction FE.
T, 3, 4, 5 and 6 are diodes, 126 is current control means, 109 is signal processing means, 14 is a DC main power supply, 1
5, 16, 17, and 18 are DC power supplies, and 105 is a resistor. The above is the same as the configuration of FIG.

The difference from the configuration of FIG. 1 is that the current control means 1
25 is composed of a current mirror means 98 and a current control means 127.

The operations of the current mirror means 98 and the current control means 127, which are different from the configuration of FIG. 1, in the output circuit for the PWM inverter configured as above will be described.

In order to simplify the explanation, all the cases where the motor release signal 156 is instructing the "H" level, that is, the state where the motor is not free running will be described.
Finally, a description will be added to the case where the motor release signal 156 commands the “L” level, that is, the free-run state.

First, the operation of the current control means 127 will be described in detail with reference to FIG. NPN type transistor 2
The base signal 43 of 8 causes the switching command signal 42 to be generated through the logical product negating means 107 and the logical inverting means 20. The base signal 43 is substantially the same as the switching command signal 42, and it is assumed that the'L 'level takes a value of 0V and the'H' level takes a value of 5V, for example. Next, the gate signal 44 of the N-channel type MOS-FET 30 causes the switching command signal 42 to be generated through the logic inverting means 21 and 22, the logical product negating means 107 and the signal delay means 26. The gate signal 44 is obtained by delaying a signal obtained by logically inverting the switching command signal 42 by a delay time TA, and sets the “L” level to a sufficient OF of the MOS-FET 30.
Set the voltage to F and set the'H 'level to MOS
-Use a voltage that can sufficiently turn on the FET 30. The transistor 28 has an emitter follower type circuit configuration, and when the base signal 43 becomes about 0.7 V or more, a collector current 47 determined by the voltage of the base signal 43 and the value of the resistance connected to the emitter flows, and the base signal 43 becomes about 0. .7
When the voltage is V or less, the collector current 47 becomes zero. MOS
The -FET 30 functions to switch the value of the resistance connected to the emitter of the transistor 28, and when the base signal of the transistor 28 is about 0.7 V or higher, the MOS-FET 3
When 0 is turned on, the collector current 47 of the transistor 28 is increased.

Considering the relationship between the switching command signal 42 and the collector current 47, the collector current 47 is 0 when the switching command signal 42 is at the “L” level.
Then, until the delay time TA elapses after the switching command signal 42 changes to the “H” level, the collector current 4
7 has a relatively large current value, and then has a relatively small current value. When the switching command signal 42 becomes the'L 'level, the collector current 47 becomes zero.

The above is the description of the operation of the current control means 127. Next, the function of the current mirror means 98 will be described.

The resistors 11 and 12 and the transistors 9 and 10 have a current mirror configuration with each other, and serve to make the collector current 49 of the transistor 9 a current corresponding to the collector current 47 of the transistor 28 in a range where the transistor 9 is not saturated. .

The diode 3 limits the upper limit of the collector voltage of the transistor 9 so that the transistor 9 is not saturated at least when the second current value 165 is flowing.

Considering the relationship between the switching command signal 42 and the collector current 49 of the transistor 9, the collector current 49 is 0 when the switching command signal 42 is at the “L” level, and the switching command signal 42 is next at the “H” level. The collector current 49 has a relatively large current value and then a relatively small current value until the delay time TA elapses after the level is changed to the level, and the switching command signal 42
Becomes "L" level, the collector current 49 becomes zero.

The above is the current control means 127 and the current mirror means 98 in the case where the motor release signal 156 indicates the "H" level, that is, the state where the motor is not free running.
Finally, the operation of the current control means 127 and the current mirror means 98 when the electric motor release signal 156 is commanding the “L” level, that is, the free-run state is added. When the motor release signal 156 is'L 'level, that is, the free run state is instructed, the output signal of the logical product negation means 107 becomes'H' level regardless of the switching command signal 42, and therefore, the NPN type transistor. Two
The base signal 43 of 8 becomes the'L 'level. In this state, the collector current 47 is 0 and the collector current 49 of the transistor 9 is also 0. This is the so-called fifth state.

As described above, it is understood that the current mirror means 98 and the current control means 127 perform the same operations as the current control means 125.

Also in FIGS. 4, 6 and 7, the motor winding terminal voltage 51 is further increased by connecting a capacitor between the gate and source of the junction FETs 1 and 2.
It goes without saying that the rise time and fall time of can be significantly increased.

It goes without saying that the PNP type transistor 10 in FIG. 4 may be expressed as a diode.

(Embodiment 3) A third embodiment of the present invention will be described below with reference to the drawings.

In FIG. 6, 1 is an N-channel type junction FET and 2 is a P-channel type junction FE.
T, 3, 4, 5 and 6 are diodes, 126 and 1
27 is a current control means, 109 is a signal processing means, 14 is a DC main power supply, 15, 16, 17 and 18 are DC power supplies, 1
Reference numeral 05 denotes a resistor, which has the same structure as that shown in FIG.
4 is different from the configuration shown in FIG. 4 in that the current mirror means 98, which is composed of the PNP type transistors 9 and 10 and the resistors 11 and 12, is replaced with the PNP type transistor 9.
And the resistors 11 and 12 simply constitute the current mirror means.

Since the current mirror means in FIG. 6 is inferior in accuracy and temperature characteristics to the current mirror means in FIG. 4, it is necessary to raise the voltage of the DC power supply 15, but if it is allowed, there is no practical problem. Absent.

(Embodiment 4) A fourth embodiment of the present invention will be described below with reference to the drawings.

In FIG. 7, 1 is an N-channel type junction FET and 2 is a P-channel type junction FE.
T, 3, 4, 5 and 6 are diodes, 126 and 1
27 is a current control means, 109 is a signal processing means, 14 is a DC main power supply, 15, 16, 17 and 18 are DC power supplies, 1
Reference numeral 05 denotes a resistor, which has the same structure as that shown in FIG.

The difference from the configuration of FIG. 4 is that the current mirror means 98 composed of the PNP type transistors 9 and 10 and the resistors 11 and 12 is replaced by a PNP type transistor 9, an NPN type transistor 128 and a diode 129. This is that the resistors 11 and 130 constitute a current mirror means.

In the current mirror means shown in FIG. 4, P
When the collector voltage of the NP transistor 9 drops, PN
The base voltage of the P-transistor 9 is the collector output capacitance Co
It is lowered by the current flowing through b and turns on the PNP transistor 9. Therefore, a current leaks to the collector of the PNP transistor 9, and the gate signal voltage 5
The fall time of 0 becomes long and the switching loss of the junction FET increases. So to prevent this,
The PNP type transistor 9 has a collector output capacitance Co
It is necessary to select one in which b is very small.

On the other hand, in the current mirror means shown in FIG. 7, when the collector voltage of the PNP transistor 9 drops, the current flowing through the collector output capacitance Cob is NP.
Since it is compensated by the emitter current of the N-transistor 128, the base voltage of the PNP transistor 9 can be prevented from lowering, and the PNP-type transistor 9 is configured to have a small switching loss even if a collector output capacitance Cob having a relatively large value is selected. be able to.

(Fifth Embodiment) A fifth embodiment of the present invention will be described below with reference to the drawings.

In FIG. 8, reference numeral 1 is an N-channel type junction FET, and 2 is a P-channel type junction FE.
T, 3, 4, 5 and 6 are diodes, 109 is signal processing means, 14 is a DC main power supply, 15, 16, 17 and 1
Reference numeral 8 is a DC power source and 105 is a resistor. The above is the same as the configuration of FIG.

The difference from the configuration of FIG. 1 is that the current control means 1
26 is a current mirror means 132 and a current control means 131
And the current control means 125 are connected to the current control means 16
3 points.

The operations of the current mirror means 132 and the current control means 131 different from those of the configuration of FIG. 1 in the output circuit for the PWM inverter configured as above will be described.

In order to simplify the explanation, the case where the motor release signal 156 is instructing the "H" level, that is, the state where the motor is not free running, will be described.
Finally, a description will be added to the case where the motor release signal 156 commands the “L” level, that is, the free-run state.

First, the operation of the current control means 131 will be described in detail with reference to FIG. PNP type transistor 1
The base signal 148 of 37 causes the switching command signal 42 to be generated through the logical product negating means 106 and the logical inverting means 65, 161, and 139. The base signal 148 has the same potential as the plus terminal of the DC power supply 15 when the switching command signal 42 is at the “H” level, and has a potential 5 V lower than the plus terminal of the DC power supply 15 when at the “L” level.

Next, a P-channel type MOS-FE
The gate signal 149 of T138 is the switching command signal 4
2 is generated through the logical inversion means 65, 161, 140 and 141, the logical product negation means 106 and the signal delay means 142. The gate signal 149 is obtained by logically inverting the switching command signal 42 and delaying it by the delay time TB.
The "L" level is set to a voltage that can sufficiently turn on the MOS-FET 138, and the "H" level is set to the MOS-FE.
The voltage is set so that T138 can be sufficiently turned off.

The transistor 137 has an emitter follower type circuit configuration, and the potential of the base signal 148 is the DC power supply 1
When it becomes lower than the potential of the positive terminal of No. 5 by about 0.7 V or more, a current determined by the value of the resistor connected to the emitter and the voltage applied thereto flows as a collector current 150, and the potential of the base signal 148 and the DC power supply 15 If the difference from the positive terminal potential is about 0.7 V or less, collector current 15
0 becomes 0.

The MOS-FET 138 is the transistor 13
When the MOS-FET 138 is turned on in the state where the potential of the base signal of the transistor 137 is lower than the potential of the plus terminal of the DC power source 15 by about 0.7V or more, it functions to switch the value of the resistor connected to the emitter of the transistor 7. It has the effect of increasing the collector current 150 of the transistor 137.

Considering the relationship between the switching command signal 42 and the collector current 150, the collector current 150 is 0 when the switching command signal 42 is at the “H” level, and then the switching command signal 42 is at the “L” level. The collector current 150 has a relatively large current value and then has a relatively small current value until the delay time TB elapses after the change to, and the collector current 150 becomes 0 when the switching command signal 42 becomes the “H” level. .

The above is the description of the operation of the current control means 131. Next, the function of the current mirror means 132 will be described.

Resistors 135 and 136 and transistor 1
33 and 134 have a current mirror configuration with each other,
In the range where the transistor 133 is not saturated, the collector current 48 of the transistor 133 is set to the transistor 137.
Of the collector current 150.

The diode 4 limits the lower limit of the collector voltage of the transistor 133 so that the transistor 133 is not saturated at least when the fourth current value 167 is flowing.

Now, considering the relationship between the switching command signal 42 and the collector current 48 of the transistor 133, the collector current 48 is 0 when the switching command signal 42 is at the “H” level, and the switching command signal 4 is next.
The collector current 48 has a relatively large current value until the delay time TB elapses after 2 changes to the'L 'level.
Next, when the switching command signal 42 becomes relatively high and the switching command signal 42 becomes the “H” level, the collector current 48 becomes zero.

The above is the current control means 131 and the current mirror means 13 in the case where the electric motor release signal 156 commands the “H” level, that is, the state where the motor is not free running.
Regarding the operation of No. 2, the operation of the current control means 131 and the current mirror means 132 in the case where the electric motor release signal 156 is instructing the “L” level, that is, the free-run state is added at the end.

When the motor release signal 156 is at the'L 'level, that is, when the free run state is commanded, the output signal of the logical product negation means 106 becomes the'H' level regardless of the switching command signal 42, and thus the PNP. The base signal 148 of the type transistor 137 becomes the “H” level. In this state, the collector current 150 is 0 and the collector current 48 of the transistor 133 is also 0. This is the so-called fifth state.

As described above, the current mirror means 132
It can be seen that the current control means 131 and the current control means 131 operate in the same manner as the current control means 126.

Further, the current control means 1 different from the configuration of FIG.
63 is that the photocoupler 115 of the current control means 125 is the logic inverting means 162.

This is the current control means 163 and 131.
Since it is not necessary to consider insulation by operating the logic element of the signal processing means 109 with a common power supply, the same operation as the current control means 125 can be obtained by the configuration of the current control means 163.

Also in FIGS. 8, 10 and 11, by connecting a capacitor between the gate and the source of the junction type FETs 1 and 2, the rise time and fall time of the motor winding terminal voltage 51 can be made much longer. It goes without saying that you can do it.

It goes without saying that the NPN type transistor 134 in FIG. 8 may be expressed as a diode.

(Embodiment 6) A sixth embodiment of the present invention will be described below with reference to the drawings.

In FIG. 10, reference numeral 1 is an N-channel type junction FET, and 2 is a P-channel type junction FE.
T, 3, 4, 5 and 6 are diodes, 131 and 1
63 is a current control means, 109 is a signal processing means, 14 is a DC main power supply, 15, 16, 17 and 18 are DC power supplies, 1
Reference numeral 05 denotes a resistor, which has the same configuration as that shown in FIG.

The difference from the configuration of FIG. 8 is that NPN type transistors 133 and 134 and resistors 135 and 1 are used.
The current mirror means 132, which is composed of
N-type transistor 133 and resistors 135 and 13
6 is that the current mirror means is simply configured.
Since the current mirror means in FIG. 10 is inferior in accuracy and temperature characteristics to the current mirror means in FIG. 8, it is necessary to increase the voltage of the DC power supply 16, but if it is allowed, there is no practical problem.

(Embodiment 7) A seventh embodiment of the present invention will be described below with reference to the drawings.

In FIG. 11, reference numeral 1 is an N-channel type junction FET, and 2 is a P-channel type junction FE.
T, 3, 4, 5 and 6 are diodes, 131 and 1
63 is a current control means, 109 is a signal processing means, 14 is a DC main power supply, 15, 16, 17 and 18 are DC power supplies, 1
Reference numeral 05 denotes a resistor, which has the same configuration as that shown in FIG.

The difference from the configuration of FIG. 8 is that NPN type transistors 133 and 134 and resistors 135 and 1 are used.
The current mirror means 132, which is composed of
N-type transistor 133, PNP-type transistor 152, diode 153, resistors 135 and 1
This is the point that the current mirror means is constituted by 54.

In the current mirror means shown in FIG.
When the collector voltage of the PN transistor 133 rises,
The base voltage of the NPN transistor 133 rises due to the current flowing through the collector output capacitance Cob, turning on the NPN transistor 133. Therefore, the current leaks to the collector of the NPN transistor 133,
The rise time of the gate signal voltage 50 becomes long and the junction type FET
Will increase the switching loss.

Therefore, in order to prevent this, it is necessary to select the NPN type transistor 133 having a very small collector output capacitance Cob.

On the other hand, in the current mirror means in FIG. 11, when the collector voltage of the NPN transistor 133 rises, the current flowing through the collector output capacitance Cob can be removed by the emitter current of the PNP transistor 152, and the NPN transistor 133 can be removed. It is possible to prevent the rise of the base voltage of 133, and NPN type transistor 1
Even if 33 having a relatively large collector output capacitance Cob is selected, the switching loss can be reduced.

In the case of constructing a three-phase PWM inverter as shown in FIG. 12, generally, a DC main power supply is commonly connected and three PWM inverter output circuits are arranged. Needless to say, the DC power supplies 15, 16, 17, and 18 in the first, second, third, fourth, fifth, sixth, and seventh embodiments can also be commonly connected in the inverter output circuit.

[0123]

As described above, according to the present invention, by adopting the configuration of the first embodiment, there is essentially no floating state, and the switching command signal and the average voltage of the motor winding terminals are unique when the floating time is zero. Excellent PW with very small control error and low power consumption
The output circuit for the M inverter can be provided at low cost. Further, it is possible to provide an excellent output circuit for a PWM inverter, which generates very little electrical noise, at a low cost, if necessary.

Moreover, by adopting the configuration of the second embodiment,
The current control means and the signal processing means can be operated by a common power source, and the same effect as that of the first embodiment can be obtained while reducing the insulating means such as the photocoupler and the DC power source.

Further, with the configuration of the third embodiment,
The current mirror means can be configured simply and the accuracy and temperature characteristics are inferior to those of the second embodiment, but the same effect as that of the second embodiment can be obtained at low cost.

Moreover, by adopting the configuration of the fourth embodiment,
It is possible to prevent the base voltage of the PNP transistor 9 from decreasing when the collector voltage of the PNP transistor 9 decreases, and it is possible to obtain the same effect as that of the second embodiment while reducing the switching loss.

Further, by adopting the configuration of the fifth embodiment,
The same effect as that of the second embodiment can be obtained.

Further, by adopting the configuration of the sixth embodiment,
The current mirror means can be simply configured, and although the accuracy and temperature characteristics are inferior to those of the fifth embodiment, the same effect as that of the fifth embodiment can be obtained at low cost.

Further, by adopting the configuration of the seventh embodiment,
The base voltage of the NPN transistor 133 can be prevented from increasing when the collector voltage of the NPN transistor 133 increases, and the same effect as that of the fifth embodiment can be obtained while reducing the switching loss.

[Brief description of drawings]

FIG. 1 is an output circuit diagram for a PWM inverter according to a first embodiment of the present invention.

FIG. 2 (a) is a diagram showing the operation of the current control means of the PWM inverter output circuit in the first embodiment of the present invention. (B) Current control of the PWM inverter output circuit in the first embodiment of the present invention. The figure which shows the other operation of the means

FIG. 3 is a diagram showing the operation of the PWM inverter output circuit according to the first embodiment of the present invention.

FIG. 4 is an output circuit diagram for a PWM inverter according to a second embodiment of the present invention.

FIG. 5 is a diagram showing the operation of the current control means of the PWM inverter output circuit according to the second embodiment of the present invention.

FIG. 6 is an output circuit diagram for a PWM inverter according to a third embodiment of the present invention.

FIG. 7 is an output circuit diagram for a PWM inverter according to a fourth embodiment of the present invention.

FIG. 8 is an output circuit diagram for a PWM inverter according to a fifth embodiment of the present invention.

FIG. 9 is a diagram showing the operation of the current control means of the PWM inverter output circuit according to the fifth embodiment of the present invention.

FIG. 10 is an output circuit diagram for a PWM inverter according to a sixth embodiment of the present invention.

FIG. 11 is an output circuit diagram for a PWM inverter according to a seventh embodiment of the present invention.

FIG. 12 is a circuit diagram of a general PWM inverter.

FIG. 13 is a conventional output circuit diagram for a PWM inverter.

FIG. 14 is a diagram showing an operation of a conventional PWM inverter output circuit.

[Explanation of symbols]

1 N-channel type junction FET 2 P-channel type junction FET 3, 4, 5, 6, 78, 79, 129, 153 Diodes 9, 10, 119, 137, 152 PNP type transistor 11, 12, 32 , 33, 34, 35, 40, 41, 8
3,84,85,86,87,88,89,90,9
1, 92, 105, 116, 117, 121, 122,
130,135,136,146,147,154 Resistance 14 DC main power supply 15,16,17,18,93,94,118 DC power supply 20,21,22,23,24,25,65,111,
112, 113, 139, 140, 141, 161, 1
62 logic inversion means 26, 27, 114, 142 signal delay means 28, 29, 74, 75, 76, 77, 128, 13
3,134 NPN type transistor 30,31 N channel type MOS-FET 36,37,95,96 Zener diode 38,39 Capacitor 42,61,62 Switching command signal 52,63,64 Motor winding terminal 53 PWM inverter Output circuit 54 First state 55 Second state 56 Third state 57 Fourth state 58 Frequency voltage setting means 59 PWM control circuit 60 Electric motor 66,67 On-delay circuit 68,69 Base drive circuit 70,71 Power Transistors 72, 73, 115 Photocoupler 98, 132 Current mirror means 106, 107 Logical product negation means 109 Signal processing means 120, 138 P-channel type MOS-FET 125, 126, 127, 131, 163 Current control means 157, 1 58 AND means

Claims (11)

[Claims] 1. An N-channel type first junction type FET.
, A P-channel type second junction type FET, first, second, fifth and sixth diodes, and a current control means 1 for controlling a current flowing out from the current output terminal having a current output terminal A current control means 2 having a current input terminal for controlling a current flowing from the current input terminal; a DC main power source; and a third DC power source in which a minus terminal is connected to a plus terminal of the DC main power source, A fourth direct current power source in which a positive terminal is connected to a negative terminal of the direct current main power source, the drain of the first junction type FET, the cathode of the first diode, and the positive terminal of the direct current main power source are connected; Of the junction type FET, the anode of the second diode and the negative terminal of the DC main power source are connected, and the source of the first junction type FET, the anode of the first diode and the second junction type FE Is connected to the cathode of the second diode, the gate of the first junction type FET, the gate of the second junction type FET, the current output terminal of the current control means 1 and the current input terminal of the current control means 2. And, connecting the anode of the fifth diode and the cathode of the sixth diode, connecting the positive terminal of the third DC power supply and the cathode of the fifth diode, connecting the negative terminal of the fourth DC power supply and the sixth diode. Of the first or second junction type FET, and a resistor is connected between the gate and the source of the first or second junction type FET, wherein the current control means 1 and the current control means 2 are A first state in which a current flowing out from an output terminal is a first current value and a current flowing in from a current input terminal of the current control means 2 is a seventh current value; and a current output of the current control means 1 A second state in which the current flowing out from the child is the second current value and the current flowing in from the current input terminal of the current control means 2 is the eighth current value; and the current flowing out from the current output terminal of the current control means 1. The third state in which the current to be supplied is the fifth current value and the current flowing in from the current input terminal of the current control means 2 is the third current value, and the current flowing out from the current output terminal of the current control means 1 is A fourth state in which a current flowing in from a current input terminal of the current control means 2 is a fourth current value and a fourth current value is a sixth current value, and a current flowing out from a current output terminal of the current control means 1 is a ninth current value There is a fifth state in which the current value is a current value and the current flowing in from the current input terminal of the current control means 2 is also a ninth current value, and the first current value is a current value larger than the seventh current value. And the second current value is greater than the eighth current value. A larger current value, the third current value is a larger current value than the fifth current value, the fourth current value is a larger current value than the sixth current value, the first current value The difference between the value and the seventh current value is greater than the difference between the second current value and the eighth current value, and the difference between the third current value and the fifth current value is the fourth current value. It is set to be larger than the difference between the current value and the sixth current value, and only the second state and the fifth state can be shifted from the first state, and the third state and the fifth state can be changed from the second state. It is possible to shift only to the state, from the third state to only the fourth state and the fifth state, from the fourth state to only the first state and the fifth state, An output circuit for a PWM inverter configured to be able to shift from the state 5 to at least a first state and a third state. 2. An N-channel type first junction type FET.
A second junction FET of P-channel type, first, second, fifth and sixth diodes, a current inflow terminal and first and second current outflow terminals, and the second current outflow. A current mirror means 1 for causing a current corresponding to a current flowing out from a terminal to flow out from the first current outflow terminal, and a current control means 3 having a current input terminal for controlling a current flowing in from the current input terminal A current control means 2 having a current input terminal for controlling a current flowing from the current input terminal; a DC main power source; and a third DC power source in which a minus terminal is connected to a plus terminal of the DC main power source, A fourth direct current power source in which a positive terminal is connected to a negative terminal of the direct current main power source, and a first direct current source having a positive terminal connected to a positive terminal of the direct current main power source and having a higher voltage than the third direct current power source. And a drain of the first junction type FET, a cathode of the first diode and the positive terminal of the DC main power source are connected, and a drain of the second junction type FET, an anode of the second diode and the DC The negative terminal of the main power source is connected, the source of the first junction type FET, the anode of the first diode, the source of the second junction type FET and the cathode of the second diode are connected, and the first junction type FET is connected. , The gate of the second junction FET, the first current outflow terminal of the current mirror means 1, the current input terminal of the current control means 2, the anode of the fifth diode and the cathode of the sixth diode. The positive terminal of the third DC power supply is connected to the cathode of the fifth diode, and the negative terminal of the fourth DC power supply is connected to the anode of the sixth diode. The second current outflow terminal of the current mirror means 1 is connected to the current input terminal of the current control means 3; the positive terminal of the first DC power supply is connected to the current inflow terminal of the current mirror means 1; 2 has a configuration in which a resistor is connected between the gate and the source of the junction type FET, and the current mirror means 1 and the current control means 2
A first current value is a current flowing out from a first current outflow terminal of the current mirror means 1 and a seventh current value is a current flowing in from a current input terminal of the current control means 2.
And a current flowing out from the first current outflow terminal of the current mirror means 1 as a second current value and a current flowing in from the current input terminal of the current control means 2 as an eighth current value
And a current flowing out from the first current outflow terminal of the current mirror means 1 as a fifth current value and a current flowing in from the current input terminal of the current control means 2 as a third current value.
And a current flowing out from the first current outflow terminal of the current mirror means 1 as a sixth current value and a current flowing in from the current input terminal of the current control means 2 as a fourth current value
And a current flowing out from the first current outflow terminal of the current mirror means 1 as a ninth current value and a current flowing in from the current input terminal of the current control means 2 as a ninth current value.
And the first current value is a current value greater than the seventh current value, the second current value is a current value greater than the eighth current value, the third current value The current value is a current value greater than the fifth current value, the fourth current value is a current value greater than the sixth current value, the first current value and the seventh current value of The difference is made larger than the difference between the second current value and the eighth current value, and
The difference between the current value and the fifth current value is larger than the difference between the fourth current value and the sixth current value, and only the second state and the fifth state are changed from the first state. The second state can be changed to only the third state and the fifth state, and the third state can be changed to only the fourth state and the fifth state. The output circuit for the PWM inverter is configured so that it can be shifted only to the first state and the fifth state from, and can be shifted from the fifth state to at least the first state and the third state. 3. The current mirror means 1 comprises PNP type third and fourth transistors,
The collector of the third transistor serves as a first current outflow terminal, and the base and collector of the fourth transistor are connected to the base of the third transistor to form a second one.
3. The output circuit for the PWM inverter according to claim 2, wherein the current outflow terminal is a current outflow terminal, and the current inflow terminal is connected to the emitters of the third and fourth transistors via resistors. 4. The current mirror means 1 has a third transistor of PNP type, the collector of the third transistor serves as a first current outflow terminal, and the base of the third transistor serves as a second current output terminal. 3. The output circuit for a PWM inverter according to claim 2, wherein the current outflow terminal is used, and the current inflow terminal is connected to the base and emitter of the third transistor via a resistor. 5. The current mirror means 1 has a PNP type third transistor, an NPN type fifth transistor and a fifth diode, and a collector of the third transistor is a first current outflow terminal. The base of the fifth transistor and the cathode of the fifth diode are connected to form a second current outflow terminal, and the base of the third transistor, the emitter of the fifth transistor, and the fifth One in which the anode of the diode is connected, the base of the fifth transistor and the cathode of the fifth diode are connected, and one in which the emitter of the third transistor is connected via a resistor, respectively.
3. The PWM inverter output circuit according to claim 2, wherein a current inflow terminal is formed by connecting the collectors of the fifth transistors. 6. An N-channel type first junction type FET.
, A P-channel type second junction type FET, first, second, fifth and sixth diodes, and a current control means 1 for controlling a current flowing out from the current output terminal having a current output terminal And a current mirror means 2 which has a current outflow terminal and first and second current inflow terminals and serves to flow in a current corresponding to the current flowing in from the second current inflow terminal from the first current inflow terminal. A current control means 4 having a current output terminal for controlling a current flowing out from the current output terminal; a DC main power supply; and a third DC power supply in which a minus terminal is connected to a plus terminal of the DC main power supply, A fourth direct current power source in which a positive terminal is connected to the negative terminal of the direct current main power source; And a drain of the first junction type FET, a cathode of the first diode and the positive terminal of the DC main power source are connected, and a drain of the second junction type FET, an anode of the second diode and the DC The negative terminal of the main power source is connected, the source of the first junction type FET, the anode of the first diode, the source of the second junction type FET, and the cathode of the second diode are connected, and the first junction type FET is connected. , The gate of the second junction FET, the current output terminal of the current control means 1, the first current inflow terminal of the current mirror means 2, the anode of the fifth diode and the cathode of the sixth diode. The positive terminal of the third DC power supply and the cathode of the fifth diode are connected, and the negative terminal of the fourth DC power supply is connected to the anode of the sixth diode. The current output terminal of the control means 4 and the second current inflow terminal of the current mirror means 2 are connected, and the negative terminal of the second DC power supply and the current outflow terminal of the current mirror means 2 are connected. 2 has a structure in which a resistor is connected between the gate and the source of the junction FET, and the current control means 1 and the current mirror means 2
A first current value is a current flowing out from the current output terminal of the current control means 1 and a seventh current value is a current flowing in from the first current inflow terminal of the current mirror means 2.
And a current flowing out from the current output terminal of the current control means 1 as a second current value and a current flowing in from the first current inflow terminal of the current mirror means 2 as an eighth current value.
And a current flowing out from the current output terminal of the current control means 1 as a fifth current value and a current flowing in from the first current inflow terminal of the current mirror means 2 as a third current value.
And a current flowing out from the current output terminal of the current control means 1 as a sixth current value and a current flowing into the first current inflow terminal of the current mirror means 2 as a fourth current value. And the current flowing out from the current output terminal of the current control means 1 is the ninth current value, and the current flowing in from the first current inflow terminal of the current mirror means 2 is also the ninth current value.
And the first current value is a current value greater than the seventh current value, the second current value is a current value greater than the eighth current value, the third current value The current value is a current value greater than the fifth current value, the fourth current value is a current value greater than the sixth current value, the first current value and the seventh current value of The difference is greater than the difference between the second current value and the eighth current value, and the difference between the third current value and the fifth current value is the fourth current value and the sixth current value. The second state and the fifth state from the first state, and the third state and the fifth state from the second state. It is possible to move only from the 4th state to the 5th state, and from the 4th state to only the 1st state and the 5th state. An output circuit for a PWM inverter configured to be able to shift from the fifth state to at least the first state and the third state. 7. The current mirror means 2 has NPN type sixth and seventh transistors,
The collector of the sixth transistor serves as a first current inflow terminal, and the base and collector of the seventh transistor are connected to the base of the sixth transistor to form a second
7. The output circuit for the PWM inverter according to claim 6, wherein the current inflow terminal is the current outflow terminal, and the ones connected to the emitters of the sixth and seventh transistors through resistors are current outflow terminals. 8. The current mirror means 2 has a sixth transistor of NPN type, the collector of the sixth transistor serves as a first current inflow terminal, and the base of the sixth transistor serves as a second transistor. 7. The output circuit for a PWM inverter according to claim 6, wherein a current inflow terminal is used, and the base and the emitter of the sixth transistor are respectively connected via a resistor as a current outflow terminal. 9. The current mirror means 2 has an NPN type sixth transistor, a PNP type eighth transistor and a sixth diode, and the collector of the sixth transistor is a first current inflow terminal. The base of the eighth transistor and the anode of the sixth diode are connected to form a second current inflow terminal, and the base of the sixth transistor, the emitter of the eighth transistor, and the sixth transistor A diode connected to the cathode, a base connected to the eighth transistor and an anode to the sixth diode, and a diode connected to the emitter of the sixth transistor via a resistor, respectively.
7. The PWM inverter output circuit according to claim 6, wherein a current output terminal is formed by connecting the collector of the eighth transistor. 10. The method according to claim 1, wherein the fifth current value, the sixth current value, the seventh current value, the eighth current value or the ninth current value is 0.
An output circuit for a PWM inverter according to claim 3, claim 4, claim 5, claim 6, claim 7, claim 8, or claim 9. 11. A Zener diode having a common anode or cathode connected in series to each other is connected between the gate and the source of the first or second junction type FET. P of claim 3 or claim 4 or claim 5 or claim 6 or claim 7 or claim 8 or claim 9 or claim 10.
Output circuit for WM inverter.