JP3228059B2 - Output circuit for PWM inverter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention
The present invention relates to a power circuit of a PWM inverter that performs WM control. PWM stands for Pulse Width Mod
This is a technique that is widely used in the field of motor control.

[0002]

2. Description of the Related Art In recent years, PWM inverters have rapidly spread and are widely used for motor control.

FIG. 5 is a schematic diagram showing a configuration of a general PWM inverter, and shows a three-phase PWM inverter as an example. Generally, in a PWM inverter, the number of PWM inverter output circuits 53 is different depending on the number of phases of a motor used, but the basic operation is the same.

Referring to FIG. 5, the structure of a general three-phase PWM inverter will be described. First, the fundamental frequency and the effective voltage value of the three-phase AC voltage waveform supplied to the electric motor 60 are set in the frequency voltage setting means 58. Next, the PWM control circuit 59
Generates a three-phase PWM signal internally based on the information set in the frequency voltage setting means 58 and outputs it as switching command signals 42, 61 and 62. The switching command signals 42, 61 and 62 are supplied to the motor winding terminal 5
2, 63 and 64 are binary signals for instructing whether to connect to the plus terminal or the minus terminal of the DC main power supply 14, respectively. The frequency of the switching command signal 42 or 61 or 62 is called a PWM carrier frequency, and takes a value that is ten times or more the fundamental frequency of the three-phase AC voltage waveform supplied to the motor 60. Generally, the basic frequency of the three-phase AC voltage waveform supplied to the motor is about 0 Hz to 200 Hz, and the PWM carrier frequency is 2 kHz.
Many are about 20 kHz. Motor release signal 156
Commands whether the motor is to be in a free-run state 2
It is a value signal. The free run state is the motor winding terminal 5
It is common practice to protect the motor and the control device when all troubles 2, 63 and 64 are not connected to the positive terminal or the negative terminal of the DC main power supply 14 and some trouble occurs. is there. PW
The M inverter output circuit 53 is a semiconductor switch circuit that controls connection of the motor winding terminal 52 or 63 or 64 to the plus or minus terminal of the DC main power supply 14 in accordance with the switching command signal 42 or 61 or 62. When the motor release signal 156 indicates a free-run state, the switching command signal 42
Or motor winding terminal 52 irrespective of 61 or 62
Alternatively, the configuration is such that 63 or 64 is not connected to the plus terminal or the minus terminal of the DC main power supply 14.
Generally, DC main power supply is DC rectified and smoothed AC100V.
140V or a DC 200V rectified and smoothed
Many have C280V.

Hereinafter, a conventional output circuit for a PWM inverter will be described. FIG. 6 shows a configuration of a conventional PWM inverter output circuit.

In FIG. 6, reference numeral 65 denotes a logic inversion means for inverting the positive / negative logic of the switching command signal 42 and outputting an inverted switching signal 80. 157 and 158 are logical product means, and the motor release signal 156 and the switching command signal 42
The result of AND of the upper arm switching signal 15
9 and outputs the result of ANDing the motor release signal 156 and the inverted switching signal 80 as the lower arm switching signal 160. Reference numerals 66 and 67 denote on-delay circuits which output the upper-arm control signal 81 or the lower-arm control signal 82 by delaying the rising edges of the upper-arm switching signal 159 and the lower-arm switching signal 160 by the on-delay time TD, respectively. 68 and 6
9 is a base drive circuit, and 68 is an upper arm control signal 8
ON or OFF of the power transistor 70 corresponding to 1
F, 69 is configured to turn on or off the power transistor 71 in response to the lower arm control signal 82. That is, the upper arm control signal 81 becomes “H”.
Level, the output transistor of the photocoupler 72 becomes O
N, whereby the transistor 74 is turned on, whereby the transistor 76 is turned off, and the power transistor 70 is turned on. Conversely, when the upper arm control signal 81 becomes “L” level, the output transistor of the photocoupler 72 is turned off, and the transistor 74 is also turned off.
As a result, the transistor 76 is turned on and the power transistor 70 is turned off.

This base drive circuit is disclosed in
Although there are those described in JP-A-7-42589 and JP-A-59-178980, they can be replaced by performing basically the same operation as the base drive circuits 68 and 69 shown in FIG.

The operation of the output circuit for a PWM inverter configured as described above will be described below.
First, consider the case where the motor release signal 156 is at the "L" level, that is, when the motor is in the free-run state.
It can be seen that the power transistor 70 and the power transistor 71 are turned off regardless of whether the switching command signal 42 is at the “L” level or the “H” level.

A case where the motor release signal 156 is at the "H" level, that is, a command not in a free-run state will be described below.

FIG. 7 is a diagram showing signals inside the output circuit for the PWM inverter of FIG.
When 2 changes from the “L” level to the “H” level, the ON delay circuit 66 changes the upper arm control signal 81 from the “L” level to the “H” level with a delay of the ON delay time TD. When the upper arm control signal 81 is set to the “H” level, the power transistor 70 is turned on. In the meantime, the operation delay time TX1 of the base drive circuit 68 and the power transistor 70 exists. This operation delay time TX1
The power supply voltage fluctuates due to changes in the temperature of the power transistor 70 and the value of the current flowing through the collector, and also due to variations and aging of components constituting the base drive circuit and the power transistor.

When the switching command signal 42 is "L"
When the level changes from the “H” level to the “H” level, the inverted switching signal 80 changes from the “H” level to the “L” level,
The ON delay circuit 67 sets the lower arm control signal 82 to the “L” level with almost no time delay. When the lower arm control signal 82 is set to “L” level, the power transistor 71
Is turned off, and there is an operation delay time TY2 between the base drive circuit 69 and the power transistor 71 during that time. This operation delay time TY2 is equal to the power transistor 71.
Fluctuates due to changes in the temperature of the
It also changes due to variations in components and power transistors constituting the base drive circuit and aging.

Next, when the switching command signal 42 changes from the "H" level to the "L" level, the on-delay circuit 66 changes the upper arm control signal 81 to the "L" level with almost no time delay, and the power transistor 70 is turned off. However, there is an operation delay time TY1 between the base drive circuit 68 and the power transistor 70 in the meantime.

When the switching command signal 42 is "H"
When the level changes from the “L” level to the “L” level, the inverted switching signal 80 changes from the “L” level to the “H” level,
The on-delay circuit 67 changes the lower arm control signal 82 from 'L' level to 'H' level with a delay of the on-delay time TD. When the lower arm control signal 82 is set to the “H” level, the power transistor 71 is turned on. In the meantime, the operation delay time TX2 of the base drive circuit 69 and the power transistor 71 exists.

Here, comparing the operation delay time TX1 or the operation delay time TX2 with the operation delay time TY1 or the operation delay time TY2, the operation delay time TY1 or TY2 is generally longer than the operation delay time TX1 or TX2. Tend. The shortest value in consideration of the worst condition of the operation delay time TX1 and the operation delay time TX2 is defined as TXW, and the operation delay time TY1 and the operation delay time T
Assuming that the longest value in consideration of the worst condition of Y2 is TYW, the normal on-delay time TD is set to a value obtained by subtracting TXW from TYW and adding some margin.
Normally, the on-delay time TD is set to about 10 to 50 microseconds using a bipolar type power transistor, and is set to about 5 to 30 microseconds using an IGBT.
-Uses FET and is set to about 2 to 10 microseconds. Thereby, when the switching command signal 42 changes from the “H” level to the “L” level or from the “L” level to the “H” level, the power transistor 70 and the power transistor 71 are simultaneously turned on, and the DC A short circuit between the plus terminal and the minus terminal of the main power supply 14 is prevented.

From the above, considering the switching command signal 42 and the state of the motor winding terminal voltage 51,
First, when the switching command signal 42 is fixed at the "L" level, the power transistor 70 is OFF and the power transistor 71 is ON, so that the motor winding terminal 52 is connected to the minus terminal of the DC main power supply 14. When the switching command signal 42 is fixed at "H" level, the power transistor 7
Since 0 is ON and the power transistor 71 is OFF, the motor winding terminal 52 is connected to the plus terminal of the DC main power supply 14.

[0016]

However, in the above conventional configuration, when the motor release signal 156 is at the "H" level, that is, when the motor is in a non-free-run state, the switching command signal 42 is changed from the "L" level to the "L" level. When the voltage changes to the H level or the voltage changes from the H level to the L level, the power transistor 70 and the power transistor 71 are both turned off for a certain period of time. Control error. This control error has caused a problem that the generated torque and the rotation speed of the electric motor fluctuate, and the noise and vibration of the electric motor also increase.

This will be described in more detail. 6 and 7, when the switching command signal 42 changes from "L" level to "H" level or from "H" level to "L" level, the power transistor which has been ON is first turned OFF. After that, the power transistor that has been turned off is turned on. Therefore, for a certain time, both the power transistor 70 and the power transistor 71
FF is set. This state is called a floating state, and this time is called a floating time TZ. Generally, the floating time TZ is often about 1/2 to 2/3 of the ON delay time TD.

Generally, the PWM control of a motor is originally performed by alternately connecting a motor winding terminal to a plus terminal and a minus terminal of a DC main power supply, and setting a ratio of a time for connecting to the plus terminal to a time for connecting to the minus terminal. The average voltage of the motor winding terminal is controlled accordingly. Therefore,
When the voltage of the DC main power supply 14 is constant, it is ideal that the average voltage of the motor winding terminal 52 can be uniquely controlled according to the ratio of the time between the “H” level and the “L” level of the switching command signal 42. It is.

However, in the conventional output circuit for a PWM inverter, since the floating state exists, the average voltage of the motor winding terminal varies depending on the direction of the current flowing through the motor winding terminal. That is, the motor winding terminal 5
2, when the current flows in the direction in which the current flows into the PWM inverter output circuit 53, the diode 78 conducts when the floating state occurs, and the motor winding terminal 52 is connected to the plus terminal of the DC main power supply 14. Becomes
This state is shown by the motor winding terminal voltage 51A in FIG. Conversely, when a current flows from the PWM inverter output circuit 53 to the motor winding terminal 52 in a floating state in a floating state, the diode 79 conducts and the motor winding terminal 52 is connected to the minus terminal of the DC main power supply 14. It will be in the state that was done. This state is shown in FIG.
1B. In the floating state, when no current flows through the motor winding terminal 52, the voltage of the motor winding terminal 52 becomes a voltage determined by an induced voltage generated inside the motor 60.

As described above, since there is a floating state, the switching command signal 42 and the motor winding terminal 52
, The control voltage is not uniquely determined, causing a control error. Normally, since the direction of the current flowing through the motor winding terminal 52 is changed by alternating current, the control error also changes accordingly, and the generated torque and the rotation speed of the motor 60 fluctuate. This problem can be solved by eliminating the floating state and setting the floating time to 0. However, in the conventional PWM inverter output circuit, a short circuit occurs between the plus terminal and the minus terminal of the DC main power supply 14, and it is actually impossible. It is.

Further, electrical noise is generated when the power transistor is turned on or off. In particular, in applications where it is desired to reduce the noise, the switching speed is reduced by connecting a capacitor between the base and the emitter of the power transistor. There are cases. However, this causes the operation delay times TX1, TX2, TY1 and TY
2 becomes very large, and the floating time must be further increased. Therefore, the control error increases, and as a result, the switching speed cannot be reduced much.

The power transistor 70 and the power transistor 71 shown in FIG.
There is a conventional PWM inverter output circuit of the type in which the power transistor 70 and the power transistor 71 of FIG. 6 are replaced by IGBTs, respectively.
And has a floating state.

The present invention solves the above-mentioned conventional problems, in which the floating state is essentially eliminated, the floating time is zero, and the switching command signal and the average voltage of the motor winding terminal are uniquely determined. It is an object of the present invention to provide an inexpensive PWM inverter output circuit that does not cause power consumption and consumes less power.

[0024]

To achieve this object, an output circuit for a PWM inverter according to the present invention comprises a first power MOS-FET of a channel type, a second power MOS-FET of a P-channel type, and , 1st, 2nd
Third and fourth diodes, current control means 1 having a current output terminal and controlling a current flowing out of the current output terminal, and a current having a current input terminal and controlling a current flowing from the current input terminal A control means for connecting the drain of the first power MOS-FET to the cathode of the third diode, the anode of the third diode, the cathode of the first diode, and the DC main power supply; A positive terminal is connected, a drain of the second power MOS-FET is connected to an anode of the fourth diode, and a cathode of the fourth diode, an anode of the second diode and a negative terminal of the DC main power supply are connected. , The source of the first power MOS-FET, the anode of the first diode, the source of the second power MOS-FET, and the cathode of the second diode. Continue, and the first of the power MOS-FET
, The gate of the second power MOS-FET, the current output terminal of the current control means 1 and the current input terminal of the current control means 2 are connected, and the first or second power MOS-FET is connected.
-A resistor and a voltage limiting means having a Zener phenomenon for positive and negative bidirectional voltages and a current limiting means for limiting current for positive and negative bidirectional currents in parallel between a gate and a source of the FET; The current control means 1 and the current control means 2 have a current flowing out of a current output terminal of the current control means 1 as a first current value and have a current input terminal of the current control means 2 Inflow,
A current smaller than the first current is defined as a seventh current value.
The first power MOS is determined by the difference between the first current value and the seventh current value.
Switch the FET from a non-conducting state to a conducting state with a second power M
Move OS-FET from conductive state to non-conductive state
In the first state, the current flowing out of the current output terminal of the current control means 1 is set to a second current value, and the current flowing from the current input terminal of the current control means 2 is smaller than the second current.
Current as an eighth current value, a second current value and an eighth current value
The conduction state of the first power MOS-FET is maintained by the difference
The second state and the current flowing from the current output terminal of said current control means 1 and the fifth current value of the current control means for
2 and is smaller than the fifth current.
The third current value is defined as the fifth current value and the third current value as the third current value.
The first power MOS-FET is changed from the conductive state by the difference of the flow values.
Put the second power MOS-FET in a non-conductive state to a non-conductive state
A third state in which the state is changed from the state to the conducting state, and a current flowing out of the current output terminal of the current control means 1 is set as a sixth current value, flowing in from the current input terminal of the current control means 2, and the sixth state. A current smaller than the current of
The second power M is determined by the difference between the sixth current value and the fourth current value.
The fourth state in which the conduction state of the OS-FET is maintained, and the current flowing out of the current output terminal of the current control means 1 is set to a ninth current value, and the current flowing in from the current input terminal of the current control means 2 is also the fourth state. 9 as the first power MOS
-Both the FET and the second power MOS-FET are non-conductive
A fifth state, wherein a difference between the first current value and the seventh current value is larger than a difference between the second current value and the eighth current value, and The difference between the current value and the fifth current value is larger than the difference between the fourth current value and the sixth current value, and the transition from the first state to only the second state and the fifth state is possible. From the second state, it is possible to shift only to the third state and the fifth state, from the third state, only to the fourth state and the fifth state, and from the fourth state. Only the first state and the fifth state can be shifted, and at least the first state and the third state can be shifted from the fifth state.

Alternatively, a first power MOS-FET of an N-channel type, a second power MOS-FET of a P-channel type, and a current control having a current output terminal and controlling a current flowing out of the current output terminal Means 1, a current control means 2 having a current input terminal and controlling a current flowing from the current input terminal, and a DC main power supply; a drain of a first power MOS-FET and a positive terminal of the DC main power supply Are connected, the drain of the second power MOS-FET is connected to the negative terminal of the DC main power supply, and the source of the first power MOS-FET is connected to the second power MOS-FET.
The first power MOS-FET is connected to the source of the FET.
, The gate of the second power MOS-FET, the current output terminal of the current control means 1 and the current input terminal of the current control means 2 are connected, and the first or second power MOS-FET is connected.
-A resistor and a voltage limiting means having a Zener phenomenon for positive and negative bidirectional voltages and a current limiting means for limiting current for positive and negative bidirectional currents in parallel between a gate and a source of the FET; The current control means 1 and the current control means 2 have a current flowing out of a current output terminal of the current control means 1 as a first current value and have a current input terminal of the current control means 2 Inflow,
A current smaller than the first current is defined as a seventh current value.
The first power MOS is determined by the difference between the first current value and the seventh current value.
From the non-conductive state to the conductive state by the second power M
Move OS-FET from conductive state to non-conductive state
In the first state, the current flowing out of the current output terminal of the current control means 1 is set to a second current value, and the current flowing from the current input terminal of the current control means 2 is smaller than the second current.
Current as an eighth current value, a second current value and an eighth current value
The conduction state of the first power MOS-FET is maintained by the difference
The second state and the current flowing from the current output terminal of said current control means 1 and the fifth current value of the current control means for
2 and is smaller than the fifth current.
The third current value is defined as the fifth current value and the third current value as the third current value.
The first power MOS-FET is changed from the conductive state by the difference of the flow values.
Put the second power MOS-FET in a non-conductive state to a non-conductive state
A third state in which the state is changed from the state to the conducting state, and a current flowing out of the current output terminal of the current control means 1 is set as a sixth current value, flowing in from the current input terminal of the current control means 2, and the sixth state. A current smaller than the current of
The second power M is determined by the difference between the sixth current value and the fourth current value.
The fourth state in which the conduction state of the OS-FET is maintained, and the current flowing out of the current output terminal of the current control means 1 is set to a ninth current value, and the current flowing in from the current input terminal of the current control means 2 is also the fourth state. 9 as the first power MOS
-Both the FET and the second power MOS-FET are non-conductive
A fifth state, wherein a difference between the first current value and the seventh current value is larger than a difference between the second current value and the eighth current value, and The difference between the current value and the fifth current value is larger than the difference between the fourth current value and the sixth current value, and the transition from the first state to only the second state and the fifth state is possible. From the second state, it is possible to shift only to the third state and the fifth state, from the third state, only to the fourth state and the fifth state, and from the fourth state. Only the first state and the fifth state can be shifted, and at least the first state and the third state can be shifted from the fifth state.

Alternatively, the fifth current value or the sixth current value
, The seventh current value, the eighth current value, or the ninth current value is set to 0.

Alternatively, the voltage limiting means having a Zener phenomenon for positive and negative bidirectional voltages is constituted by two Zener diodes having their anodes or cathodes connected in common and in series.

Alternatively, the current limiting means for limiting the current in both the positive and negative directions is constituted by two constant current diodes having their anodes or cathodes connected in common and in series.

[0029]

According to this structure, the first and second power MOS-FETs are essentially not turned on at the same time and are safe, and the floating time is essentially zero. An output circuit for a PWM inverter with low power consumption and capable of turning off the power element at high speed at the time of a free-run command can be realized.

[0030]

(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, 1 is an N-channel type power MOS-FET, 2 is a P-channel type power MOS-FET, 5, 6, 7 and 8 are diodes,
125 and 126 are current control means, 109 is signal processing means, 14 is a DC main power supply, 15 and 16 are DC power supplies,
Reference numeral 99 denotes current limiting means constituted by constant current diodes 101 and 102, and 97 denotes voltage limiting means constituted by zener diodes 95 and 96.

The operation of the PWM inverter output circuit configured as described above will be described with reference to FIG. 65 is a logic inversion means, which is a switching command signal 42
Is output as an inverted switching signal 80. 106 and 107 are logical product negation means.
Outputs a result obtained by negating the logical product of the motor release signal 156 and the inverted switching signal 80, and outputs a result obtained by negating the logical product of the motor release signal 156 and the switching command signal 42.

For the sake of simplicity, a description will first be given of the case where the motor release signal 156 is at the "H" level, that is, a command not in a free-run state. Finally, the motor release signal 156 is at the "L" level. The level, that is, the case where the free-run state is commanded, will be added. First, the operations of the current control means 125 and the current control means 126 will be described in detail with reference to FIG. The base signal 123 of the transistor 119 of the PNP type converts the switching command signal 42 to the logical product negation means 1.
07, the photocoupler 115 and the logic inversion means 111. This base signal 123 is, for example, DC power supply 1 when switching command signal 42 is at “L” level.
In the case of the same potential as the plus terminal 5 and the “H” level, for example, the potential is set to 5 V lower than the plus terminal of the DC power supply 15.
Next, the gate signal 124 of the P-channel type MOS-FET 120 converts the switching command signal 42 into a logical product negation means 107, a photocoupler 115, and a logic inversion means 112.
And 113 and the signal delay means 114. The gate signal 124 is the switching command signal 4
2 is delayed by the delay time TA, the 'L' level is a voltage at which the MOS-FET 120 can be sufficiently turned on, and the 'H' level is a voltage at which the MOS-FET 120 can be sufficiently turned off. The transistor 119 has an emitter-follower circuit configuration. When the potential of the base signal 123 becomes lower than the potential of the plus terminal of the DC power supply 15 by about 0.7 V or more, it is determined by the value of the resistor connected to the emitter and the voltage applied thereto. The current substantially flows as the collector current 49, and the collector current 49 becomes 0 when the difference between the potential of the base signal 123 and the potential of the plus terminal of the DC power supply 15 is about 0.7 V or less. MOS-FET
A transistor 120 functions to switch the value of a resistor connected to the emitter of the transistor 119.
9 is lower than the potential of the plus terminal of the DC power supply 15 by about 0.7 V or more.
When 0 is ON, the collector current 49 of the transistor 119
Has the effect of increasing

Here, considering the relationship between the switching command signal 42 and the collector current 49, when the switching command signal 42 is at the "L" level, the collector current 49 becomes zero.
Then, after the switching command signal 42 changes to the “H” level, the collector current 4 is maintained until the delay time TA elapses.
Reference numeral 9 indicates a relatively large current value, and then a relatively small current value. When the switching command signal 42 becomes "L" level, the collector current 49 becomes zero. The base signal 45 of the NPN type transistor 29 generates the switching command signal 42 through the logic inversion means 65 and 23 and the logical product negation means 106. This base signal 45
Is almost the same as a signal obtained by logically inverting the switching command signal 42. It is assumed that the 'L' level has a value of, for example, 0V and the 'H' level has a value of, for example, 5V. Next, the gate signal 46 of the N-channel type MOS-FET 31 generates the switching command signal 42 through the logic inversion means 65, 24 and 25, the logical product negation means 106, and the signal delay means 27. The gate signal 46 is obtained by delaying the switching command signal 42 by the delay time TB, and is "L".
The level is set to a voltage at which the MOS-FET 31 can be sufficiently turned off, and the “H” level is set to the MOS-FET 31
Is a voltage that can be sufficiently turned on. The transistor 29 has an emitter-follower type circuit configuration. When the base signal 45 becomes about 0.7 V or more, a collector current 48 determined by the voltage of the base signal 45 and the value of a resistor connected to the emitter flows, and the base signal 45 becomes about 0 V. When the voltage is 0.7 V or less, the collector current 48 becomes zero. MOS-FET31
Functions to switch the value of the resistor connected to the emitter of the transistor 29. When the base signal of the transistor 29 is about 0.7 V or more and the MOS-FET 31 is turned on, the collector current 48 of the transistor 29 increases. .

Considering the relationship between the switching command signal 42 and the collector current 48, when the switching command signal 42 is at the "H" level, the collector current 48 becomes zero.
Then, after the switching command signal 42 changes to the “L” level, the collector current 4 is maintained until the delay time TB elapses.
8 becomes a relatively large current value, then becomes a relatively small current value, and when the switching command signal 42 becomes the "H" level, the collector current 48 becomes 0.

In summary, according to the switching command signal 42, the collector current 49 becomes the first current value 1
64, the collector current 48 has a seventh current value 170, and the collector current 49 has a second current value 165.
And the collector current 48 is set to the eighth current value 171.
And the third state in which the collector current 49 is the fifth current value 168 and the collector current 48 is the third current value 166, and the collector current 49 is the sixth current value 169 and the collector current 48 is the fourth current value. It can be seen that there is a fourth state with a current value of 167, and the fourth state is repeatedly realized in order from the first state. However, in the present embodiment, the fifth
Current value 168, sixth current value 169, seventh current value 1
70, and the eighth current value 171 is 0. The above is the description of the operation of the current control means 125 and 126.

Next, the operation of the voltage limiting means 97 will be described. The voltage limiting means 97 constituted by the Zener diodes 95 and 96 is connected to the transistor 11 so that the transistor 119 of the current control means 125 is not saturated.
9 functions to limit the upper limit of the collector voltage and also functions to limit the upper limit of the gate voltage of the power MOS-FETs 1 and 2. The voltage limiter 97 functions to limit the lower limit of the collector voltage of the transistor 29 so that the transistor 29 of the current controller 126 is not saturated.
It functions to limit the lower limit of the gate voltages of 1 and 2. Here, the upper limit of the gate voltage of the power MOS-FETs 1 and 2 is a voltage at which the power MOS-FET 1 can be sufficiently turned on, and the power MOS-FET 2 has a sufficient O
It is necessary that the voltage be a voltage that can be FF and that does not exceed the withstand voltage between the gate and the source of the power MOS-FETs 1 and 2. The lower limit of the gate voltage of the power MOS-FETs 1 and 2 is such that the power MOS-FET 2 is sufficiently ON.
The voltage must be a voltage that can be achieved, a voltage that can sufficiently turn off the power MOS-FET 1, and a value that does not exceed the withstand voltage between the gate and the source of the power MOS-FETs 1 and 2.

Generally, an N-channel type power MO
The breakdown voltage between the gate and the source of the S-FET is ± 20 V to ± 3
In many cases, the gate voltage threshold at which conduction between the drain and source starts is +0 V with respect to the source voltage.
Many are about 1V to + 5V. On the other hand, the breakdown voltage between the gate and the source of a P-channel type power MOS-FET is often about ± 20 V to ± 30 V, and the gate voltage threshold value at which conduction between the drain and the source starts is based on the source voltage. Many are about 1V to -5V.

FIG. 3 shows the relationship between the switching command signal 42 and the gate signal voltage 50 based on the minus terminal of the DC main power supply 14. First, when the switching command signal 42 changes from “L” level to “H” level, the collector current 49 of the transistor 119 flows, the gate signal voltage 50 sharply rises, and the voltage is fixed when the Zener diodes 95 and 96 are turned on. Is done. The rise time TR required for the gate signal voltage 50 to rise is determined by the relationship between the capacitance included in the power MOS-FETs 1 and 2 and the Zener diodes 95 and 96 and the collector current 49. When the Zener diodes 95 and 96 are conducting, the gate signal voltage 5
Since 0 does not change significantly, the voltage can be maintained even if the collector current 49 is a very small current. In practice, it is sufficient to set the current to a value equal to or more than the current flowing through the current limiting means 99. Therefore, the delay time T of the signal delay means 114
If A is set to be slightly longer than the rising time TR, the rising time TR can be reduced and the transistor 11
9 and the resistance of the resistor 122 can be minimized.

Next, the switching command signal 42 becomes "H".
When the level changes from the “L” level to the “L” level, the transistor 2
The collector current 48 of 9 flows and the gate signal voltage 50 drops sharply, and the voltage is fixed when the Zener diodes 95 and 96 become conductive. The time TF required for the gate signal voltage 50 to fall is determined by the relationship between the capacitance included in the power MOS-FETs 1 and 2 and the Zener diodes 95 and 96 and the collector current 48.
In addition, when the Zener diodes 95 and 96 are conducting, the gate signal voltage 50 does not greatly change. Therefore, even if the collector current 48 is a very small current, the voltage can be maintained, and the current flows to the current limiting means 99 in practice. It is enough to set the current value or more. Therefore, if the delay time TB of the signal delay means 27 is set to be slightly longer than the fall time TF, the fall time TF can be reduced, and the power loss of the transistor 29 and the resistor 35 can be minimized.

Next, the operation of the power MOS-FETs 1 and 2 will be described. Since the gates and the sources of the power MOS-FETs 1 and 2 are commonly connected, the gate signal voltage 50 is higher than the motor winding terminal voltage 51 by the power M
When the voltage becomes higher than the gate voltage threshold value of the OS-FET1, the power MOS-FET1 starts flowing current from the drain to the source, and conversely, the gate signal voltage 50 becomes higher than the motor winding terminal voltage 51. When the voltage becomes lower than the threshold, the power MOS-FET 2 starts flowing current from the source to the drain. Therefore, the potential difference between the gate signal voltage 50 and the motor winding terminal voltage 51 always falls within a certain range, and the power MOS-
The FETs 1 and 2 supply current at the same time to
It is essentially impossible that the plus terminal and the minus terminal are short-circuited.

Next, the operation of the diodes 5, 6, 7 and 8 will be described. Generally, a simple equivalent circuit of a motor winding is represented as a series connection of a resistance, an inductance, and a voltage source corresponding to an induced voltage. Therefore, unlike the pure resistance load, the direction of the current flowing through the motor winding terminal 52 is not uniquely determined by the voltage applied to the motor winding terminal 52, and the power MOS-FET1 is ON and the power MOS-FET2 is OFF. And the state of A in which a current flows out of the motor winding terminal 52 to the motor and the power MO
S-FET1 is ON and power MOS-FET2 is O
The state of B in which the current is flowing from the motor to the motor winding terminal 52 at the FF and the power MOS-FET 1 is OFF
And the state of C where the power MOS-FET 2 is ON and current flows from the motor to the motor winding terminal 52;
Power MOS-FET1 is OFF and power MOS-
There are four states, D, in which FET2 is ON and current flows from the motor winding terminal 52 to the motor. First, in the state A, it can be seen that the current flowing through the motor winding terminal 52 flows through the diode 7 and the power MOS-FET 1. Further, in the state C, the current flowing through the motor winding terminal 52 is the diode 8 and the power MO
It turns out that it flows through S-FET2. The state of B and D
It can be seen that the current flowing through the motor winding terminal 52 flows through the diode 5 and the diode 6, respectively. Here, it can be seen that the motor winding terminal voltage 51 in the state B rises due to the current flowing through the motor winding terminal 52 and is fixed when the diode 5 becomes conductive. Generally, an N-channel type power MOS-
An FET has a parasitic diode that functions to flow a current from a source to a drain, but has a disadvantage that the reverse recovery time trr of the parasitic diode is very long. Therefore, a diode 5 having a short reverse recovery time trr is separately provided, and the diode 7 is attached so that no current flows through the parasitic diode of the power MOS-FET 1. If the reverse recovery time trr of the diode 5 is long, switching loss increases. Therefore, it is preferable to select a diode 5 having a short reverse recovery time as much as possible. Similarly, the motor winding terminal voltage 51 in the state D falls due to the current flowing through the motor winding terminal 52 and is fixed when the diode 6 becomes conductive. Generally, a P-channel type power MOS-FET has a parasitic diode that functions to flow a current from a drain to a source, but has a disadvantage that the reverse recovery time trr of the parasitic diode is very long. Therefore, a diode 6 with a short reverse recovery time trr is separately provided, and the diode 8 is attached so that no current flows through the parasitic diode of the power MOS-FET 2. If the reverse recovery time trr of the diode 6 is long, switching loss increases. Therefore, it is preferable to select a diode 6 having a short reverse recovery time as much as possible.

As described above, the switching command signal 4
When 2 is set to the “H” level, it is understood that the motor winding terminal 52 is connected to the plus terminal of the DC main power supply 14. Further, when the switching command signal 42 is set to the “L” level, the motor winding terminal 52 is connected to the minus terminal of the DC main power supply 14, and when the switching command signal 42 is changed from the “H” level to the “L” level, It can be seen that the floating time is essentially zero even when the level is changed from the “L” level to the “H” level.

Further, by changing the current values of the collector current 49 of the transistor 119 and the collector current 48 of the transistor 29, the rise time T of the gate signal voltage 50 is increased.
R and the fall time TF can be freely set within a certain range, and accordingly, the rise time and the fall time of the motor winding terminal voltage 51 can be freely set within a certain range. Normally, motor winding terminal voltage 5
As the rise time and fall time of 1 are smaller, the power M
This is preferable because the power loss of the OS-FET1 and the power MOS-FET2 can be reduced, but has a disadvantage that electric noise increases. Therefore, it is necessary to increase the rise time and the fall time of the motor winding terminal voltage 51 in an application in which electric noise is particularly desired to be reduced, and this configuration can easily cope with this.

The power MO shown in FIGS.
By connecting a capacitor between the gate and the source of the S-FETs 1 and 2, the motor winding terminal voltage 51
It is needless to say that the rise time and the fall time can be greatly increased.

The above is the description of the operation of the current control means 125 and 126 when the motor release signal 156 is at the "H" level, that is, when the motor is not in the free-run state. An explanation of the operation of the current control means 125 and 126 in the case of commanding the "L" level, that is, the free-run state, will be added.

When the motor release signal 156 is at the "L" level, that is, when the free-run state is commanded, the output signals of the logical product negation means 106 and 107 are both at the "H" level regardless of the switching command signal 42. Therefore, the base signal 123 of the transistor 119 of the PNP type becomes "H" level, and the base signal 45 of the transistor 29 becomes "L" level.

This state is a so-called fifth state, in which the ninth current values of the collector current 49 and the collector current 48
Are both 0.

In the fifth state, the current limiting means 9
9, the power MOS-FETs 1 and 2 are turned off, and a free-run state can be realized.

The current limiting means 99 is composed of constant current diodes 101 and 102, and becomes a constant current source when a voltage is applied. The current limit means 99 allows the power MOS-FET
The electric charges charged in the input capacitors 1 and 2 are discharged at high speed, and the power MOS-FETs 1 and 2 are turned off in a short time.
can do. Further, it is needless to say that by connecting a resistor in parallel to the current limiting means 99, the potential of the gate and the potential of the source can be made substantially the same. The fifth state is mainly used for stopping the operation of the motor and protecting the motor and the control device when some trouble occurs.

The transition to the fifth state is based on the first state,
The state can be changed from any of the second state, the third state, and the fourth state, and the operation is shifted to the moment when the motor release signal 156 changes to the “L” level. Conversely, the fifth state is configured to shift to the first state or the third state at the moment when the motor release signal 156 changes to the “H” level. This is because when the state shifts from the fifth state to the second state or the fourth state, the time required for the rise or fall of the gate signal voltage 50 becomes extremely long, and the power MOS-FET 1
This is a measure to prevent excessive heat generation in (2) and (2). However, the transition from the fifth state to another state is mainly for the purpose of resuming the operation of the interrupted electric motor, and in this case, about once every few seconds at most. Power MOS-FET1
If the withstand capability of (2) and (3) is sufficient, it is also possible to adopt a configuration in which the state can be shifted from the fifth state to all other states. Note that the current control means 125 and 126 of this embodiment set the fifth current value 168, the sixth current value 169, the seventh current value 170, and the eighth current value 171 to 0, but the first current value The current value 164 is a current value larger than the seventh current value 170, the second current value 165 is a current value larger than the eighth current value 171, and the third current value 166 is a fifth current value 168 And the fourth current value 16
7 is a current value larger than the sixth current value 169,
The difference between the current value 164 and the seventh current value 170 is larger than the difference between the second current value 165 and the eighth current value 171.
If the difference between the current value 166 and the fifth current value 168 is larger than the difference between the fourth current value 167 and the sixth current value 169,
It goes without saying that the fifth current value 168, the sixth current value 169, the seventh current value 170, and the eighth current value 171 can be set to values other than 0. FIG. 2B shows an example. Further, the current control means 125 and 126 of this embodiment
Although the ninth current value in the fifth state is also 0, it goes without saying that the ninth current value can also be a value other than 0. That is, the collector current 4 of the transistor 119
If the collector current 9 of the transistor 9 and the collector current 48 of the transistor 29 have the same current value, they can be set to values other than 0.

(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

In FIG. 4, reference numerals 125 and 126 denote current control means, 109 denotes signal processing means, 14 denotes a DC main power supply,
15 and 16 are DC power supplies, 99 is a constant current diode 1
Current limiting means comprising 97, 97
Is a voltage limiting means composed of Zener diodes 95 and 96, and the above is the same as the configuration of FIG. The difference from the configuration of FIG.
And 2, and the diodes 5, 6, 7 and 8 are an N-channel type power MOS-FET 1a and a P-channel type power MOS-FET 2a having a parasitic diode with a short reverse recovery time trr.

In recent years, the technology of power MOS-FETs has been advanced, and only a part of the parasitic diode whose reverse recovery time trr is very short is manufactured. This reverse recovery time trr
When a power MOS-FET having a short parasitic diode can be obtained, the configuration shown in FIG. 4 can be employed, and the number of components can be reduced.

[0055]

As described above, according to the first embodiment of the present invention, the switching command signal and the average voltage of the motor winding terminal are uniquely determined by essentially eliminating the floating state and having no floating time. Thus, it is possible to provide an excellent PWM inverter output circuit which has a very small control error, consumes little power, and can quickly turn off the power element at the time of a free-run command. Furthermore, if necessary, an excellent PWM inverter output circuit that generates very little electrical noise can be provided at low cost.

Further, by adopting the configuration of the second embodiment, the same effect as that of the first embodiment can be obtained. Recently, the technology of the power MOS-FET has been developed, and only a part of the diode has a very short reverse recovery time trr. When a power MOS-FET having a parasitic diode with a short reverse recovery time trr is available, this configuration can be adopted, and the number of components can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an output circuit for a PWM inverter according to a first embodiment of the present invention.

FIG. 2A shows the operation of the current control means of the output circuit for a PWM inverter according to the first embodiment of the present invention. FIG. 2B shows the current control of the output circuit for a PWM inverter according to the first embodiment of the present invention. Diagram showing another operation of the means

FIG. 3 is a diagram showing an operation of the output circuit for the PWM inverter according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram of an output circuit for a PWM inverter according to a second embodiment of the present invention.

FIG. 5 is a schematic diagram showing a configuration of a general PWM inverter;

FIG. 6 is a configuration diagram of a conventional output circuit for a PWM inverter.

FIG. 7 is a diagram showing the operation of a conventional PWM inverter output circuit.

[Explanation of symbols]

1, 1a N-channel type power MOS-FET 2, 2a P-channel type power MOS-FET 5, 6, 7, 8, 78, 79 Diode 14 DC main power supply 15, 16, 93, 94 DC power supply 23, 24 , 25, 65, 111, 112, 113 Logical inversion means 27, 114 Signal delay means 29, 74, 75, 76, 77 NPN type transistor 31 N-channel type MOS-FET 34, 35, 83, 84, 85, 86,87,88,8
9,90,91,92,116,117,121,12
2 Resistance 42, 61, 62 Switching command signal 45, 123 Base signal 48, 49 Collector current 50 Gate signal voltage 51, 51A, 51B Motor winding terminal voltage 52, 63, 64 Motor winding terminal 53 PWM inverter output circuit 54 1st state 55 2nd state 56 3rd state 57 4th state 58 Frequency voltage setting means 59 PWM control circuit 60 Electric motor 66, 67 On delay circuit 68, 69 Base drive circuit 70, 71 Power transistor 72, 73 , 115 Photocoupler 80 Inverting switching signal 81 Upper arm control signal 82 Lower arm control signal 95, 96 Zener diode 97 Voltage limiter 99 Current limiter 101, 102 Constant current diode 106, 107 Logical product negation unit 109 Signal processing unit 1 9 PNP type transistor 120 P-channel type MOS-FET 124 gate signals 125 and 126 current control unit 156 motor release signal 157, 158 logical product means 159 upper-arm switching signal 160 lower-arm switching signal

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-233548 (JP, A) JP-A-6-315270 (JP, A) JP-A-6-121540 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H02M 7/48 H02M 7/537 H02M 7/5387

Claims (5)

(57) [Claims] 1. An N-channel type first power MOS
-FET and P-channel type second power MOS
An FET, first, second, third and fourth diodes, current control means 1 having a current output terminal and controlling a current flowing out of the current output terminal, and a current control means having a current input terminal. A current control means for controlling a current flowing from an input terminal; a DC main power supply; a drain of the first power MOS-FET and a cathode of a third diode connected to each other; Connecting the cathode of the diode to the plus terminal of the DC main power supply, connecting the drain of the second power MOS-FET to the anode of the fourth diode, and connecting the cathode of the fourth diode and the anode of the second diode. The negative terminal of the DC main power supply is connected, and the source of the first power MOS-FET, the anode of the first diode, and the source of the second power MOS-FET Connect the cathode of the second diode, a gate and a second power of the first power MOS-FET M
A gate of the OS-FET, a current output terminal of the current control means 1 and a current input terminal of the current control means 2 are connected, and a resistance and a positive and negative resistance are provided between the gate and the source of the first or second power MOS-FET. A voltage limiting means having a Zener phenomenon for a bidirectional voltage and a current limiting means for limiting a current for a positive and a negative bidirectional current are connected in parallel; The current control means 2 sets a current flowing from a current output terminal of the current control means 1 as a first current value, flows in from a current input terminal of the current control means 2, and sets a current smaller than the first current to a Current of 7
The value of the first parameter is the difference between the first current value and the seventh current value.
The power MOS-FET from the non-conductive state to the conductive state,
Power MOS-FET from conductive state to non-conductive state
The first state to be shifted and the current flowing out of the current output terminal of the current control means 1 as a second current value, flowing in from the current input terminal of the current control means 2, and the current smaller than the second current Eighth current
The value of the first parameter is the difference between the second current value and the eighth current value.
Second state for maintaining conduction state of power MOS-FET
When the current control means 2 of the current input terminal and the current flowing from the current the current output terminal of the control unit 1 and the fifth current value of
And a current smaller than the fifth current is supplied to the third current.
As the value, the first parameter is determined by the difference between the fifth current value and the third current value.
The power MOS-FET from the conductive state to the non-conductive state,
Power MOS-FET from non-conductive state to conductive state
The third state to be shifted and the current flowing out of the current output terminal of the current control means 1 as a sixth current value, flowing in from the current input terminal of the current control means 2, and the current smaller than the sixth current Fourth current
The value of the second parameter is the difference between the sixth current value and the fourth current value.
Fourth state for maintaining conduction state of power MOS-FET
When the first power MO a current flowing from the current output terminal of said current control means 1 a ninth current is also a current value of the ninth and the current value flowing from the current input terminal of the current control means 2
Disconnect both S-FET and second power MOS-FET
A fifth state in which the first current value and the seventh current value are larger than a difference between the second current value and the eighth current value; And the fifth current value is larger than the difference between the fourth current value and the sixth current value, and the first state is shifted only to the second state and the fifth state. It is possible to make it possible to make the transition from the second state only to the third state and the fifth state, and to make it possible to make the transition from the third state only to the fourth state and the fifth state. From the fourth state Is an output circuit for a PWM inverter configured to be able to shift only to the first state and the fifth state, and to be able to shift from the fifth state to at least the first state and the third state. 2. An N-channel type first power MOS
-FET and P-channel type second power MOS
A current control means 1 having a current output terminal and controlling a current flowing out of the current output terminal; a current control means 2 having a current input terminal and controlling a current flowing from the current input terminal; A DC main power supply, wherein a drain of the first power MOS-FET is connected to a plus terminal of the DC main power supply, a drain of a second power MOS-FET is connected to a minus terminal of the DC main power supply, Of the power MOS-FET and the second power M
The source of the OS-FET is connected, and the first power MOS-
A gate of the FET, a gate of the second power MOS-FET, a current output terminal of the current control means 1 and a current input terminal of the current control means 2 are connected, and a gate of the first or second power MOS-FET is connected. It has a configuration in which a resistor and a voltage limiter having a Zener phenomenon for positive and negative bidirectional voltages and a current limiter for limiting current for positive and negative bidirectional currents are connected in parallel between the sources. and, the current control unit 1 and the current control means 2, a current flowing from the current output terminal of said current control means 1 and the first current value flows from the current input terminal of the current control means 2, the second The current smaller than the current of the first is the seventh current
The value of the first parameter is the difference between the first current value and the seventh current value.
The power MOS-FET from the non-conductive state to the conductive state,
Power MOS-FET from conductive state to non-conductive state
The first state to be shifted and the current flowing out of the current output terminal of the current control means 1 as a second current value, flowing in from the current input terminal of the current control means 2, and the current smaller than the second current Eighth current
The value of the first parameter is the difference between the second current value and the eighth current value.
Second state for maintaining conduction state of power MOS-FET
When the current control means 2 of the current input terminal and the current flowing from the current the current output terminal of the control unit 1 and the fifth current value of
And a current smaller than the fifth current is supplied to the third current.
As the value, the first parameter is determined by the difference between the fifth current value and the third current value.
The power MOS-FET from the conductive state to the non-conductive state,
Power MOS-FET from non-conductive state to conductive state
The third state to be shifted and the current flowing out of the current output terminal of the current control means 1 as a sixth current value, flowing in from the current input terminal of the current control means 2, and the current smaller than the sixth current Fourth current
The value of the second parameter is the difference between the sixth current value and the fourth current value.
Fourth state for maintaining conduction state of power MOS-FET
When the first power MO a current flowing from the current output terminal of said current control means 1 a ninth current is also a current value of the ninth and the current value flowing from the current input terminal of the current control means 2
Disconnect both S-FET and second power MOS-FET
A fifth state in which the first current value and the seventh current value are larger than a difference between the second current value and the eighth current value; And the fifth current value is larger than the difference between the fourth current value and the sixth current value, and the first state is shifted only to the second state and the fifth state. It is possible to make it possible to make the transition from the second state only to the third state and the fifth state, and to make it possible to make the transition from the third state only to the fourth state and the fifth state. From the fourth state Is an output circuit for a PWM inverter configured to be able to shift only to the first state and the fifth state, and to be able to shift from the fifth state to at least the first state and the third state. 3. The method according to claim 1, wherein the fifth current value, the sixth current value, the seventh current value, the eighth current value, or the ninth current value is zero. An output circuit for a PWM inverter as described in the above. 4. The voltage limiting means having a Zener phenomenon with respect to positive and negative bidirectional voltages is two Zener diodes having their anodes or cathodes connected in common and in series. The output circuit for a PWM inverter according to claim 2 or 3. 5. A current limiting means having a current limit for positive and negative bidirectional currents is two constant current diodes having their anodes or cathodes connected in common and in series. 5. The output circuit for a PWM inverter according to claim 2, 3 or 4.