JP3235336B2 - Output circuit for PWM inverter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention
The present invention relates to a power circuit of a PWM inverter that performs WM control.

[0002] PWM stands for Pulse Width Mo.
Abbreviation of duration, a technique widely used in the field of motor control.

[0003]

2. Description of the Related Art In recent years, PWM inverters have rapidly spread and are widely used for motor control.

FIG. 12 is a schematic diagram showing a configuration of a general PWM inverter, and shows a three-phase PWM inverter as an example. Generally, in a PWM inverter, the number of PWM inverter output circuits 53 is different depending on the number of phases of a motor used, but the basic operation is the same.

Referring to FIG. 12, the configuration of a general three-phase PWM inverter will be described. First, the frequency voltage setting means 58
, The fundamental frequency and the effective voltage value of the three-phase AC voltage waveform supplied to the electric motor 60 are set. Next, the PWM control circuit 59
Generates a three-phase PWM signal internally based on the information set in the frequency voltage setting means 58 and outputs it as switching command signals 42, 61 and 62. The switching command signals 42, 61 and 62 are supplied to the motor winding terminal 5
2, 63 and 64 are binary signals for instructing whether to connect to the plus terminal or the minus terminal of the DC main power supply 14, respectively. The frequency of the switching command signal 42 or 61 or 62 is called a PWM carrier frequency, and takes a value that is ten times or more the fundamental frequency of the three-phase AC voltage waveform supplied to the motor 60. Generally, the basic frequency of the three-phase AC voltage waveform supplied to the motor is about 0 Hz to 200 Hz, and the PWM carrier frequency is 2 kHz.
Many are about 20 kHz. Motor release signal 156
Commands whether the motor is to be in a free-run state 2
It is a value signal. The free run state is the motor winding terminal 5
In a state where some trouble occurs when all of 2, 63 and 64 are not connected to the plus terminal or the minus terminal of the DC main power supply 14, this state is generally adopted to protect the motor and the control device. is there. PWM
The inverter output circuit 53 outputs the switching command signal 4
Motor winding terminal 5 according to 2 or 61 or 62
2 or 63 or 64 is a semiconductor switch circuit that controls connection of the DC main power supply 14 to the plus terminal or the minus terminal. When the motor release signal 156 indicates a free-run state, the motor winding terminal 52 or 63 or 64 is also connected to the plus terminal of the DC main power supply 14 regardless of the switching command signal 42 or 61 or 62. It is configured not to be connected to the terminal. Generally, DC main power supply is DC1 which rectifies and smoothes AC100V.
DC of about 40V or rectified and smoothed AC200V
Many are about 280V.

Hereinafter, a conventional output circuit for a PWM inverter will be described. FIG. 13 shows a configuration of a conventional PWM inverter output circuit.

In FIG. 13, reference numeral 65 denotes a logic inversion means for inverting the positive / negative logic of the switching command signal 42 and outputting an inverted switching signal 80. 157 and 158 are logical product means, and the motor release signal 156 and the switching command signal 4
The result of the logical product of 2 is used as the upper arm switching signal 1
59, and outputs the result of ANDing the motor release signal 156 and the inverted switching signal 80 as the lower arm switching signal 160. Reference numerals 66 and 67 denote on-delay circuits which output the upper-arm control signal 81 or the lower-arm control signal 82 by delaying the rising edges of the upper-arm switching signal 159 and the lower-arm switching signal 160 by the on-delay time TD, respectively. Reference numerals 68 and 69 denote base drive circuits. Reference numeral 68 denotes a power transistor 70 which is turned on or off in response to the upper arm control signal 81.
The FF 69 is configured to turn on or off the power transistor 71 in response to the lower arm control signal 82. That is, when the upper arm control signal 81 becomes “H” level, the output transistor of the photocoupler 72 is turned on, whereby the transistor 74 is turned on, whereby the transistor 76 is turned off, and the power transistor 70 is turned on. Conversely, when the upper arm control signal 81 goes low, the output transistor of the photocoupler 72 is turned off.
FF is performed, whereby the transistor 76 is turned on, and the power transistor 70 is turned off.

This base drive circuit is disclosed in
Although there are those described in JP-A-7-42589 and JP-A-59-178980, they can be replaced by performing basically the same operation as the base drive circuits 68 and 69 shown in FIG.

The operation of the PWM inverter output circuit configured as described above will be described below.

First, consider the case where the motor release signal 156 is at the "L" level, that is, when the switching command signal 42 is at the "L" level or the "H" level. It turns out that 71 is in an OFF state.

A case will be described below in which the motor release signal 156 is at the "H" level, that is, the motor is not in a free-run state.

FIG. 14 is a diagram showing signals inside the output circuit for the PWM inverter of FIG. 13. First, when the switching command signal 42 changes from "L" level to "H" level, the on-delay circuit 66 turns on-delay. The upper arm control signal 81 is changed from "L" level to "H" with a delay of time TD.
Change to level. When the upper arm control signal 81 is set to the “H” level, the power transistor 70 is turned on. In the meantime, the operation delay time TX1 of the base drive circuit 68 and the power transistor 70 exists. The operation delay time TX1 fluctuates due to changes in the temperature of the power transistor 70 and the value of the current flowing through the collector, and also changes due to variations and aging of components constituting the base drive circuit and the power transistor.

When the switching command signal 42 is "L"
When the level changes from the “H” level to the “H” level, the inverted switching signal 80 changes from the “H” level to the “L” level,
The ON delay circuit 67 sets the lower arm control signal 82 to the “L” level with almost no time delay. When the lower arm control signal 82 is set to “L” level, the power transistor 71
Is turned off, and there is an operation delay time TY2 between the base drive circuit 69 and the power transistor 71 during that time. This operation delay time TY2 is equal to the power transistor 71.
Fluctuates due to changes in the temperature of the
It also changes due to variations in components and power transistors constituting the base drive circuit and aging.

Next, when the switching command signal 42 changes from the "H" level to the "L" level, the on-delay circuit 66 changes the upper arm control signal 81 to the "L" level with almost no time delay, and the power transistor 70 is turned off. However, there is an operation delay time TY1 between the base drive circuit 68 and the power transistor 70 in the meantime.

When the switching command signal 42 is "H"
When the level changes from the “L” level to the “L” level, the inverted switching signal 80 changes from the “L” level to the “H” level,
The on-delay circuit 67 changes the lower arm control signal 82 from 'L' level to 'H' level with a delay of the on-delay time TD. When the lower arm control signal 82 is set to the “H” level, the power transistor 71 is turned on. In the meantime, the operation delay time TX2 of the base drive circuit 69 and the power transistor 71 exists.

Here, when the operation delay time TX1 or TX2 is compared with the operation delay time TY1 or TY2, the operation delay time TY1 or TY2 is generally longer than the operation delay time TX1 or TX2. Tend. The shortest value in consideration of the worst condition of the operation delay time TX1 and the operation delay time TX2 is defined as TXW, and the operation delay time TY1 and the operation delay time T
Assuming that the longest value in consideration of the worst condition of Y2 is TYW, the normal on-delay time TD is set to a value obtained by subtracting TXW from TYW and adding some margin.
Normally, the on-delay time TD is set to about 10 to 50 microseconds using a bipolar type power transistor, and is set to about 5 to 30 microseconds using an IGBT.
-Uses FET and is set to about 2 to 10 microseconds. Thus, when the switching command signal 42 changes from the “H” level to the “L” level or from the “L” level to the “H” level, the power transistor 70 and the power transistor 71 are simultaneously turned ON, and the DC A short circuit between the plus terminal and the minus terminal of the power supply 14 is prevented.

From the above, considering the switching command signal 42 and the state of the motor winding terminal voltage 51,
First, when the switching command signal 42 is fixed at the "L" level, the power transistor 70 is OFF and the power transistor 71 is ON, so that the motor winding terminal 52 is connected to the minus terminal of the DC main power supply 14. When the switching command signal 42 is fixed at "H" level, the power transistor 7
Since 0 is ON and the power transistor 71 is OFF, the motor winding terminal 52 is connected to the plus terminal of the DC main power supply 14.

[0018]

However, in the above conventional configuration, when the motor release signal 156 is at the "H" level, that is, when the motor is in a non-free-run state, the switching command signal 42 is changed from the "L" level to the "L" level. When the voltage changes to the H level or the voltage changes from the H level to the L level, the power transistor 70 and the power transistor 71 are both turned off for a certain period of time. Control error. This control error causes a problem that the generated torque and the rotation speed of the electric motor fluctuate, and the noise and vibration of the electric motor also increase.

This will be described in more detail. 13 and FIG. 14, the switching command signal 42 is “L”.
When the level changes from the “H” level to the “H” level, or when the level changes from the “H” level to the “L” level, the power transistor that has been turned on is turned off first, and then the power transistor that has been turned off is turned on. Therefore, the power transistor 70 and the power transistor 71 are both turned off for a certain time. This state is called a floating state, and this time is called a floating time TZ. Generally, the floating time TZ is often about 1/2 to 2/3 of the ON delay time TD.

Generally, the PWM control of a motor is originally performed by alternately connecting a motor winding terminal to a plus terminal and a minus terminal of a DC main power supply, and reducing a ratio of a time for connecting to the plus terminal to a time for connecting to the minus terminal. The average voltage of the motor winding terminal is controlled accordingly. Therefore,
When the voltage of the DC main power supply 14 is constant, it is ideal that the average voltage of the motor winding terminal 52 can be uniquely controlled according to the ratio of the time between the “H” level and the “L” level of the switching command signal 42. It is.

However, in the conventional output circuit for a PWM inverter, since the floating state exists, the average voltage of the motor winding terminal varies depending on the direction of the current flowing through the motor winding terminal. That is, the motor winding terminal 5
2, when the current flows in the direction in which the current flows into the PWM inverter output circuit 53, the diode 78 conducts when the floating state occurs, and the motor winding terminal 52 is connected to the plus terminal of the DC main power supply 14. Becomes
This state is shown as a motor winding terminal voltage 51A in FIG.
Conversely, when a current flows from the PWM inverter output circuit 53 to the motor winding terminal 52 in a floating state in a floating state, the diode 79 conducts and the motor winding terminal 52 is connected to the minus terminal of the DC main power supply 14. It will be in the state that was done. This state is shown as a motor winding terminal voltage 51B in FIG. In the floating state, when no current flows through the motor winding terminal 52, the voltage of the motor winding terminal 52 becomes a voltage determined by an induced voltage generated inside the motor 60 and the like.

As described above, since there is a floating state, the switching command signal 42 and the motor winding terminal 52
, The control voltage is not uniquely determined, causing a control error. Normally, since the direction of the current flowing through the motor winding terminal 52 is changed by alternating current, the control error also changes accordingly, and the generated torque and the rotation speed of the motor 60 fluctuate. This problem can be solved by eliminating the floating state and setting the floating time to 0. However, in the conventional PWM inverter output circuit, a short circuit occurs between the plus terminal and the minus terminal of the DC main power supply 14, which is practically impossible. is there.

Further, electrical noise is generated when the power transistor is turned on or off. In particular, in applications where it is desired to reduce the noise, the switching speed is reduced by, for example, connecting a capacitor between the base and the emitter of the power transistor. There are cases. However, this causes the operation delay times TX1, TX2, TY1 and TY2
Becomes very large, and the floating time has to be further increased. Therefore, the control error increases, and as a result, the switching speed cannot be reduced much.

A conventional PWM inverter output circuit of the type in which the power transistor 70 and the power transistor 71 of FIG.
There is also a conventional PWM inverter output circuit of a type in which the power transistor 70 and the power transistor 71 are replaced with power MOS-FETs, respectively, but the operation is exactly the same as that of the PWM inverter output circuit shown in FIG. 13 and has a floating state. .

An object of the present invention is to solve the above-mentioned problem. The floating state is essentially eliminated, the floating time is zero, and the switching command signal and the average voltage of the motor winding terminal are uniquely determined. Accordingly, it is an object to provide an output circuit for a PWM inverter which does not cause a control error and consumes less power at a low cost.

[0026]

In order to achieve this object, an output circuit for a PWM inverter according to the present invention comprises an N-channel type first junction type FET, a P-channel type second junction type FET, First and second diodes, current control means 1 having a current output terminal and controlling a current flowing out of the current output terminal, and a current having a current input terminal and controlling a current flowing from the current input terminal A control means for connecting a drain of the first junction type FET, a cathode of the first diode and a plus terminal of the DC main power supply, and a drain of the second junction type FET; The anode of the diode is connected to the negative terminal of the DC main power supply, and the source of the first junction type FET is connected to the first terminal.
The anode of the diode, the source of the second junction FET and the cathode of the second diode are connected, and the gate of the first junction FET, the gate of the second junction FET, and the current output of the current control means 1 are connected. Voltage limiting means for connecting a resistor and a current input terminal of the current control means 2 and having a resistance between the gate and the source of the first or second junction type FET and having a Zener phenomenon with respect to positive and negative bidirectional voltages; Are connected in parallel, and the current control means 1 and the current control means 2 use the current flowing from the current output terminal of the current control means 1 as a first current value, and the current control means 2
And a current flowing from the current output terminal of the current control means 1 as a second current value, and a first state in which a current flowing from the current input terminal of the current control terminal 1 is set as a seventh current value. A second state in which the current flowing from the terminal is set to an eighth current value, and a current flowing out of the current output terminal of the current control unit 1 is set to a fifth current value and the current flowing from the current input terminal of the current control unit 2 The third current value as the third current value
And a fourth state in which the current flowing from the current output terminal of the current control means 1 is a sixth current value and the current flowing from the current input terminal of the current control means 2 is a fourth current value. A fifth state in which the current flowing from the current output terminal of the current control means 1 is a ninth current value, and the current flowing from the current input terminal of the current control means 2 is also a ninth current value; The first current value is a current value larger than the seventh current value, the second current value is a current value larger than the eighth current value, and the third current value is a fifth current value. The fourth current value is larger than the sixth current value, and the fourth current value is larger than the sixth current value.
Is larger than the difference between the second current value and the eighth current value, and the difference between the third current value and the fifth current value is the difference between the third current value and the fifth current value. And the sixth current value.
The current value is larger than the difference between the first state and the second state and the fifth state can be shifted only from the first state, and the second state can be shifted only to the third state and the fifth state. From the third state to the fourth state and the fifth state only,
Only the first state and the fifth state can be shifted from the fourth state, and at least the first state and the third state can be shifted from the fifth state.
The state can be shifted to the state.

[0027]

According to this structure, the first and second junction FETs are essentially safe from being simultaneously turned ON, and the floating time is essentially zero, so that the control error is very small, and An output circuit for a PWM inverter with low power consumption can be realized.

[0028]

【Example】

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is an N-channel type junction FET, and 2 is a P-channel type junction FE.
T, 5 and 6 are diodes, 125 and 126 are current control means, 109 is a signal processing means, 14 is a DC main power supply, 15 and 16 are DC power supplies, 105 is a resistor, 97 is a voltage limit means and Zener diodes 95 and 96
It is composed of

The operation of the output circuit for a PWM inverter configured as described above will be described.

Numeral 65 denotes a logic inverting means, which outputs the result of logically inverting the switching command signal 42 as an inverted switching signal 8
Output as 0.

Reference numerals 106 and 107 denote logical AND negation means.
6 is a motor release signal 156 and an inverted switching signal 80
Is output, and 107 outputs a result obtained by performing a logical negation of the motor release signal 156 and the switching command signal 42.

For the sake of simplicity, a description will first be given of the case where the motor release signal 156 is at the "H" level, that is, a command not in a free-run state. Finally, the motor release signal 156 is at the "L" level. The level, that is, the case where the free-run state is commanded, will be added.

First, the operation of the current control means 125 and the current control means 126 will be described in detail with reference to FIG.

The base signal 123 of the PNP-type transistor 119 generates the switching command signal 42 through the logical product negation means 107, the photocoupler 115 and the logic inversion means 111. The base signal 123 has, for example, the same potential as the plus terminal of the DC power supply 15 when the switching command signal 42 is at the “L” level, and has a potential 5 V lower than the plus terminal of the DC power supply 15 when the switching command signal 42 is at the “H” level.

Next, a P-channel type MOS-FE
The gate signal 124 of T120 is the switching command signal 4
2 is generated through the logical product negation means 107, the photocoupler 115, the logic inversion means 112 and 113, and the signal delay means 114. The gate signal 124 is obtained by delaying the switching command signal 42 by the delay time TA, and is "L".
The level is set to a voltage at which the MOS-FET 120 can be sufficiently turned on, and the “H” level is set to the MOS-FET 12
0 is a voltage that can be sufficiently turned off.

The transistor 119 has an emitter-follower circuit configuration, and the potential of the base signal 123 is
5 becomes lower than the potential of the plus terminal by about 0.7 V or more, a current determined by the value of the resistor connected to the emitter and the voltage applied thereto flows as the collector current 49, and the potential of the base signal 123 and the DC power supply 15 When the difference from the potential of the plus terminal is about 0.7 V or less, the collector current 49 becomes zero.

The MOS-FET 120 is the transistor 11
When the MOS-FET 120 is turned on in a state where the potential of the base signal of the transistor 119 is lower than the potential of the plus terminal of the DC power supply 15 by about 0.7 V or more, the resistance of the resistor connected to the emitter of the transistor 9 is changed. This has the effect of increasing the collector current 49 of the transistor 119.

Here, considering the relationship between the switching command signal 42 and the collector current 49, when the switching command signal 42 is at the "L" level, the collector current 49 becomes zero.
Next, the collector current 49 becomes a relatively large current value until the delay time TA elapses after the switching command signal 42 changes to the “H” level, and then becomes a relatively small current value. Becomes "L" level, collector current 49 becomes zero.

The base signal 45 of the NPN type transistor 29 generates the switching command signal 42 through the logic inversion means 65 and 23 and the logical product negation means 106. The base signal 45 is almost the same as a signal obtained by logically inverting the switching command signal 42. It is assumed that the “L” level has a value of, for example, 0V and the “H” level has a value of, for example, 5V.

Next, an N-channel type MOS-FE
The gate signal 46 of T31 converts the switching command signal 42 into the logical inversion means 1 with the logical inversion means 65, 24 and 25.
06 and signal delay means 27.

The gate signal 46 is obtained by delaying the switching command signal 42 by the delay time TB. The "L" level is set to a voltage which can sufficiently turn off the MOS-FET 31, and the "H" level is set to a voltage which allows the MOS-FET 31 to be turned off. A voltage that can be sufficiently turned on.

The transistor 29 has an emitter-follower type circuit configuration. When the base signal 45 becomes about 0.7 V or more, a collector current 48 determined by the voltage of the base signal 45 and the value of the resistor connected to the emitter flows. Is less than about 0.7 V, the collector current 48 becomes zero. The MOS-FET 31 functions to switch the value of a resistor connected to the emitter of the transistor 29. When the base signal of the transistor 29 is about 0.7 V or more, the MOS-FET 31
When the FET 31 is turned on, the collector current 48 of the transistor 29 is increased.

Considering the relationship between the switching command signal 42 and the collector current 48, when the switching command signal 42 is at the "H" level, the collector current 48 becomes zero.
Then, after the switching command signal 42 changes to the “L” level, the collector current 4 is maintained until the delay time TB elapses.
8 becomes a relatively large current value, then becomes a relatively small current value, and when the switching command signal 42 becomes the "H" level, the collector current 48 becomes 0.

In summary, the collector current 49 changes to the first current value 1 according to the switching command signal 42.
64, the collector current 48 has a seventh current value 170, and the collector current 49 has a second current value 165.
And the collector current 48 is set to the eighth current value 171.
And the third state in which the collector current 49 is the fifth current value 168 and the collector current 48 is the third current value 166, and the collector current 49 is the sixth current value 169 and the collector current 48 is the fourth current value. It can be seen that there is a fourth state with a current value of 167, and the fourth state is repeatedly realized in order from the first state.

However, in this embodiment, the fifth current value 168, the sixth current value 169, the seventh current value 170,
The eighth current value 171 is set to 0.

The operation of the current control means 125 and 126 has been described above. Next, voltage limit means 9
The function of No. 7 will be described.

The voltage limiting means 97 composed of the Zener diodes 95 and 96 is connected to the transistor 119 so that the transistor 119 of the current control means 125 does not saturate at least when the second current value 165 flows.
At the same time as limiting the upper limit of the gate voltage of the junction type FETs 1 and 2. The voltage limiting means 97 constituted by the Zener diodes 95 and 96 sets the lower limit of the collector voltage of the transistor 29 so that the transistor 29 of the current control means 126 does not saturate at least when the fourth current value 167 flows. It functions to limit the lower limit of the gate voltage of the junction type FETs 1 and 2 at the same time.

The upper limit of the gate voltage of the junction type FETs 1 and 2 is a voltage at which the junction type FET 1 can be sufficiently turned on, a voltage at which the junction type FET 2 can be sufficiently turned off, and the gates of the junction type FETs 1 and 2. It must be a value that does not exceed the breakdown voltage between the source and the source. Also, the joint type FE
The lower limit of the gate voltages of T1 and T2 is a voltage at which the junction FET2 can be sufficiently turned on, a voltage at which the junction FET1 can be sufficiently turned off, and does not exceed the breakdown voltage between the gate and the source of the junction FET1 and 2. Must be a value.

Generally, an N-channel type junction type FE
The breakdown voltage between the gate and the source of T is often about ± 20 V to ± 30 V, and the gate voltage threshold for starting conduction between the drain and the source is +1 V to ++ with respect to the source voltage.
Many are about 5V. On the other hand, the breakdown voltage between the gate and the source of the P-channel type junction FET is ± 20V to ± 30V.
V, and the gate voltage threshold at which conduction between the drain and source starts is -1 with respect to the source voltage.
Many have a voltage of about V to -5V.

FIG. 3 shows the relationship between the switching command signal 42 and the gate signal voltage 50 based on the minus terminal of the DC main power supply 14. First, when the switching command signal 42 changes from the "L" level to the "H" level, the collector current 49 of the transistor 119 flows, the gate signal voltage 50 rapidly rises, and the Zener diodes 95 and 9
The voltage is fixed when 6 becomes conductive. The rising time TR required for the gate signal voltage 50 to rise is the junction type F
It is determined from the relationship between the capacitance included in ET1 and ET2 and the Zener diodes 95 and 96 and the collector current 49. Further, when the Zener diodes 95 and 96 are conducting, the gate signal voltage 50 does not largely change, so that even if the collector current 49 is a very small current, the voltage can be maintained. Setting above is sufficient. Therefore, if the delay time TA of the signal delay unit 114 is set to be slightly longer than the rise time TR, the rise time TR can be reduced, and the power loss of the transistor 119 and the resistor 122 can be minimized.

Next, the switching command signal 42 becomes "H".
When the level changes from the “L” level to the “L” level, the transistor 2
The collector current 48 of 9 flows and the gate signal voltage 50 drops sharply, and the voltage is fixed when the Zener diodes 95 and 96 become conductive. The time TF required for the gate signal voltage 50 to fall is determined by the relationship between the capacitance included in the junction type FETs 1 and 2 and the Zener diodes 95 and 96 and the collector current 48. In addition, when the Zener diodes 95 and 96 are conducting, the gate signal voltage 50 does not greatly change. Therefore, even if the collector current 48 is a very small current, the voltage can be maintained. Setting above is sufficient. Therefore, if the delay time TB of the signal delay means 27 is set to be slightly longer than the fall time TF, the fall time TF can be reduced, and the power loss of the transistor 29 and the resistor 35 can be minimized.

Next, the operation of the junction type FETs 1 and 2 will be described. Since the junction type FETs 1 and 2 have their gates and sources connected in common, when the gate signal voltage 50 becomes higher than the motor winding terminal voltage 51 by the gate voltage threshold value of the junction type FET 1, the junction type FET 1 is switched from the drain to the source. , The gate signal voltage 50 is higher than the motor winding terminal voltage 51 and the junction FET 2
When the gate voltage becomes lower than or equal to the gate voltage threshold value, the junction type FET 2 starts flowing current from the source to the drain. Therefore, the gate signal voltage 50 and the motor winding terminal voltage 51
Is always within a certain range, and the junction FET
It is essentially impossible for 1 and 2 to flow current at the same time and the plus terminal and the minus terminal of the DC main power supply 14 are short-circuited.

Next, the operation of the diodes 5 and 6 will be described. Generally, a simple equivalent circuit of a motor winding is represented as a series connection of a resistance, an inductance, and a voltage source corresponding to an induced voltage. Therefore, unlike the pure resistance load, the direction of the current flowing through the motor winding terminal 52 is not uniquely determined by the voltage applied to the motor winding terminal 52, and the junction FET1 is ON and the junction FET2 is OFF.
State F in which current flows out of the motor from the motor winding terminal 52 to the motor, state in which the junction FET 1 is ON and junction FET 2 is OFF, and current flows from the motor into the motor winding terminal 52 B state and the junction type FET1 is O
The state of C in which the FF is set, the junction FET 2 is ON, and a current flows from the motor to the motor winding terminal 52, and the junction FET 1 is OFF, the junction FET 2 is ON, and the motor is connected to the motor winding terminal 52. Current is flowing to D
There are four states. First, in the state of A, the current flowing through the motor winding terminal 52 is the junction type FET1.
It can be seen that it flows through. Further, in the state C, the current flowing through the motor winding terminal 52 flows through the junction FET 2. Further, it can be seen that in the states B and D, the current flowing through the motor winding terminal 52 flows through the diode 5 and the diode 6, respectively. Here, it can be seen that the motor winding terminal voltage 51 in the state B rises due to the current flowing through the motor winding terminal 52 and is fixed when the diode 5 becomes conductive. This diode 5
If the reverse recovery time trr is long, the switching loss increases. Therefore, it is preferable to select the diode 5 having a short reverse recovery time as much as possible. Similarly, the motor winding terminal voltage 51 in the state D falls due to the current flowing through the motor winding terminal 52 and is fixed when the diode 6 becomes conductive. If the reverse recovery time trr of the diode 6 is long, switching loss increases. Therefore, it is preferable to select a diode 6 having a short reverse recovery time as much as possible.

According to the above description, the switching command signal 4
When 2 is set to the “H” level, it is understood that the motor winding terminal 52 is connected to the plus terminal of the DC main power supply 14. Further, when the switching command signal 42 is set to the “L” level, the motor winding terminal 52 is connected to the minus terminal of the DC main power supply 14, and when the switching command signal 42 is changed from the “H” level to the “L” level, It can be seen that the floating time is essentially zero even when the level is changed from the “L” level to the “H” level.

Further, by changing the current values of the collector current 49 of the transistor 119 and the collector current 48 of the transistor 29, the rise time T of the gate signal voltage 50 is increased.
R and the fall time TF can be freely set within a certain range, and accordingly, the rise time and the fall time of the motor winding terminal voltage 51 can be freely set within a certain range. Normally, motor winding terminal voltage 5
As the rise time and fall time of No. 1 are reduced, the joint type F
It is preferable because the power loss of the ET1 and the junction type FET2 can be reduced, but there is a disadvantage that electric noise increases. Therefore, it is necessary to increase the rise time and the fall time of the motor winding terminal voltage 51 in an application in which electric noise is particularly desired to be reduced, and this configuration can easily cope with this.

It is needless to say that the rise time and the fall time of the motor winding terminal voltage 51 can be greatly increased by connecting a capacitor between the gate and the source of each of the junction type FETs 1 and 2 in FIG.

The above is the description of the operation of the current control means 125 and 126 when the motor release signal 156 is at the "H" level, that is, when the motor is not in a free-run state. L '
The level, that is, the operation of the current control means 125 and 126 when the free-run state is commanded will be added.

When the motor release signal 156 is at the "L" level, that is, when the motor is in the free-run state, the output signals of the AND circuits 106 and 107 are both at the "H" level regardless of the switching command signal 42. Therefore, the base signal 123 of the transistor 119 of the PNP type becomes "H" level, and the base signal 45 of the transistor 29 becomes "L" level.

This state is a so-called fifth state, in which the collector current 49 and the collector current 48, which are the ninth current values, are set.
Are both 0.

In the fifth state, the gate signal voltage 50 of the junction type FETs 1 and 2 becomes substantially the same potential as the motor winding terminal voltage 51 by the resistor 105. Therefore, the junction FETs 1 and 2 are both turned off, and a free-run state can be realized. The fifth state is mainly used for interrupting the operation of the electric motor to protect the electric motor and the control device when some trouble occurs.
The transition to the fifth state includes the first state, the second state,
The state can be changed from any of the third state and the fourth state, and shifts to the moment when the motor release signal 156 changes to the “L” level. Conversely, the fifth state is configured to shift to the first state or the third state at the moment when the motor release signal 156 changes to the “H” level. this is,
When the state changes from the fifth state to the second state or the fourth state, the time required for the gate signal voltage 50 to rise or fall becomes extremely long, and excessive heat is generated in the junction type FETs 1 and 2. It is.

However, the transition from the fifth state to another state is mainly for the purpose of resuming the operation of the motor, which has been interrupted. In this case, the frequency is increased once every few seconds. Since it is as low as the number of times, if the resistance of the junction type FETs 1 and 2 is sufficient, it is possible to adopt a configuration in which the state can be shifted from the fifth state to all other states.

It should be noted that the current control means 125 and 126 of the present embodiment are provided with the fifth current value 168 and the sixth current value 16
9, the seventh current value 170 and the eighth current value 171 are set to 0.
Where the first current value 164 is the seventh current value 17
The current value is larger than 0, and the second current value 165 is the eighth current value.
And the third current value 166 is a current value larger than the fifth current value 168,
The fourth current value 167 is a current value larger than the sixth current value 169, and the first current value 164 and the seventh current value 170
Is larger than the difference between the second current value 165 and the eighth current value 171, and the third current value 166 and the fifth current value 168
Is larger than the difference between the fourth current value 167 and the sixth current value 169, the fifth current value 168 and the sixth current value 1
Needless to say, 69, the seventh current value 170 and the eighth current value 171 can be set to values other than 0.

FIG. 2B shows an example. Further, the ninth current value in the fifth state is also set to 0 by the current control means 125 and 126 in the present embodiment, but it goes without saying that the ninth current value can also be set to a value other than 0.

That is, if the collector current 49 of the transistor 119 and the collector current 48 of the transistor 29 have the same current value, they can be set to values other than 0.

(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

In FIG. 4, 1 is an N-channel type junction FET, and 2 is a P-channel type junction FE.
T, 5 and 6 are diodes, 126 is current control means,
109 is a signal processing means, 14 is a DC main power supply, 15 and 16 are DC power supplies, 105 is a resistor, 97 is a voltage limiting means composed of zener diodes 95 and 96,
The above is the same as the configuration in FIG.

The difference from the configuration of FIG.
25 is constituted by a current mirror means 98 and a current control means 127.

The operation of the current mirror means 98 and the current control means 127 of the PWM inverter output circuit configured as described above, which is different from the configuration of FIG. 1, will be described.

Here, for the sake of simplicity, first, all the cases where the motor release signal 156 is at the "H" level, that is, when the motor is not in a free-run state, will be described.
Finally, a description will be given of a case where the motor release signal 156 is at the "L" level, that is, the motor is in the free-run state.

First, the operation of the current control means 127 will be described in detail with reference to FIG. NPN type transistor 2
The base signal 43 of 8 generates the switching command signal 42 through the logical product negation means 107 and the logic inversion means 20. The base signal 43 is almost the same as the switching command signal 42, and it is assumed that the “L” level takes a value of, for example, 0V and the “H” level takes a value of, for example, 5V. Next, the gate signal 44 of the N-channel type MOS-FET 30 generates the switching command signal 42 through the logic inversion means 21 and 22, the logical product negation means 107, and the signal delay means 26. The gate signal 44 is obtained by delaying a signal obtained by logically inverting the switching command signal 42 by a delay time TA.
F, and set the 'H' level to MOS
-A voltage that can sufficiently turn on the FET 30. The transistor 28 has an emitter-follower type circuit configuration. When the base signal 43 becomes about 0.7 V or more, a collector current 47 determined by the voltage of the base signal 43 and the value of the resistor connected to the emitter flows, and the base signal 43 becomes about 0 V. .7
When the voltage is equal to or lower than V, the collector current 47 becomes zero. MOS
The FET 30 functions to switch the value of the resistor connected to the emitter of the transistor 28. When the base signal of the transistor 28 is about 0.7 V or more, the MOS-FET 3
When 0 is turned on, the collector current 47 of the transistor 28 is increased.

Here, considering the relationship between the switching command signal 42 and the collector current 47, when the switching command signal 42 is at the "L" level, the collector current 47 becomes zero.
Then, after the switching command signal 42 changes to the “H” level, the collector current 4 is maintained until the delay time TA elapses.
7 has a relatively large current value, and then has a relatively small current value. When the switching command signal 42 becomes the "L" level, the collector current 47 becomes zero.

The above is the description of the operation of the current control means 127. Next, the operation of the current mirror means 98 will be described.

The resistors 11 and 12 and the transistors 9 and 10 have a current mirror configuration with each other, and serve to make the collector current 49 of the transistor 9 a current corresponding to the collector current 47 of the transistor 28 within a range where the transistor 9 is not saturated. .

Voltage limiting means 97 composed of Zener diodes 95 and 96 limits the upper limit of the collector voltage of transistor 9 so that transistor 9 does not saturate at least when the second current value 165 flows. .

Here, considering the relationship between the switching command signal 42 and the collector current 49 of the transistor 9, when the switching command signal 42 is at "L" level, the collector current 49 is 0, and then the switching command signal 42 is at "H". The collector current 49 becomes a relatively large current value until the delay time TA elapses from the change to the level, and then becomes a relatively small current value.
Becomes "L" level, collector current 49 becomes zero.

The operation of the current control means 127 and the current mirror means 98 when the motor release signal 156 is at the "H" level, that is, when the motor is not in the free-run state, has been described. 1
The operation of the current control means 127 and the current mirror means 98 when the signal 56 indicates the "L" level, that is, the free-run state is added. When the motor release signal 156 is at the "L" level, that is, when the motor is in the free-run state, the output signal of the logical product negation means 107 is at the "H" level regardless of the switching command signal 42. 28
Becomes the 'L' level. This state is
The collector current 47 is 0, and the collector current 49 of the transistor 9 is also 0. This is the so-called fifth state.

As described above, it can be seen that the current mirror means 98 and the current control means 127 perform the same operations as the current control means 125.

Also in FIGS. 4, 6 and 7, by connecting a capacitor between the gate and the source of each of the junction type FETs 1 and 2, the motor winding terminal voltage 51
It is needless to say that the rise time and the fall time can be greatly increased.

It goes without saying that the PNP type transistor 10 in FIG. 4 may be expressed as a diode.

(Embodiment 3) A third embodiment of the present invention will be described below with reference to the drawings.

In FIG. 6, 1 is an N-channel type junction type FET, and 2 is a P-channel type junction type FE.
T, 5 and 6 are diodes, 126 and 127 are current control means, 109 is a signal processing means, 14 is a DC main power supply, 15 and 16 are DC power supplies, 105 is a resistor, and 97 is a Zener diode 95 and 96. The voltage limiting means has the same configuration as that of FIG.

4 is different from the structure of FIG. 4 in that current mirror means 98, which is composed of PNP type transistors 9 and 10, and resistors 11 and 12, is simply simplified by PNP type transistor 9 and resistors 11 and 12. This is the point that constitutes the means.

The current mirror means in FIG. 6 is inferior to the current mirror means in FIG. 4 in accuracy and temperature characteristics, so that it is necessary to increase the voltage of the DC power supply 15. However, if this is permitted, there is no practical problem. Absent.

(Embodiment 4) A fourth embodiment of the present invention will be described below with reference to the drawings.

In FIG. 7, 1 is an N-channel type junction type FET, and 2 is a P-channel type junction type FE.
T, 5 and 6 are diodes, 126 and 127 are current control means, 109 is a signal processing means, 14 is a DC main power supply, 15 and 16 are DC power supplies, 105 is a resistor, and 97 is a Zener diode 95 and 96. The voltage limiting means has the same configuration as that of FIG.

4 is different from the configuration of FIG. 4 in that the current mirror means 98 which has been constituted by PNP type transistors 9 and 10 and resistors 11 and 12 is replaced by a PNP type transistor 9, an NPN type transistor 128, a diode 129 and a resistor. 11 and 130 constitute a current mirror means.

In the current mirror means shown in FIG.
When the collector voltage of the NP transistor 9 falls, PN
The base voltage of the P transistor 9 is equal to the collector output capacitance Co.
The current drops through b, causing the PNP transistor 9 to turn on. As a result, a current leaks to the collector of the PNP transistor 9, and the gate signal voltage 5
The fall time of 0 becomes long, and the switching loss of the junction FET increases. Therefore, to prevent this,
The PNP type transistor 9 is connected to the collector output capacitance Co.
It is necessary to select one with a very small b.

On the other hand, in the current mirror means shown in FIG. 7, when the collector voltage of the PNP transistor 9 falls, the current flowing through the collector output capacitance Cob becomes NP.
Since the current is compensated by the emitter current of the N-transistor 128, a decrease in the base voltage of the PNP transistor 9 can be prevented. be able to.

(Embodiment 5) Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings.

In FIG. 8, 1 is an N-channel type junction type FET, and 2 is a P-channel type junction type FE.
T, 5 and 6 are diodes, 109 is signal processing means,
14 is a DC main power supply, 15 and 16 are DC power supplies, 105
Is a resistor, and 97 is a voltage limiting means composed of Zener diodes 95 and 96. The above is the same as the configuration of FIG.

The difference from the configuration of FIG.
26 is a current mirror unit 132 and a current control unit 131
And the current control means 125 is replaced with the current control means 16.
3

The operation of the current mirror unit 132 and the current control unit 131 of the PWM inverter output circuit configured as described above, which differs from the configuration of FIG. 1, will be described.

Here, for the sake of simplicity, all the cases where the motor release signal 156 is at the "H" level, that is, a command not in a free-run state will be described.
Finally, a description will be given of a case where the motor release signal 156 is at the "L" level, that is, the motor is in the free-run state.

First, the operation of the current control means 131 will be described in detail with reference to FIG. PNP type transistor 1
The base signal 148 of 37 generates the switching command signal 42 through the logical product negation means 106 and the logic inversion means 65, 161 and 139. The base signal 148 has the same potential as, for example, the plus terminal of the DC power supply 15 when the switching command signal 42 is at the “H” level, and has a potential that is, for example, 5 V lower than the plus terminal of the DC power supply 15 when the switching command signal 42 is at the “L” level.

Next, a P-channel type MOS-FE
The gate signal 149 of T138 is the switching command signal 4
2 is generated through the logical inversion means 65, 161, 140 and 141, the logical product negation means 106, and the signal delay means 142. The gate signal 149 is obtained by logically inverting the switching command signal 42 and delaying the switching command signal 42 by the delay time TB, and setting the “L” level to sufficiently turn on the MOS-FET 138.
And the “H” level is set to MOS-
The voltage is such that the FET 138 can be sufficiently turned off.

The transistor 137 has an emitter-follower type circuit configuration, and the potential of the base signal 148 is
5, the current determined by the value of the resistor connected to the emitter and the voltage applied thereto flows almost as a collector current 150, and the potential of the base signal 148 and the DC power supply 15 When the difference from the potential of the plus terminal is about 0.7 V or less, the collector current 15
0 becomes 0.

The MOS-FET 138 is a transistor 13
When the MOS-FET 138 is turned on in a state where the potential of the base signal of the transistor 137 is lower than the potential of the plus terminal of the DC power supply 15 by about 0.7 V or more, the resistance of the resistor connected to the emitter of the transistor 7 is changed. This has an effect of increasing the collector current 150 of the transistor 137.

Considering the relationship between the switching command signal 42 and the collector current 150, when the switching command signal 42 is at the "H" level, the collector current 150 is 0, and then the switching command signal 42 is at the "L" level. Until the delay time TB elapses, the collector current 150 becomes a relatively large current value, and then becomes a relatively small current value. When the switching command signal 42 becomes the "H" level, the collector current 150 becomes 0. .

The above is the description of the operation of the current control means 131. Next, the operation of the current mirror unit 132 will be described.

Resistors 135 and 136 and Transistor 1
33 and 134 have a current mirror configuration with each other,
As long as the transistor 133 is not saturated, the collector current 48 of the transistor 133
And a current corresponding to the collector current 150.

The voltage limiting means 97 constituted by the Zener diodes 95 and 96 limits the lower limit of the collector voltage of the transistor 133 so that the transistor 133 does not saturate at least when the fourth current value 167 flows. .

Here, considering the relationship between the switching command signal 42 and the collector current 48 of the transistor 133, when the switching command signal 42 is at "H" level, the collector current 48 is 0, and then the switching command signal 4
2 changes to the “L” level and the collector current 48 has a relatively large current value until the delay time TB elapses,
Next, the current value becomes relatively small, and when the switching command signal 42 becomes the “H” level, the collector current 48 becomes 0.

The above is the description of the current control means 131 and the current mirror means 132 when the motor release signal 156 is at the "H" level, that is, when it is instructing that the motor is not in a free-run state.
The operation of the current control unit 131 and the current mirror unit 132 when the motor release signal 156 is at the "L" level, that is, when the motor is in the free-run state, will be described.

When the motor release signal 156 is at the "L" level, that is, when the motor is in the free-run state, the output signal of the logical product negation means 106 is at the "H" level regardless of the switching command signal 42. The base signal 148 of the type transistor 137 becomes “H” level. In this state, the collector current 150 is 0 and the collector current 48 of the transistor 133 is also 0.
This is the so-called fifth state.

As described above, the current mirror means 132
It can be understood that the current control means 131 performs the same operation as the current control means 126.

Further, current control means 1 different from the configuration of FIG.
63 is that the photocoupler 115 of the current control means 125 is replaced with a logic inversion means 162.

This is because the current control means 163 and 131
By operating the logic elements of the signal processing unit 109 and the signal processing unit 109 with a common power supply, there is no need to consider insulation, and the configuration of the current control unit 163 can provide an operation equivalent to that of the current control unit 125.

Also in FIGS. 8, 10 and 11, by connecting a capacitor between the gate and the source of each of the junction type FETs 1 and 2, the rise time and the fall time of the motor winding terminal voltage 51 can be made much longer. It goes without saying that you can do it.

It goes without saying that the NPN type transistor 134 in FIG. 8 may be expressed as a diode.

(Embodiment 6) Hereinafter, a sixth embodiment of the present invention will be described with reference to the drawings.

In FIG. 10, 1 is an N-channel type junction FET, and 2 is a P-channel type junction FE.
T, 5 and 6 are diodes, 131 and 163 are current control means, 109 is a signal processing means, 14 is a DC main power supply, 15 and 16 are DC power supplies, 105 is a resistor, and 97 is a Zener diode 95 and 96. The voltage limit means is the same as that shown in FIG.

The difference from the configuration of FIG. 8 is that NPN type transistors 133 and 134 and resistors 135 and 1
36 is replaced by an NPN
Type transistor 133 and resistors 135 and 136
Thus, the current mirror means is simply configured. The current mirror means in FIG. 10 is inferior in accuracy and temperature characteristics as compared with the current mirror means in FIG. 8, so that it is necessary to increase the voltage of the DC power supply 16, but there is no practical problem when this is permitted.

(Embodiment 7) Hereinafter, a seventh embodiment of the present invention will be described with reference to the drawings.

In FIG. 11, 1 is an N-channel type junction type FET, and 2 is a P-channel type junction type FE.
T, 5 and 6 are diodes, 131 and 163 are current control means, 109 is a signal processing means, 14 is a DC main power supply, 15 and 16 are DC power supplies, 105 is a resistor, and 97 is a Zener diode 95 and 96. The voltage limit means is the same as that shown in FIG.

The difference from the configuration of FIG. 8 is that NPN type transistors 133 and 134 and resistors 135 and 1
36 is replaced by an NPN
Type transistor 133, PNP type transistor 152, diode 153 and resistors 135 and 15.
4 is that the current mirror means is configured.

In the current mirror means shown in FIG.
When the collector voltage of the PN transistor 133 increases,
The base voltage of the NPN transistor 133 rises due to the current flowing through the collector output capacitance Cob, and turns on the NPN transistor 133. This results in leakage of current to the collector of the NPN transistor 133,
The rise time of the gate signal voltage 50 becomes longer and the junction type FET
Switching loss increases.

Therefore, in order to prevent this, it is necessary to select an NPN-type transistor 133 having a very small collector output capacitance Cob.

On the other hand, in the current mirror means shown in FIG. 11, when the collector voltage of the NPN transistor 133 rises, the current flowing through the collector output capacitance Cob can be removed by the emitter current of the PNP transistor 152. 133 can prevent an increase in the base voltage, and is an NPN-type transistor 1
Even if a capacitor 33 having a relatively large collector output capacitance Cob is selected, a configuration in which switching loss is small can be achieved.

When a three-phase PWM inverter is constructed as shown in FIG. 12, three DC inverter output circuits are generally arranged by commonly connecting a DC main power supply. Needless to say, in the inverter output circuit, the DC power supplies 15 and 16 in the first, second, third, fourth, fifth, sixth and seventh embodiments can also be connected in common.

[0121]

As described above, according to the present invention, by adopting the structure of the first embodiment, there is essentially no floating state, the floating time is 0, and the switching command signal and the average voltage of the motor winding terminal are uniquely defined. Excellent PW with very small control error and low power consumption
An M inverter output circuit can be provided at low cost. Further, if necessary, it is possible to provide an excellent output circuit for a PWM inverter which generates very little electric noise at a low cost.

Further, by adopting the configuration of the second embodiment,
The current control means and the signal processing means can be operated by a common power supply, and the same effects as in the first embodiment can be obtained while reducing the number of insulating means such as a photocoupler and DC power supply.

Further, by adopting the configuration of the third embodiment,
The current mirror means can be simply configured, and although the accuracy and temperature characteristics are inferior to those of the second embodiment, the same effects as those of the second embodiment can be obtained at low cost.

Also, by adopting the configuration of the fourth embodiment,
A decrease in the base voltage of the PNP transistor 9 that occurs when the collector voltage of the PNP transistor 9 decreases can be prevented, and the same effect as in the second embodiment can be obtained while reducing the switching loss.

Further, by adopting the configuration of the fifth embodiment,
The same effect as in the second embodiment can be obtained.

Further, by adopting the structure of the sixth embodiment,
The current mirror means can be simply configured, and although the accuracy and the temperature characteristics are inferior to those of the fifth embodiment, the same effects as those of the fifth embodiment can be obtained at low cost.

Further, by adopting the configuration of the seventh embodiment,
An increase in the base voltage of the NPN transistor 133 that occurs when the collector voltage of the NPN transistor 133 increases can be prevented, and the same effect as in the fifth embodiment can be obtained while reducing the switching loss.

[Brief description of the drawings]

FIG. 1 is an output circuit diagram for a PWM inverter according to a first embodiment of the present invention.

FIG. 2A shows the operation of the current control means of the output circuit for a PWM inverter according to the first embodiment of the present invention. FIG. 2B shows the current control of the output circuit for a PWM inverter according to the first embodiment of the present invention. Diagram showing another operation of the means

FIG. 3 is a diagram showing an operation of the output circuit for the PWM inverter according to the first embodiment of the present invention.

FIG. 4 is an output circuit diagram for a PWM inverter according to a second embodiment of the present invention.

FIG. 5 is a diagram showing the operation of the current control means of the output circuit for the PWM inverter according to the second embodiment of the present invention.

FIG. 6 is an output circuit diagram for a PWM inverter according to a third embodiment of the present invention.

FIG. 7 is an output circuit diagram for a PWM inverter according to a fourth embodiment of the present invention.

FIG. 8 is an output circuit diagram for a PWM inverter according to a fifth embodiment of the present invention.

FIG. 9 is a diagram showing the operation of the current control means of the output circuit for the PWM inverter according to the fifth embodiment of the present invention.

FIG. 10 is an output circuit diagram for a PWM inverter according to a sixth embodiment of the present invention.

FIG. 11 is an output circuit diagram for a PWM inverter according to a seventh embodiment of the present invention.

FIG. 12 is a general PWM inverter circuit diagram.

FIG. 13 is a conventional output circuit diagram for a PWM inverter.

FIG. 14 is a diagram showing the operation of a conventional PWM inverter output circuit.

[Explanation of symbols]

1 N-channel type junction type FET 2 P-channel type junction type FET 5, 6, 78, 79, 129, 153 Diode 9, 10, 119, 137, 152 PNP type transistor 11, 12, 32, 33, 34 , 35,83,84,8
5,86,87,88,89,90,91,92,10
5,116,117,121,122,130,13
5,136,146,147,154 Resistance 14 DC main power supply 15,16,93,94,118 DC power supply 20,21,22,23,24,25,65,111,
112, 113, 139, 140, 141, 161, 1
62 logic inversion means 26, 27, 114, 142 signal delay means 28, 29, 74, 75, 76, 77, 128, 13
3,134 NPN type transistor 30,31 N-channel type MOS-FET 42,61,62 Switching command signal 52,63,64 Motor winding terminal 53 PWM inverter output circuit 54 First state 55 Second state 56 Third state 57 Fourth state 58 Frequency voltage setting means 59 PWM control circuit 60 Motor 66, 67 On delay circuit 68, 69 Base drive circuit 70, 71 Power transistor 72, 73, 115 Photocoupler 95, 96 Zener diode 97 Voltage limit means 98, 132 Current mirror means 106, 107 Logical product negation means 109 Signal processing means 120, 138 P-channel type MOS-FETs 125, 126, 127, 131, 163 Current control means 157, 158 Logical product Stage

Continuation of front page (56) References JP-A-5-308778 (JP, A) JP-A-6-70549 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H02M 7 / 48 H02M 7/537 H02P 7/63

Claims (11)

(57) [Claims] 1. An N-channel type first junction type FET
A second junction FET of a P-channel type;
Current control means 1 having a current output terminal and controlling a current flowing out of the current output terminal; current control means having a current input terminal and controlling a current flowing in from the current input terminal And a DC main power supply, wherein the drain of the first junction type FET, the cathode of the first diode and the positive terminal of the DC main power supply are connected, and the drain of the second junction type FET and the second diode are connected to each other. Connecting the anode to the negative terminal of the DC main power supply, connecting the source of the first junction FET, the anode of the first diode, the source of the second junction FET, and the cathode of the second diode, Connecting the gate of the junction type FET, the gate of the second junction type FET, the current output terminal of the current control means 1 and the current input terminal of the current control means 2, A current limiting means having a configuration in which a resistance and a voltage limiting means having a Zener phenomenon with respect to a positive and a negative bidirectional voltage are connected in parallel between the gate and the source of the FET, wherein said current control means 1 and said current control means 2 A first state in which a current flowing from a current output terminal of the current control means 1 is a first current value, and a current flowing from a current input terminal of the current control means 2 is a seventh current value; A second state in which the current flowing from the current output terminal of the control means 1 is a second current value, and the current flowing from the current input terminal of the current control means 2 is an eighth current value; A third state in which the current flowing out of the current output terminal of the current control terminal 2 is a fifth current value and the current flowing in from the current input terminal of the current control means 2 is a third current value; Leaks from the terminal A fourth state in which the current is a sixth current value and a current flowing from the current input terminal of the current control means 2 is a fourth current value, and a current flowing out of the current output terminal of the current control means 1 is a fourth state. There is a fifth state in which the current flowing through the current input terminal of the current control means 2 is set to a ninth current value, and the first current value is larger than the seventh current value. A current value, the second current value is a current value larger than the eighth current value, the third current value is a current value larger than the fifth current value, the fourth current value Is a current value larger than the sixth current value, the difference between the first current value and the seventh current value is larger than the difference between the second current value and the eighth current value, The difference between the third current value and the fifth current value is the difference between the fourth current value and the sixth current value. From the first state to the second state and the fifth state only, from the second state to the third state and the fifth state only, and from the third state Can be shifted only to the fourth state and the fifth state, can be shifted only to the first state and the fifth state from the fourth state, and is at least the first state and the fifth state from the fifth state. 3. An output circuit for a PWM inverter having a configuration capable of shifting to the state of 3. 2. An N-channel type first junction type FET.
A second junction FET of a P-channel type;
And a second diode having a current inflow terminal and first and second current outflow terminals, and having a function of causing a current corresponding to a current flowing out of the second current outflow terminal to flow out of the first current outflow terminal. Current mirror means 1, a current control means 3 having a current input terminal and controlling a current flowing from the current input terminal, and a current control means having a current input terminal and controlling a current flowing from the current input terminal 2, a DC main power supply, and a first DC power supply having a negative terminal connected to a positive terminal of the DC main power supply, and a drain of a first junction FET, a cathode of a first diode, and a power supply of the DC main power supply. A positive terminal is connected, a drain of the second junction FET, an anode of the second diode, and a minus terminal of the DC main power supply are connected, and a source of the first junction FET is connected to the first terminal. The anode of the diode, the source of the second junction FET and the cathode of the second diode are connected, and the gate of the first junction FET, the gate of the second junction FET, and the first of the current mirror means 1 A current outflow terminal of the current control means 2 is connected to a current outflow terminal of the current control means 2, and a second current outflow terminal of the current mirror means 1 is connected to a current input terminal of the current control means 3; A positive terminal is connected to the current inflow terminal of the current mirror means 1, and a resistance between the gate and the source of the first or second junction type FET and a voltage limit having a Zener phenomenon for positive and negative bidirectional voltages. The current mirror means 1 and the current control means 2
However, a current flowing out of a first current outflow terminal of the current mirror means 1 is a first current value, and a current flowing out of a current input terminal of the current control means 2 is a seventh current value.
And a current flowing from a first current outflow terminal of the current mirror means 1 as a second current value and a current flowing from a current input terminal of the current control means 2 as an eighth current value.
And a current flowing out of the first current outflow terminal of the current mirror means 1 as a fifth current value, and a current flowing out of the current input terminal of the current control means 2 as a third current value.
And the current flowing out of the first current outflow terminal of the current mirror means 1 as a sixth current value, and the current flowing out of the current input terminal of the current control means 2 as a fourth current value.
And the current flowing out of the first current outflow terminal of the current mirror means 1 is a ninth current value, and the current flowing out of the current input terminal of the current control means 2 is also a ninth current value.
Wherein the first current value is a current value larger than the seventh current value, the second current value is a current value larger than the eighth current value, and the third current value The current value is a current value larger than the fifth current value, the fourth current value is a current value larger than the sixth current value, and the first current value and the seventh current value are different from each other. The difference is larger than the difference between the second current value and the eighth current value, and the difference between the third current value and the fifth current value is the fourth current value and the sixth current value. The difference from the first state can be changed only to the second state and the fifth state, and the second state can be changed only to the third state and the fifth state. The state can be shifted only to the fourth state and the fifth state, and the state can be shifted only to the first state and the fifth state from the fourth state. An output circuit for a PWM inverter configured to be able to shift from the fifth state to at least the first state and the third state. 3. The current mirror means 1 includes third and fourth transistors of PNP type,
The collector of the third transistor is used as a first current outflow terminal, and the base of the fourth transistor connected to the collector and the base of the third transistor is connected to the second transistor.
3. The output circuit for a PWM inverter according to claim 2, wherein said current outflow terminal is connected to the emitters of said third and fourth transistors via resistors, respectively, as a current inflow terminal. 4. The current mirror means 1 includes a third transistor of a PNP type, wherein the collector of the third transistor is a first current outflow terminal, and the base of the third transistor is a second transistor. 3. The output circuit for a PWM inverter according to claim 2, wherein a current outflow terminal, and a current inflow terminal connected to the base and the emitter of the third transistor via a resistor, respectively, are used as a current inflow terminal. 5. The current mirror means 1 includes a third transistor of PNP type, a fifth transistor of NPN type and a fifth diode, and a collector of the third transistor is connected to a first current outflow terminal. A connection of the base of the fifth transistor and the cathode of the fifth diode is defined as a second current outflow terminal, and the base of the third transistor, the emitter of the fifth transistor, and the fifth An anode of the fifth transistor connected to the base of the fifth transistor and a cathode of the fifth diode, an emitter connected to the emitter of the third transistor via a resistor,
3. The output circuit for a PWM inverter according to claim 2, wherein the one connected to the collector of said fifth transistor is a current inflow terminal. 6. A first junction type FE of an N-channel type.
T, a second junction FET of a P-channel type, first and second diodes, current control means 1 having a current output terminal and controlling a current flowing out of the current output terminal, a current outflow terminal Current mirror means 2 having a first current inflow terminal, a first current inflow terminal, and a second current inflow terminal. A current control means for controlling a current flowing out of the current output terminal; a DC main power supply; a second DC power supply having a plus terminal connected to a minus terminal of the DC main power supply; The drain of the FET, the cathode of the first diode and the positive terminal of the DC main power supply are connected, and the drain of the second junction FET, the anode of the second diode and the power supply of the DC main power supply are connected. Connecting the negative terminal, connecting the source of the first junction FET, the anode of the first diode, the source of the second junction FET, and the cathode of the second diode, and connecting the gate of the first junction FET to the gate of the first junction FET. A gate of the second junction type FET, a current output terminal of the current control means 1 and a first current inflow terminal of the current mirror means 2 are connected, and a current output terminal of the current control means 4 and the current mirror means 2 are connected. The second current inflow terminal is connected to the negative terminal of the second DC power supply and the current outflow terminal of the current mirror means 2, and a resistor and a resistor are provided between the gate and the source of the first or second junction type FET. A voltage limiting means having a Zener phenomenon for a positive and a negative bidirectional voltage connected in parallel; the current control means 1 and the current mirror means 2
A current flowing from a current output terminal of the current control means 1 as a first current value, and a current flowing from a first current inflow terminal of the current mirror means 2 as a seventh current value.
And a current flowing out of the current output terminal of the current control means 1 as a second current value, and a current flowing out of the first current inflow terminal of the current mirror means 2 as an eighth current value.
And a current flowing out of the current output terminal of the current control means 1 as a fifth current value and a current flowing from the first current inflow terminal of the current mirror means 2 as a third current value.
State and a current flowing from the current output terminal of said current control means 1 to the current value of the sixth first electrodeposition of said current mirror means 2
The fourth current value is a current value flowing from the inflow terminal .
And the current flowing out of the current output terminal of the current control means 1 is a ninth current value, and the current flowing from the first current inflow terminal of the current mirror means 2 is also a ninth current value.
Wherein the first current value is a current value larger than the seventh current value, the second current value is a current value larger than the eighth current value, and the third current value The current value is a current value larger than the fifth current value, the fourth current value is a current value larger than the sixth current value, and the first current value and the seventh current value are different from each other. The difference is larger than the difference between the second current value and the eighth current value, and the difference between the third current value and the fifth current value is the fourth current value and the sixth current value. The difference from the first state can be changed only to the second state and the fifth state, and the second state can be changed only to the third state and the fifth state. The state can be shifted only to the fourth state and the fifth state, and the state can be shifted only to the first state and the fifth state from the fourth state. An output circuit for a PWM inverter configured to be able to shift from the fifth state to at least the first state and the third state. 7. The current mirror means 2 includes sixth and seventh transistors of NPN type,
The collector of the sixth transistor is used as a first current inflow terminal, and the base and collector of the seventh transistor are connected to the base of the sixth transistor to form a second current input terminal.
7. The output circuit for a PWM inverter according to claim 6, wherein said current inflow terminal is connected to the emitters of said sixth and seventh transistors via respective resistors, and said current outflow terminal is used as a current outflow terminal. 8. The current mirror means 2 includes a sixth transistor of NPN type, wherein the collector of the sixth transistor is a first current inflow terminal and the base of the sixth transistor is a second transistor. 7. The output circuit for a PWM inverter according to claim 6, wherein a current inflow terminal, and a current outflow terminal connected to the base and the emitter of the sixth transistor via a resistor, respectively, are used as a current outflow terminal. 9. The current mirror means 2 comprises a sixth transistor of NPN type, an eighth transistor of PNP type and a sixth diode, and a collector of the sixth transistor is connected to a first current inflow terminal. Wherein the base of the eighth transistor and the anode of the sixth diode are connected to form a second current inflow terminal; the base of the sixth transistor, the emitter of the eighth transistor, and the sixth A cathode connected to a diode, a base connected to the base of the eighth transistor and an anode connected to the sixth diode, a base connected to the emitter of the sixth transistor via a resistor,
7. The output circuit for a PWM inverter according to claim 6, wherein a connection of the collector of said eighth transistor is a current outflow terminal. 10. The method according to claim 1, wherein the fifth current value, the sixth current value, the seventh current value, the eighth current value, or the ninth current value is 0.
10. The output circuit for a PWM inverter according to claim 3, claim 4, claim 5, claim 5, claim 6, claim 7, claim 8, or claim 9. 11. A voltage limiting means having a Zener phenomenon for positive and negative bidirectional voltages is a Zener diode having an anode or a cathode connected in common and in series. Claim 3
Or claim 4 or claim 5 or claim 6 or claim 7 or claim 8 or claim 9 or claim 10
An output circuit for a PWM inverter as described in the above.