JPH06121540A - Output circuit for pwm inverter - Google Patents

Abstract

PURPOSE:To provide an inexpensive and excellent output circuit for PWM inverter in which error is suppressed considerably in PWM control of the coil voltage of a motor while suppressing power consumption. CONSTITUTION:A current control means 13 controls collector currents 47 and 48 while making sequential transition among four states thus controlling the terminal voltage 51 of motor winding correctly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power circuit of a PWM inverter for PWM controlling a coil voltage of an electric motor.

[0002]

2. Description of the Related Art In recent years, PWM inverters have rapidly spread and are widely used for motor control.

FIG. 5 is a schematic diagram showing the structure of a general PWM inverter, and shows a three-phase PWM inverter as an example. Generally, in the PWM inverter, the number of output circuits 53 for the PWM inverter differs depending on the number of phases of the motor used, but the basic operation is the same.

The configuration of a general three-phase PWM inverter will be described with reference to FIG. First, the fundamental frequency and the effective voltage value of the three-phase AC voltage waveform supplied to the electric motor 60 are set in the frequency voltage setting means 58. Next, the PWM control circuit 59
Generates a three-phase PWM signal internally based on the information set in the frequency voltage setting means 58 and outputs it as switching command signals 42, 61 and 62. The switching command signals 42, 61 and 62 are applied to the motor winding terminal 5
It is a binary signal for instructing whether 2, 63 and 64 are connected to the positive terminal or the negative terminal of the DC main power supply 14, respectively. The frequency of the switching command signal 42, 61, or 62 is called the PWM carrier frequency, and takes a value 10 times or more the basic frequency of the three-phase AC voltage waveform normally supplied to the electric motor 60. Generally, the fundamental frequency of the three-phase AC voltage waveform supplied to the motor is about 0 Hz to 200 Hz, and the PWM carrier frequency is 2 kHz.
Many are about -20 kHz. The output circuit 53 for the PWM inverter outputs the motor winding terminal 52 or 63 or 6 according to the switching command signal 42 or 61 or 62.
4 is a semiconductor switch circuit for controlling connection of the positive and negative terminals of the DC main power supply 14. In general, most of the DC main power supplies are about DC140V obtained by rectifying and smoothing AC100V and about 280VDC obtained by rectifying and smoothing AC200V.

A conventional PWM inverter output circuit will be described below. FIG. 6 shows the configuration of a conventional PWM inverter output circuit.

In FIG. 6, numeral 65 is a logic inverting means for inverting the positive / negative logic of the switching command signal 42 and outputting an inverted switching signal 80. Reference numerals 66 and 67 denote on-delay circuits, which delay the rising edges of the switching command signal 42 and the inverted switching signal 80 by the on-delay time TD and output the upper arm control signal 81 or the lower arm control signal 82. 68 and 69 are base drive circuits, 68 is for turning on or off the power transistor 70 in response to the upper arm control signal 81, and 69 is for turning on or off the power transistor 71 in response to the lower arm control signal 82. It is configured. That is, when the upper arm control signal 81 becomes the “H” level, the output transistor of the photocoupler 72 is turned on, which turns on the transistor 74, which causes the transistor 7 to turn on.
When 6 is turned off, the power transistor 70 is turned off.
N On the contrary, when the upper arm control signal 81 becomes'L 'level, the output transistor of the photocoupler 72 is turned off,
This also turns off the transistor 74, which turns on the transistor 76, turning off the power transistor 70.

[0007] This base drive circuit is also used in the actual 5
There are those described in Japanese Patent Application Laid-Open No. 7-42589 and Japanese Patent Application Laid-Open No. 59-178980, but basically the same operation as the base drive circuits 68 and 69 shown in FIG.

The operation of the PWM inverter output circuit configured as described above will be described below.

FIG. 7 is a diagram showing internal signals of the output circuit for the PWM inverter shown in FIG. 6. First, when the switching command signal 42 changes from the “L” level to the “H” level, the on-delay circuit 66 turns on-delay. The upper arm control signal 81 is changed from the “L” level to the “H” level with a delay of the time TD. When the upper arm control signal 81 is set to the “H” level, the power transistor 70 is turned on, but there is an operation delay time TX1 of the base drive circuit 68 and the power transistor 70 between them. This operation delay time TX
1 changes depending on the temperature of the power transistor 70 and changes in the current value flowing through the collector, and also changes due to variations in components forming the base drive circuit and power transistors, and changes over time.

Further, the switching command signal 42 is "L".
When the level changes to the'H 'level, the inverted switching signal 80 changes from the'H' level to the'L 'level,
The on-delay circuit 67 sets the lower arm control signal 82 to the'L 'level with almost no time delay. When the lower arm control signal 82 is set to the “L” level, the power transistor 71
Is turned off, but there is an operation delay time TY2 of the base drive circuit 69 and the power transistor 71 in the meantime. This operation delay time TY2 depends on the power transistor 71.
Fluctuates due to changes in the temperature of the
It also changes due to variations and aging of the components that make up the base drive circuit and power transistors.

Next, when the switching command signal 42 changes from the "H" level to the "L" level, the on-delay circuit 66 sets the upper arm control signal 81 to the "L" level with almost no time delay, and the power transistor 70 is turned off. However, there is an operation delay time TY1 of the base drive circuit 68 and the power transistor 70 between them.

Further, the switching command signal 42 is "H".
When the level changes to the'L 'level, the inverted switching signal 80 changes from the'L' level to the'H 'level,
The on-delay circuit 67 changes the lower arm control signal 82 with a delay of the on-delay time TD. When the lower arm control signal 82 is set to the “H” level, the power transistor 71
Is turned on, but there is an operation delay time TX2 of the base drive circuit 69 and the power transistor 71 in the meantime.

When the operation delay time TX1 or the operation delay time TX2 is compared with the operation delay time TY1 or the operation delay time TY2, the operation delay time TY1 or TY2 is generally longer than the operation delay time TX1 or TX2. Tend. The shortest value of the operation delay time TX1 and the operation delay time TX2 considering the worst condition is TXW, and the operation delay time TY1 and the operation delay time T are set.
When the longest value of Y2 in consideration of the worst condition is TYW, the normal on-delay time TD is set to a value obtained by subtracting TXW from TYW with some margin.
Normally, the on-delay time TD uses a bipolar type power transistor and is set to about 10 to 50 microseconds.
Is set to about 2 to 10 microseconds. Accordingly, when the switching command signal 42 changes from the “H” level to the “L” level or when the switching command signal 42 changes from the “L” level to the “H” level, the power transistor 70
And the power transistor 71 are simultaneously turned on to prevent the positive terminal and the negative terminal of the DC main power supply 14 from being short-circuited.

From the above, considering the switching command signal 42 and the state of the motor winding terminal voltage 51,
First, when the switching command signal 42 is fixed at the “L” level, the power transistor 70 is in the OFF state and the power transistor 71 is in the ON state, so the motor winding terminal 52 is connected to the negative terminal of the DC main power supply 14. In addition, when the switching command signal 42 is fixed at the "H" level, the power transistor 7
Since 0 is in the ON state and the power transistor 71 is in the OFF state, the motor winding terminal 52 is connected to the positive terminal of the DC main power supply 14.

[0015]

However, in the above-mentioned conventional configuration, there are cases when the switching command signal 42 changes from the'L 'level to the'H' level or from the'H 'level to the'L' level. Both the time power transistor 70 and the power transistor 71 are turned off, which causes a control error in controlling the voltage of the motor winding terminal 52. This control error has a problem that the torque generated by the electric motor and the rotation speed are changed, and the noise and vibration of the electric motor also increase.

This will be described in more detail. In FIG. 6 and FIG. 7, when the switching command signal 42 changes from the “L” level to the “H” level or when the “H” level changes to the “L” level, the power transistor that has been turned on is first turned off. After that, the power transistor that was off is turned on. Therefore, both the power transistor 70 and the power transistor 71 are off for a certain period of time.
It will be in the state of doing. This state is called a floating state, and this time is called a floating time TF.
Generally, the floating time TF is the on-delay time T
It is often about 1/2 to 2/3 of D.

Generally, the PWM control of an electric motor is essentially such that the electric motor winding terminals are alternately connected to the positive terminal and the negative terminal of the DC main power supply and the ratio of the time of connecting to the positive terminal and the time of connecting to the negative terminal is set. Accordingly, the average voltage of the motor winding terminals is controlled. Therefore, when the voltage of the DC main power supply 14 is constant, the average voltage of the motor winding terminal 52 can be uniquely controlled according to the ratio of the time of the “H” level and the “L” level of the switching command signal 42. Is the ideal.

However, in the conventional output circuit for the PWM inverter, since the floating state exists, the average voltage of the motor winding terminal varies depending on the direction of the current flowing through the motor winding terminal. That is, the motor winding terminal 5
When the current is flowing in the direction in which the current flows from 2 to the PWM inverter output circuit 53, the diode 78 becomes conductive and the motor winding terminal 52 is turned on.
Is connected to the positive terminal of the DC main power supply 14. This state is shown in the motor winding terminal voltage 51A of FIG. On the contrary, when current flows from the PWM inverter output circuit 53 to the electric motor winding terminal 52 in the floating state, the diode 79 conducts and the electric motor winding terminal 52 is connected to the negative terminal of the DC main power supply 14. It will be in the state of being. This state is shown in the motor winding terminal voltage 51B of FIG. In the floating state,
When no current is flowing through the motor winding terminal 52, the voltage at the motor winding terminal 52 is a voltage determined by the induced voltage generated inside the motor 60.

As described above, the switching command signal 42 and the motor winding terminal 52 are present because of the floating state.
The average voltage of is not uniquely determined and causes a control error. Normally, the current flowing through the motor winding terminal 52 is an alternating current, and the direction of the current changes. Therefore, the control error also changes accordingly, and the torque generated or the rotation speed of the motor 60 fluctuates. This problem can be solved by eliminating the floating state and setting the floating time to 0, but in the conventional output circuit for the PWM inverter, the short circuit between the positive terminal and the negative terminal of the DC main power supply 14 occurs, which is actually impossible. Is.

Further, electric noise is generated when the power transistor is turned on or off, and particularly in applications where it is desired to reduce this, the switching speed is slowed by connecting a capacitor between the base and emitter of the power transistor. There are cases. However, this causes the operation delay times TX1, TX2, TY1 and TY2.
The fluctuations in the above will become extremely large, and the floating time will have to be further increased. Therefore, the control error becomes large, and as a result, the switching speed cannot be slowed down so much.

Further, the power transistor 70 and the power transistor 71 shown in FIG.
Although there is a conventional PWM inverter output circuit of the type replaced with, the operation is exactly the same as the PWM inverter output circuit shown in FIG. 6 and has a floating state.

An object of the present invention is to solve the above problems. The floating state is essentially eliminated, the floating time is zero, and the switching command signal and the average voltage of the motor winding terminals are uniquely determined. Accordingly, it is an object of the present invention to provide a PWM inverter output circuit that does not cause a control error and consumes less power at low cost.

[0023]

In order to achieve this object, an output circuit for a PWM inverter according to the present invention comprises an N-channel type first power MOS-FET and a P-channel type second power MOS-FET. And the first, second, third, fourth, fifth and sixth diodes, and PN
A P-type third and fourth transistor, a current output terminal and first and second current input terminals, and
And a current control means capable of independently varying the current value flowing into the second current input terminal in three steps including 0.
A direct current main power supply, a first direct current power supply in which a positive terminal of the direct current main power supply is connected to a negative terminal, and a positive terminal of the direct current main power supply is connected to a negative terminal and has a voltage higher than that of the first direct current power supply. A second DC power supply, a third DC power supply in which a positive terminal is connected to the negative terminal of the DC main power supply, and a positive terminal is connected to a negative terminal of the DC main power supply and a voltage higher than that of the third DC power supply And a drain of the first power MOS-FET and a cathode of the fifth diode are connected to each other, and an anode of the fifth diode, a cathode of the third diode, and the plus of the DC main power source. Connect the terminals to the second power MOS
Connecting the drain of the FET to the anode of the sixth diode, connecting the cathode of the sixth diode to the anode of the fourth diode and the negative terminal of the DC mains power supply,
The source of the first power MOS-FET and the anode of the third diode are connected to the source of the second power MOS-FET and the cathode of the fourth diode, and the first power M
The gate of the OS-FET, the gate of the second power MOS-FET, the anode of the first diode, the cathode of the second diode, the collector of the third transistor, and the first current input terminal of the current control means are connected. Then, the positive terminal of the first DC power supply is connected to the cathode of the first diode, the negative terminal of the third DC power supply is connected to the anode of the second diode, and the positive terminal of the second DC power supply is connected to the first terminal. The emitters of the third and fourth transistors are connected via resistors, respectively, and the base and collector of the fourth transistor, the base of the third transistor and the second current input terminal of the current control means are connected to each other, and the current The current output terminal of the control means is connected to the negative terminal of the fourth DC power supply, and the current control means controls the current flowing into the first current input terminal to 0. The first state in which the current flowing into the second current input terminal is the first current value, and the current flowing into the second current input terminal is 0 when the current flowing into the first current input terminal is 0 The second state in which the second current value is smaller than the first current value, and the current flowing into the second current input terminal is 0, and the current flowing into the first current input terminal is the third current value. And a fourth state in which the current flowing into the second current input terminal is set to 0 and the current flowing into the first current input terminal is set to a fourth current value smaller than the third current value.
Has a state of 1), transitions from the first state to the 4th state in order, transitions to the 4th state, then transitions to the 1st state, and repeatedly transitions from the 1st state to the 4th state. It is configured.

[0024]

With this configuration, it is safe that the first and second power MOS-FETs are not essentially turned on at the same time, and the floating time is essentially 0, so that the control error is very small. And P that consumes less power
An output circuit for the WM inverter can be realized.

[0025]

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is an N-channel type power MOS-FET, 2 is a P-channel type power MOS-FET, 3, 4, 5, 6, 7 and 8 are diodes, and 9 and 10 are PNP type. Transistor,
Reference numerals 11 and 12 are resistors, 13 is current control means, 14 is a DC main power supply, and 15, 16, 17 and 18 are DC power supplies, and the output voltages of the DC power supplies 17 and 18 are determined by the Zener voltages of the Zener diodes 36 and 37. .

The operation of the PWM inverter output circuit configured as described above will be described.

First, the operation of the current control means 13 will be described with reference to FIG. First, NPN type transistor 28
The base signal 43 of the signal causes the switching command signal 42 to be generated through the logic inverting means 19 and 20. This base signal 43 is almost the same as the switching command signal 42,
"L" level is 0V, "H" level is 5V
Shall take the value of. Next, N channel type M
The gate signal 44 of the OS-FET 30 causes the switching command signal 42 to be generated through the logic inverting means 19, 21 and 22 and the signal delay means 26. This gate signal 44
Is a signal obtained by logically inverting the switching command signal 42 and delaying it by a delay time TA.
-The voltage which can sufficiently turn off the FET 30 and the "H" level is a voltage which can sufficiently turn on the MOS-FET 30. The transistor 28 has an emitter follower type circuit configuration, and when the base signal 43 becomes about 0.7 V or more, a collector current 47 determined by the voltage of the base signal 43 and the value of the resistance connected to the emitter flows, and the base signal 43 becomes about 0. The collector current 47 becomes 0 when the voltage is 0.7 V or less. The MOS-FET 30 functions to switch the value of the resistance connected to the emitter of the transistor 28. When the base signal of the transistor 28 is about 0.7 V or more and the MOS-FET 30 is turned on, the collector current 47 of the transistor 28 is increased. It has an effect.

Considering the relationship between the switching command signal 42 and the collector current 47, the collector current 47 is 0 when the switching command signal 42 is at the “L” level.
Then, until the delay time TA elapses after the switching command signal 42 changes to the “H” level, the collector current 4
7 has a relatively large current value, and then has a relatively small current value. When the switching command signal 42 becomes the “L” level, the collector current 47 becomes zero.

Next, the collector current 48 of the transistor 29 is
When the switching command signal 42 is at the “H” level, the collector current 48 is 0, and the collector current 48 is compared until the delay time TB elapses after the switching command signal 42 changes to the “L” level. Becomes a relatively large current value, then a relatively small current value,
When the switching command signal 42 becomes the'H 'level, the collector current 48 becomes zero.

In summary, the first state in which the collector current 48 is 0 and the collector current 47 is the first current value according to the switching command signal 42, and the collector current 48 is 0 and the collector current 47 is the first state. Second state in which the second current value is smaller than the current value of, the third state in which the collector current 47 is 0 and the collector current 48 is in the third current value, and the collector current 47 is 0 and the collector current 47 is 0. It can be seen that there is a fourth state in which the current 48 is the second current value smaller than the third current value, and the fourth state is repeatedly realized in order from the first state. The above is the current control means 1
It is an explanation of the operation of No. 3.

Next, the resistors 11 and 12 and the transistors 9 and 10 have a current mirror configuration with each other, and within a range where the transistor 9 is not saturated, the transistor 9 is
The collector current 49 of the transistor 28 is made proportional to the collector current 47 of the transistor 28. Here, the collector voltage of the transistor 9 rises too much and the transistor 9
Is saturated and becomes an ON state, the proportional relationship between the collector current 47 and the collector current 49 is broken, and the next OFF operation of the transistor 9 is delayed. Therefore, it is necessary to operate the transistor 9 without saturating it. is there. The diode 3 functions to limit the upper limit of the collector voltage of the transistor 9 so that the transistor 9 does not saturate, and at the same time functions to limit the upper limit of the gate voltage of the power MOS-FETs 1 and 2. Diode 4
Serves to limit the lower limit of the collector current 48 of the transistor 29 so that the transistor 29 of the current control means 13 does not saturate, and at the same time, the power MOS-FET 1
And 2 to limit the lower limit of the gate voltage. Here, the upper limit of the gate voltage of the power MOS-FETs 1 and 2 is a voltage at which the power MOS-FET 1 can be sufficiently turned on, and the power MOS-FET 2 is sufficiently O.
It is necessary to set the voltage so that the FF can be performed and not exceed the withstand voltage between the gate and the source of the power MOS-FETs 1 and 2.

The lower limit of the gate voltage of the power MOS-FETs 1 and 2 is a voltage at which the power MOS-FET 2 can be sufficiently turned on, and a voltage at which the power MOS-FET 1 can be sufficiently turned off, and the power MOS-FET.
It is necessary that the withstand voltage between the gate and the source of 1 and 2 is not exceeded.

Generally, N-channel type power MO
The breakdown voltage between the gate and source of the S-FET is ± 20 V to ± 3.
Most of them are about 0V, and the gate voltage threshold for starting conduction between the drain and the source is + based on the source voltage.
Most of them are about 1V to + 5V. On the other hand, the breakdown voltage between the gate and the source of a P-channel type power MOS-FET is often ± 20 V to ± 30 V, and the gate voltage threshold for starting conduction between the drain and the source is based on the source voltage. Most of them are about 1V to -5V.

Here, the relationship between the switching command signal 42 and the gate signal voltage 50 based on the negative terminal of the DC main power supply 14 is shown in FIG. First, when the switching command signal 42 changes from the “L” level to the “H” level, the collector current 49 of the transistor 9 proportional to the collector current 47 of the transistor 28 flows, and the gate signal voltage 50.
Rapidly rises, and the voltage is fixed when the diode 3 becomes conductive. The rising time TR required for the gate signal voltage 50 to rise is determined by the relationship between the electrostatic capacity contained in the power MOS-FETs 1 and 2, the diodes 3 and 4, and the collector current 49. Further, when the diode 3 is conducting, the gate signal voltage 50 does not change significantly, so that the voltage can be maintained even if the collector current 49 is a very small current. Therefore, the signal delay means 26
If the delay time TA is set to be slightly larger than the rising time TR, the rising time TR can be shortened and the power loss of the transistor 28, the transistor 9, the resistor 33 and the like can be minimized.

Next, the switching command signal 42 is "H".
When the level changes to'L 'level, transistor 2
The collector current 48 of 9 flows and the gate signal 50 suddenly drops, and the voltage is fixed when the diode 4 becomes conductive.
The time TF required for the gate signal 50 to fall is
It is determined by the relationship between the electrostatic capacitances contained in the power MOS-FETs 1 and 2, the diodes 3 and 4, and the collector current 48. Further, since the gate signal voltage 50 does not change significantly when the diode 4 is conducting, the collector current 48 can be maintained at that voltage even if it is a very small current. Therefore, the delay time TB of the signal delay means 27
If is set to a value slightly larger than the fall time TF,
The fall time TF can be reduced, and the power loss of the transistor 29, the resistor 35, etc. can be minimized.

Next, the operation of the power MOS-FETs 1 and 2 will be described. Since the gates and the sources of the power MOS-FETs 1 and 2 are commonly connected, the gate voltage 50 is higher than that of the armature winding terminal voltage 51.
When it becomes higher than the gate voltage threshold of -FET1, the power MOS-FET1 starts to flow current from the drain to the source, and conversely, the gate voltage 50 becomes a gate voltage of the power MOS-FET2 rather than the armature winding terminal voltage 51. When it becomes lower than the threshold value, the power MOS-FET 2 starts to flow current from the source to the drain. Therefore, the potential difference between the gate voltage 50 and the armature winding terminal voltage 51 is always within a certain range, and the power MOS-FETs 1 and 2
However, it is essentially impossible that the positive terminal and the negative terminal of the DC main power supply 14 are short-circuited due to the current flowing simultaneously.

Next, the functions of the diodes 5, 6, 7 and 8 will be described. Generally, a simple equivalent circuit of a motor winding is represented as a series connection of a resistance, an inductance, and a voltage source corresponding to an induced voltage. Therefore, unlike the pure resistance load, the direction of the current flowing through the motor winding terminal 52 is not uniquely determined by the voltage applied to the motor winding terminal 52, and the power MOS-FET 1 is ON and the power M
When the OS-FET2 is OFF and the current is flowing from the motor winding terminal 52 to the motor, the state of A and the power MOS
-FET1 is ON and power MOS-FET2 is OF
In the state of F, in which current flows from the motor to the motor winding terminal 52, and when the power MOS-FET 1 is off and the power MOS-FET 2 is on, current flows from the motor to the motor winding terminal 52. C state, power MOS-FET1 is OFF and power MOS-F
There are four states, D state in which ET2 is ON and current flows from the motor winding terminal 52 to the motor. First, in the state A, it can be seen that the current flowing through the motor winding terminal 52 flows through the diode 7 and the power MOS-FET 1. Further, in the state of C, the current flowing through the motor winding terminal 52 is the diode 8 and the power MOS.
-It can be seen that it flows through FET2. Further, regarding the state B and the state D, it can be seen that the current flowing through the motor winding terminal 52 flows through the diode 5 and the diode 6, respectively. Here, the motor winding terminal voltage 5 in the state of B
1 rises due to the current flowing through the motor winding terminal 52,
It can be seen that the diode 5 is fixed when it becomes conductive. Generally, N-channel type power MOS-F
The ET has a parasitic diode that functions to flow a current from the source to the drain, but has a drawback that the reverse recovery time trr of this parasitic diode is very long. Therefore,
A diode 5 having a short reverse recovery time trr is additionally provided, and a diode 7 is attached so that a current does not flow in a parasitic diode of the power MOS-FET 1. If the reverse recovery time trr of the diode 5 is long, switching loss increases. Therefore, it is preferable to select the diode 5 having a short reverse recovery time as much as possible. Similarly, the motor winding terminal voltage 51 in the D state is lowered by the current flowing through the motor winding terminal 52, and is fixed when the diode 6 becomes conductive. In general, a P-channel type power MOS-FET has a parasitic diode that functions to flow a current from the drain to the source, but has a drawback that the reverse recovery time trr of this parasitic diode is very long. Therefore, the diode 6 having a short reverse recovery time trr is additionally provided and the diode 8 is attached so that the current does not flow to the parasitic diode of the power MOS-FET 2.
If the reverse recovery time trr of the diode 6 is long, switching loss increases. Therefore, it is preferable to select the diode 6 having a short reverse recovery time as much as possible.

From the above description, the switching command signal 4
It can be seen that when 2 is set to the'H 'level, the motor winding terminal 52 is connected to the plus terminal of the DC main power supply 14. Further, when the switching command signal 42 is set to the “L” level, the motor winding terminal 52 is connected to the negative terminal of the DC main power supply 14, and when the switching command signal 42 is changed from the “H” level to the “L” level, It can be seen that the floating time is essentially 0 even when the level is changed from the “L” level to the “H” level.

Further, the rising time TR of the gate signal voltage 50 is changed by changing the current values of the collector current 47 of the transistor 28 and the collector current 48 of the transistor 29.
Also, the falling time TF can be freely set within a certain range, and accordingly, the rising time and the falling time of the motor winding terminal voltage 51 can be freely set within a certain range. Normally, the power MOS is set so that the rise time and fall time of the motor winding terminal voltage 51 are reduced.
-FET1 and power MOS-FET2 and the like can reduce power loss, which is preferable, but there is a drawback that electric noise increases. Therefore, it is necessary to increase the rising time and the falling time of the motor winding terminal voltage 51 for the purpose of particularly reducing the electric noise, and the configuration can easily cope with this.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

In FIG. 4, 1 is an N-channel type power MOS-FET, 2 is a P-channel type power MOS-FET, 3 and 4 are diodes, 9 and 10 are PNP type transistors, 11 and 12 are resistors, 13 is a current control means, 14 is a DC main power supply, 15,
Reference numerals 16, 17 and 18 denote DC power supplies, which have the same configuration as that of FIG. The difference from the configuration of FIG. 1 is that the power MOS-FETs 1 and 2 and the diodes 5, 6, 7 and 8 are N-channel type power MOS-FETs 1a and P having parasitic diodes having a short reverse recovery time trr.
This is the point that the channel type power MOS-FET 2a is used.

Recently, the technology of the power MOS-FET has advanced, and only a small part of the parasitic diode whose reverse recovery time trr is very short is manufactured. This reverse recovery time trr
When a power MOS-FET having a short parasitic diode is available, the configuration of FIG. 4 can be adopted, and the number of parts can be reduced.

In the case of constructing a three-phase PWM inverter as shown in FIG. 5, generally, a DC main power source is commonly connected and three PWM inverter output circuits are arranged. In the output circuit for use, the DC power source 1 in the first and second embodiments
It goes without saying that 5, 16, 17 and 18 can be commonly connected.

[0045]

As described above, according to the present invention, the first power MOS-FET of the N-channel type, the second power MOS-FET of the P-channel type, the first, the second, the third, the fourth. , 5th and 6th diodes, PNP type 3rd and 4th transistors, and current output terminals and first and second current input terminals, which flow into the first and second current input terminals. A current control means capable of independently varying a current value in three steps including 0, a DC main power supply, a first DC power supply in which a minus terminal is connected to a plus terminal of the DC main power supply, and a DC main power supply A second DC power supply having a positive terminal connected to a negative terminal and having a voltage higher than that of the first DC power supply; a third DC power supply having a negative terminal of the DC main power supply connected to a positive terminal; Power supply A fourth direct current power supply having a Connect the positive terminal eggplant terminal said third voltage higher than the DC power source, the drain and the fifth of the first power MOS-FET
The cathode of the diode, the anode of the fifth diode, the cathode of the third diode and the positive terminal of the DC main power source are connected, and the second power MOS-FET is connected.
Of the third diode is connected to the anode of the sixth diode, the cathode of the sixth diode is connected to the anode of the fourth diode and the negative terminal of the DC main power supply, and the source of the first power MOS-FET is connected to the third terminal. Connecting the anode of the diode, the source of the second power MOS-FET, and the cathode of the fourth diode to the first power MOS-F.
The gate of ET, the gate of the second power MOS-FET, the anode of the first diode, the cathode of the second diode, the collector of the third transistor and the first current input terminal of the current control means are connected, The positive terminal of the first DC power supply and the cathode of the first diode are connected, and the third
The negative terminal of the direct current power supply is connected to the anode of the second diode, the positive terminal of the second direct current power supply is connected to the emitters of the third and fourth transistors through resistors, and the base of the fourth transistor is connected. And collector and third
The base of the transistor is connected to the second current input terminal of the current control means, and the current output terminal of the current control means is connected to the negative terminal of the fourth DC power supply, the current control means comprising: , A first state in which the current flowing into the first current input terminal is 0 and the current flowing into the second current input terminal is the first current value, and the current flowing into the first current input terminal is 0 And a second state in which the current flowing into the second current input terminal is a second current value smaller than the first current value, and the current flowing into the second current input terminal is 0.
And a third state in which the current flowing into the first current input terminal is the third current value, and the current flowing into the second current input terminal is 0, and the current flowing into the first current input terminal is It has a fourth state in which the fourth current value is smaller than the third current value, and transitions from the first state to the fourth state in order.
After the above state, the state shifts from the first state to the fourth state.
By adopting a configuration in which the states of (1) and (2) are sequentially repeated, there is essentially no floating state, and the switching command signal and the average voltage of the motor winding terminal are uniquely determined when the floating time is 0, and the control error becomes extremely large. An excellent PWM inverter output circuit that is small and consumes less power can be provided at low cost. Further, it is possible to provide an excellent output circuit for a PWM inverter, which generates very little electrical noise, at a low cost, if necessary.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a PWM inverter output circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing the operation of the current control means of the PWM inverter output circuit in the first embodiment of the present invention.

FIG. 3 is a diagram showing the operation of the PWM inverter output circuit according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram of a PWM inverter output circuit according to a second embodiment of the present invention.

FIG. 5 is a schematic diagram showing a configuration of a general PWM inverter.

FIG. 6 is a configuration diagram of a conventional PWM inverter output circuit.

FIG. 7 is a diagram showing an operation of a conventional PWM inverter output circuit.

[Explanation of symbols]

1,1a N-channel type power MOS-FET 2,2a P-channel type power MOS-FET 3,4,5,6,7,8,78,79 diode 9,10 PNP type transistor 11,12,32 , 33, 34, 35, 40, 41, 8
3,84,85,86,87,88,89,90,9
1,92 Resistance 13 Current Control Means 14 DC Main Power Supply 15, 16, 17, 18, 93, 94 DC Power Supply 19, 20, 21, 22, 23, 24, 25, 65 Logic Inversion Means 26, 27 Signal Delay Means 28 , 29, 74, 75, 76, 77 NPN type transistor 30, 31 N channel type MOS-FET 36, 37 Zener diode 38, 39 Capacitor 42, 61, 62 Switching command signal 52, 63, 64 Motor winding terminal 53 PWM output circuit for inverter 54 First state 55 Second state 56 Third state 57 Fourth state 58 Frequency voltage setting means 59 PWM control circuit 60 Electric motor 66, 67 On-delay circuit 68, 69 Base drive circuit 70 , 71 Power transistor 72, 73 Photocoupler

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[Procedure amendment]

[Submission date] October 18, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

From the above, considering the switching command signal 42 and the state of the motor winding terminal voltage 51,
First, when the switching command signal 42 is fixed at the “L” level, the power transistor 70 is in the OFF state and the power transistor 71 is in the ON state, so the motor winding terminal 52 is connected to the negative terminal of the DC main power supply 14. In addition, when the switching command signal 42 is fixed at the "H" level, the power transistor 7
Since 0 is ON and the power transistor 71 is OFF, the motor winding terminal 52 is connected to the positive terminal of the DC main power supply 14.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0023

[Correction method] Change

[Correction content]

[0023]

In order to achieve this object, an output circuit for a PWM inverter according to the present invention comprises an N-channel type first power MOS-FET and a P-channel type second power MOS-FET. And the first, second, third, fourth, fifth and sixth diodes, and PN
A P-type third and fourth transistor, a current output terminal and first and second current input terminals, and
And a current control means capable of independently varying the current value flowing into the second current input terminal in three steps including 0.
A direct current main power supply, a first direct current power supply in which a positive terminal of the direct current main power supply is connected to a negative terminal, and a positive terminal of the direct current main power supply is connected to a negative terminal and has a voltage higher than that of the first direct current power supply. A second DC power supply, a third DC power supply in which a positive terminal is connected to the negative terminal of the DC main power supply, and a positive terminal is connected to a negative terminal of the DC main power supply and a voltage higher than that of the third DC power supply And a drain of the first power MOS-FET and a cathode of the fifth diode are connected to each other, and an anode of the fifth diode, a cathode of the third diode, and the plus of the DC main power source. Connect the terminals to the second power MOS
Connecting the drain of the FET to the anode of the sixth diode, connecting the cathode of the sixth diode to the anode of the fourth diode and the negative terminal of the DC mains power supply,
The source of the first power MOS-FET and the anode of the third diode are connected to the source of the second power MOS-FET and the cathode of the fourth diode, and the first power M
The gate of the OS-FET, the gate of the second power MOS-FET, the anode of the first diode, the cathode of the second diode, the collector of the third transistor, and the first current input terminal of the current control means are connected. Then, the positive terminal of the first DC power supply is connected to the cathode of the first diode, the negative terminal of the third DC power supply is connected to the anode of the second diode, and the positive terminal of the second DC power supply is connected to the first terminal. The emitters of the third and fourth transistors are connected via resistors, respectively, and the base and collector of the fourth transistor, the base of the third transistor and the second current input terminal of the current control means are connected to each other, and the current The current output terminal of the control means is connected to the negative terminal of the fourth DC power supply, and the current control means controls the current flowing into the first current input terminal to 0. The first state in which the current flowing into the second current input terminal is the first current value, and the current flowing into the second current input terminal is 0 when the current flowing into the first current input terminal is 0 The second state in which the second current value is smaller than the first current value, and the current flowing into the second current input terminal is 0, and the current flowing into the first current input terminal is the third current value. And a fourth state in which the current flowing into the second current input terminal is set to 0 and the current flowing into the first current input terminal is set to a fourth current value smaller than the third current value.
Has a state of 1), transitions from the first state to the 4th state in order, transitions to the 4th state, then transitions to the 1st state, and repeatedly transitions from the 1st state to the 4th state. It is configured. Alternatively, in order to achieve the above object, the PWM of the present invention
The output circuit for the inverter is the first N-channel type.
Power MOS-FET and P-channel type second
Power MOS-FET and first and second diodes
And a PNP type third and fourth transistor,
Has a current output terminal and first and second current input terminals,
The value of the current flowing into the first and second current input terminals is
Current control that can be independently changed in 3 stages including 0
Means, the DC main power supply, and the positive terminal of the DC main power supply
The first DC power source with the negative terminal connected, and the DC main
Connect the negative terminal to the positive terminal of the power supply and connect the first
A second DC power supply having a voltage higher than that of the current supply, and
3rd with positive terminal connected to negative terminal of DC main power supply
Of the DC power supply and the negative terminal of the DC main power supply
Connect the terminals and have a higher voltage than the third DC power supply
A first power MOS-FET provided with a fourth DC power supply
Connect the positive terminal of the DC main power supply to the drain of
2 power MOS-FET drain and the DC main power source
Connect the negative terminal of the first power MOS-FET
Source of the second power MOS-FET is connected
Then, the gate of the first power MOS-FET and the second power
-MOS-FET gate and first diode annotator
And the cathode of the second diode and the third transistor
And the first current input terminal of the current control means
Connect the positive terminal of the first DC power supply to the first diode.
The negative terminal of the third DC power supply by connecting the cathode of
And the anode of the second diode are connected to
Source positive terminal and third and fourth transistor emitters
Connect each via a resistor to connect the 4th transistor
The base and collector of the third transistor and the base of the third transistor
Connecting a second current input terminal of the current control means,
The current output terminal of the current control means is a minor of the fourth DC power supply.
The current control means is connected to the first terminal.
The current flowing into the current input terminal of 1 is set to 0 and the second current input is
First state in which the current flowing into the force terminal is the first current value
And setting the current flowing into the first current input terminal to 0,
The current flowing into the current input terminal is lower than the first current value.
The second state with a small second current value and the second current input
The current flowing into the input terminal is set to 0 and the current is applied to the first current input terminal.
A third state in which the input current is a third current value, and a second state
The current flowing into the current input terminal is set to 0 and the first current input terminal
The current flowing into the child is set to a fourth value smaller than the third current value.
Has a fourth state with a current value of
Moves to the 4th state, then moves to the 1st state after the 4th state
And repeat the sequence from the first state to the fourth state in sequence.
It is configured to go.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0029

[Correction method] Change

[Correction content]

Considering the relationship between the switching command signal 42 and the collector current 47, the collector current 47 is 0 when the switching command signal 42 is at the “L” level.
Then, until the delay time TA elapses after the switching command signal 42 changes to the “H” level, the collector current 4
7 has a relatively large current value, and then has a relatively small current value. When the switching command signal 42 becomes the'L 'level, the collector current 47 becomes zero.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction content]

In summary, the first state in which the collector current 48 is 0 and the collector current 47 is the first current value according to the switching command signal 42, and the collector current 48 is 0 and the collector current 47 is the first state. Second state in which the second current value is smaller than the current value of, the third state in which the collector current 47 is 0 and the collector current 48 is in the third current value, and the collector current 47 is 0 and the collector current 47 is 0. It can be seen that there is a fourth state in which the current 48 is a fourth current value smaller than the third current value, and the fourth state is repeatedly realized in order from the first state. The above is the current control means 1
It is an explanation of the operation of No. 3.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0032

[Correction method] Change

[Correction content]

Next, the resistors 11 and 12 and the transistors 9 and 10 have a current mirror configuration with each other, and within a range where the transistor 9 is not saturated, the transistor 9 is
The collector current 49 of the transistor 28 is made proportional to the collector current 47 of the transistor 28. Here, the collector voltage of the transistor 9 rises too much and the transistor 9
Is saturated and becomes an ON state, the proportional relationship between the collector current 47 and the collector current 49 is broken, and the next OFF operation of the transistor 9 is delayed. Therefore, it is necessary to operate the transistor 9 without saturating it. is there. The diode 3 functions to limit the upper limit of the collector voltage of the transistor 9 so that the transistor 9 does not saturate, and at the same time functions to limit the upper limit of the gate voltage of the power MOS-FETs 1 and 2. Diode 4
Serves to limit the lower limit of the collector voltage of the transistor 29 of the voltage control means 13 so as not to saturate the transistor 29 and at the same time limits the lower limit of the gate voltage of the power MOS-FETs 1 and 2. . Here, the upper limit of the gate voltage of the power MOS-FETs 1 and 2 is a voltage at which the power MOS-FET 1 can be sufficiently turned on, a voltage at which the power MOS-FET 2 can be sufficiently turned off, and the power MOS-FETs 1 and 2 It is necessary to use a value that does not exceed the breakdown voltage between the gate and the source of

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

Next, the switching command signal 42 is "H".
When the level changes to'L 'level, transistor 2
The collector current 48 of 9 flows and the gate signal voltage 50 suddenly drops, and the voltage is fixed when the diode 4 becomes conductive. The time TF required for the gate signal voltage 50 to fall is determined by the relationship between the collector current 48 and the capacitance included in the power MOS-FETs 1 and 2, the diodes 3 and 4, and the like. Further, since the gate signal voltage 50 does not change significantly when the diode 4 is conducting, the collector current 48 can be maintained at that voltage even if it is a very small current. Therefore, if the delay time TB of the signal delay means 27 is set to be slightly larger than the fall time TF, the fall time TF can be reduced and the power loss of the transistor 29, the resistor 35, etc. can be minimized.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0037

[Correction method] Change

[Correction content]

Next, the operation of the power MOS-FETs 1 and 2 will be described. Since the power MOS-FET1 and second gate and source are commonly connected, respectively, the gate
The signal voltage 50 is more power M than the motor winding terminal voltage 51.
When the gate voltage of the OS-FET1 becomes higher than the threshold voltage, the power MOS-FET1 starts to flow a current from the drain to the source, and conversely, the gate signal voltage 50 is higher than the motor winding terminal voltage 51 than the gate voltage of the power MOS-FET2. When it becomes lower than the threshold value, the power MOS-FET 2 starts to flow current from the source to the drain. Therefore, the potential difference between the gate signal voltage 50 and the motor winding terminal voltage 51 is always within a certain range, and the power MOS-F
It is essentially impossible for ET1 and ET2 to simultaneously conduct current and short-circuit the positive and negative terminals of DC main power supply 14.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0042

[Correction method] Change

[Correction content]

[0042] In Fig. 4, 3 and 4 are diodes,
Reference numerals 9 and 10 are PNP type transistors, 11 and 12 are resistors, 13 is a current control means, 14 is a DC main power supply, 15, 16, 17 and 18 are DC power supplies, and the above is the same as the configuration of FIG. is there. The difference from the configuration of FIG. 1 is that the power MOS-FETs 1 and 2 and the diode 5,
6, 7 and 8 are N-channel type power MOS-FE having a parasitic diode having a short reverse recovery time trr.
T1a and P channel type power MOS-FET2
This is a point.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Name of item to be corrected] 0045

[Correction method] Change

[Correction content]

[0045]

As described above, according to the present invention, the first power MOS-FET of the N-channel type, the second power MOS-FET of the P-channel type, the first, the second, the third, the fourth. , 5th and 6th diodes, PNP type 3rd and 4th transistors, and current output terminals and first and second current input terminals, which flow into the first and second current input terminals. A current control means capable of independently varying a current value in three steps including 0, a DC main power supply, a first DC power supply in which a minus terminal is connected to a plus terminal of the DC main power supply, and a DC main power supply A second DC power supply having a positive terminal connected to a negative terminal and having a voltage higher than that of the first DC power supply; a third DC power supply having a negative terminal of the DC main power supply connected to a positive terminal; Power supply A fourth direct current power supply having a Connect the positive terminal eggplant terminal said third voltage higher than the DC power source, the drain and the fifth of the first power MOS-FET
The cathode of the diode, the anode of the fifth diode, the cathode of the third diode and the positive terminal of the DC main power source are connected, and the second power MOS-FET is connected.
Of the third diode is connected to the anode of the sixth diode, the cathode of the sixth diode is connected to the anode of the fourth diode and the negative terminal of the DC main power supply, and the source of the first power MOS-FET is connected to the third terminal. Connecting the anode of the diode, the source of the second power MOS-FET, and the cathode of the fourth diode to the first power MOS-F.
The gate of ET, the gate of the second power MOS-FET, the anode of the first diode, the cathode of the second diode, the collector of the third transistor and the first current input terminal of the current control means are connected, The positive terminal of the first DC power supply and the cathode of the first diode are connected, and the third
The negative terminal of the direct current power supply is connected to the anode of the second diode, the positive terminal of the second direct current power supply is connected to the emitters of the third and fourth transistors through resistors, and the base of the fourth transistor is connected. And collector and third
The base of the transistor is connected to the second current input terminal of the current control means, and the current output terminal of the current control means is connected to the negative terminal of the fourth DC power supply, the current control means comprising: , A first state in which the current flowing into the first current input terminal is 0 and the current flowing into the second current input terminal is the first current value, and the current flowing into the first current input terminal is 0 And a second state in which the current flowing into the second current input terminal is a second current value smaller than the first current value, and the current flowing into the second current input terminal is 0.
And a third state in which the current flowing into the first current input terminal is the third current value, and the current flowing into the second current input terminal is 0, and the current flowing into the first current input terminal is It has a fourth state in which the fourth current value is smaller than the third current value, and transitions from the first state to the fourth state in order.
After the above state, the state shifts from the first state to the fourth state.
Or the N-channel type first power MOS.
-FET and P channel type second power MOS
-FET, first and second diodes, PNP tie
The third and fourth transistors of the amplifier and the current output terminal
A first and a second current input terminal, and
Three levels including 0 for the current value flowing into the second current input terminal
Current control means that can be changed independently, and DC main
Connect the power supply and the negative terminal to the positive terminal of the DC main power supply.
Connected first DC power supply and positive end of the DC main power supply
The negative terminal is connected to the child and the voltage is higher than the first DC power supply.
A second direct current power supply having a high voltage and a master of the direct current main power supply.
A third DC power supply with a positive terminal connected to the INUS terminal,
Before connecting the positive terminal to the negative terminal of the DC main power
Note Fourth DC power source having a higher voltage than the third DC power source
The source and the drain of the first power MOS-FET and the front
Connect the positive terminal of the DC mains power supply to the second power MO
The drain of the S-FET and the negative terminal of the DC main power supply
To connect the source of the first power MOS-FET and the second
The source of the power MOS-FET of
-MOS-FET gate and second power MOS-FE
The gate of T, the anode of the first diode and the second die
In front of the cathode of the ode and the collector of the third transistor
The first current input terminal of the current control means is connected to
The positive terminal of the DC power supply and the cathode of the first diode
Connect the negative terminal of the third DC power supply and the second dio
The positive terminal of the second DC power supply by connecting the anode of the battery
And the emitters of the third and fourth transistors respectively
It is connected through a resistor and is connected to the base of the fourth transistor.
And the base of the third transistor and the current control device
The second current input terminal of the stage is connected,
Connect the current output terminal to the negative terminal of the fourth DC power supply.
And the current control means has a first current input terminal.
The current flowing into the child is set to 0 and flows into the second current input terminal.
And a first state in which the current is a first current value, and a first current
The current flowing into the input terminal is set to 0 and the second current input terminal is
The inflowing current is set to a second electric current smaller than the first electric current value.
The second state, which is the flow value, and the current flowing into the second current input terminal.
The current that flows into the first current input terminal is
In the third state with the current value of 3 and the second current input terminal
The current flowing into the first current input terminal is set to 0.
Let the flow be a fourth current value smaller than the third current value
Has a fourth state, from the first state to the fourth state in order
After transitioning to the fourth state and then transitioning to the first state, the first state
The state is changed from the fourth state to the fourth state in sequence.
As a result, there is essentially no floating state and the floating time is 0, and the switching command signal and the average voltage of the motor winding terminals are uniquely determined, so that the control error is extremely small and the excellent PWM inverter with low power consumption is also provided. The output circuit for use can be provided at low cost. Further, it is possible to provide an excellent output circuit for a PWM inverter, which generates very little electrical noise, at a low cost, if necessary.

Claims (2)

[Claims] 1. An N-channel type first power MOS.
-FET and P channel type second power MOS
-FET and first, second, third, fourth, fifth and sixth
, A PNP-type third and fourth transistor, a current output terminal and first and second current input terminals, and sets the current value flowing into the first and second current input terminals to 0. Including three current control means that can be independently varied, a DC main power supply, a first DC power supply in which a minus terminal is connected to the plus terminal of the DC main power supply, and a minus terminal to the plus terminal of the DC main power supply. A second DC power supply having a voltage higher than that of the first DC power supply, a third DC power supply having a positive terminal connected to the negative terminal of the DC main power supply, and a negative terminal of the DC main power supply. A fourth DC power source having a voltage higher than that of the third DC power source is connected to the positive terminal, and the drain of the first power MOS-FET and the cathode of the fifth diode are connected to each other. The anode of the diode, the cathode of the third diode and the positive terminal of the DC main power supply are connected, the drain of the second power MOS-FET and the anode of the sixth diode are connected, and the cathode of the sixth diode and the The anode of the diode No. 4 and the negative terminal of the DC main power supply are connected to each other, and the first power MO
The source of the S-FET, the anode of the third diode, the source of the second power MOS-FET, and the cathode of the fourth diode are connected, and the gate of the first power MOS-FET and the second power MOS-FET are connected. Of the first diode, the anode of the first diode, the cathode of the second diode, the collector of the third transistor, and the first of the current control means.
Connected to the positive terminal of the first DC power supply and the cathode of the first diode, and the negative terminal of the third DC power supply to the anode of the second diode. The positive terminal of the power source and the emitters of the third and fourth transistors are connected via resistors,
The base and collector of the fourth transistor, the base of the third transistor and the second current input terminal of the current control means are connected, and the current output terminal of the current control means is connected to the negative terminal of the fourth DC power supply. A first state in which the current flowing into the first current input terminal is 0 and the current flowing into the second current input terminal is the first current value; A second current input terminal having a first current input terminal of 0 and a second current input terminal having a second current value smaller than the first current value;
And a third state in which a current flowing into the second current input terminal is 0 and a current flowing into the first current input terminal is a third current value, and a current flowing into the second current input terminal There is a fourth state in which the current is 0 and the current flowing into the first current input terminal is a fourth current value smaller than the third current value. From the first state to the fourth state in order. An output circuit for a PWM inverter having a configuration in which a transition is made from the first state to the fourth state after the transition from the fourth state to the first state. 2. An N-channel type first power MOS.
-FET and P channel type second power MOS
A FET, first and second diodes, PNP type third and fourth transistors, a current output terminal and first and second current input terminals, and the first and second current input terminals Current control means capable of independently varying the value of the current flowing into each of the three stages including 0, a DC main power supply, a first DC power supply in which the minus terminal is connected to the positive terminal of this DC main power supply, and the DC A second DC power supply having a negative terminal connected to the positive terminal of the main power supply and having a higher voltage than the first DC power supply; and a third DC power supply having a negative terminal connected to the negative terminal of the DC main power supply,
A positive terminal is connected to the negative terminal of the DC main power source, and a fourth DC power source having a higher voltage than the third DC power source is provided, and the drain of the first power MOS-FET and the positive terminal of the DC main power source. To connect the second power MOS-FET
Connect the drain of and the negative terminal of the DC main power supply,
Source of first power MOS-FET and second power M
The source of the OS-FET is connected and the first power MOS-
The gate of the FET, the gate of the second power MOS-FET, the anode of the first diode, the cathode of the second diode, the collector of the third transistor, and the first current input terminal of the current control means are connected, The positive terminal of the first DC power supply is connected to the cathode of the first diode, the negative terminal of the third DC power supply is connected to the anode of the second diode, and the positive terminal of the second DC power supply is connected to the third terminal. The emitter of the fourth transistor is connected via a resistor, respectively, the base and collector of the fourth transistor, the base of the third transistor and the second current input terminal of the current control means are connected, and the current control means is connected. The current output terminal is connected to the negative terminal of the fourth DC power supply, and the current control means sets the current flowing into the first current input terminal to 0. The first state in which the current flowing into the second current input terminal is the first current value, and the current flowing into the second current input terminal is 0 when the current flowing into the first current input terminal is 0. Second current value smaller than the current value of
And a third state in which a current flowing into the second current input terminal is 0 and a current flowing into the first current input terminal is a third current value, and a current flowing into the second current input terminal There is a fourth state in which the current is 0 and the current flowing into the first current input terminal is a fourth current value smaller than the third current value. From the first state to the fourth state in order. An output circuit for a PWM inverter having a configuration in which a transition is made from the first state to the fourth state after the transition from the fourth state to the first state.