JPH07297238A - Flux transfer method - Google Patents

Flux transfer method

Info

Publication number
JPH07297238A
JPH07297238A JP8700494A JP8700494A JPH07297238A JP H07297238 A JPH07297238 A JP H07297238A JP 8700494 A JP8700494 A JP 8700494A JP 8700494 A JP8700494 A JP 8700494A JP H07297238 A JPH07297238 A JP H07297238A
Authority
JP
Japan
Prior art keywords
flux
transfer
pads
pad
transfer pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP8700494A
Other languages
Japanese (ja)
Inventor
Tetsuji Nitta
哲二 新田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8700494A priority Critical patent/JPH07297238A/en
Publication of JPH07297238A publication Critical patent/JPH07297238A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3489Composition of fluxes; Methods of application thereof; Other methods of activating the contact surfaces

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain a flux transfer method for practical mass production, in relation to the transfer of fluxes to the pads whose patterns are formed at fine pitches on a board. CONSTITUTION:Transfer pin arrays 8, 9 for transferring fluxes to a plurality of pads are divided into two groups and are provided on a transfer unit 4. An aligning table 3 whereon the transfer unit 4 is mounted is moved, and thereby, the flux is stuck on the end parts of the transfer pins of the two groups independently of each other on a flux table 5, and thereafter, the transfer unit 4 is so moved that the fluxes are transferred to the pads.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は被処理基板上にパターン
形成してある多数のパッド上に、はんだバンプ形成のた
めのフラックスを転写する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for transferring a flux for forming solder bumps onto a large number of pads patterned on a substrate to be processed.

【0002】大量の情報を迅速に処理する必要から情報
処理装置は大容量化が行なわれており、この装置の主体
を構成する半導体装置は単位素子の小型化による大容量
化が行なわれてLSIやVLSIが実用化されている。
The information processing apparatus has been increased in capacity because of the need to process a large amount of information quickly, and the semiconductor device, which is the main component of this apparatus, has been increased in capacity by reducing the size of a unit element. And VLSI have been put to practical use.

【0003】こゝで、これらの半導体装置を含む電子回
路の装着法としてはセラミック多層回路基板上に多数の
パッドを設け、このパッドにフリップチップタイプの複
数の半導体装置を装着し、ビア(Via)により基板内にパ
ターン形成してある電子回路に回路接続し、これを取り
替え単位として情報処理装置を構成する方法が採られて
いる。
As a method of mounting an electronic circuit including these semiconductor devices, a large number of pads are provided on a ceramic multilayer circuit board, a plurality of flip chip type semiconductor devices are mounted on the pads, and vias (Via ), A circuit is connected to an electronic circuit formed in a pattern on the substrate, and the information processing apparatus is configured by using this as a replacement unit.

【0004】[0004]

【従来の技術】半導体集積回路の大容量化は先に記した
ように基板の大型化よりも単位素子の小型化により行な
われていることから、多層回路基板上に半導体装置の搭
載のためにパターン形成してあるパッドの大きさやピッ
チは益々微小化している。
2. Description of the Related Art Since the capacity of a semiconductor integrated circuit has been increased by miniaturizing a unit element rather than increasing the size of a board as described above, it is necessary to mount a semiconductor device on a multilayer circuit board. The size and pitch of the patterned pads are becoming smaller and smaller.

【0005】例えば、今までは約300 μm 角のパッドが
450 μm ピッチでマトリックス状に配列しており、この
各々のパッドはビアにより多層回路に接続されている。
こゝで、パッドは多層回路基板を形成する導体線路の構
成材料により異なるが、導体線路が銅(Cu)よりなる場合
は厚さが約1000Åのニッケル(Ni)と金(Au)をスパッタ法
などにより積層して形成した後、写真蝕刻技術( ホトリ
ソグラフィ) を用いて選択エッチングし、パターン形成
する手法が採られている。
For example, until now, a pad of about 300 μm square has been used.
The pads are arranged in a matrix with a pitch of 450 μm, and each pad is connected to a multilayer circuit by a via.
Here, the pad differs depending on the constituent material of the conductor line that forms the multilayer circuit board, but when the conductor line is made of copper (Cu), the thickness of about 1000Å nickel (Ni) and gold (Au) are sputtered. A method of forming a pattern by performing selective etching using a photo-etching technique (photolithography) after stacking and forming by a method such as photolithography is adopted.

【0006】そして、このようにして形成したパッドの
上にフリップチップタイプの集積回路を装着するには、
先ず、フラックスをパッド上に塗布し、この上にはんだ
バンプを形成した後、集積回路よりなる半導体チップを
位置決めし、トンネル炉などを用いて加熱溶融すること
により装着が行なわれている。
To mount the flip chip type integrated circuit on the pad thus formed,
First, flux is applied to a pad, solder bumps are formed on the pad, a semiconductor chip made of an integrated circuit is positioned, and heating and melting is performed using a tunnel furnace or the like to mount the semiconductor chip.

【0007】こゝで、基板上にパターン形成してあるパ
ッドにフラックスを塗布するのに、従来は図3(A)に
示すように所定の大きさの転写ピン1が所定の数だけマ
トリックス状に配列している転写ピン列2を同図(B)
に示すように転写ピン列2を位置決めテーブル3にある
転写ユニット4に装着し、先ず、位置決めテーブル3を
フラックステーブル5の位置まで移動させた後に降下さ
せて、スキージで一定の厚さに塗布さているフラックス
を転写ピン列2で捺印して転写ピン1に転写し、次に、
同図(C)に示すように位置決めテーブル3を被処理基
板6の位置にまで移動させた後、転写ユニット4を降下
させ、転写ピン列2でフラックスをパッド上に転写する
ことで塗布が行なわれていた。
Here, in order to apply the flux to the pad formed on the substrate by patterning, conventionally, as shown in FIG. 3A, a predetermined number of transfer pins 1 of a predetermined size are arranged in a matrix form. The transfer pin row 2 arranged in the same figure is shown in FIG.
As shown in FIG. 5, the transfer pin row 2 is mounted on the transfer unit 4 on the positioning table 3. First, the positioning table 3 is moved to the position of the flux table 5 and then lowered, and applied with a squeegee to a constant thickness. Mark the existing flux with the transfer pin row 2 and transfer it to the transfer pin 1. Then,
As shown in FIG. 3C, after moving the positioning table 3 to the position of the substrate 6 to be processed, the transfer unit 4 is lowered and the flux is transferred onto the pad by the transfer pin row 2 to perform the application. It was

【0008】こゝで、転写ピン1の作り方としては少な
くとも400 μm の高さを必要とすることから、図3
(A)に示すように、上下方向と左右方向から切削を行
なって450 μm ピッチでマトリックス状に形成されてい
る。
Since the transfer pin 1 needs to have a height of at least 400 μm, the transfer pin 1 shown in FIG.
As shown in (A), cutting is performed in the vertical and horizontal directions to form a matrix with a pitch of 450 μm.

【0009】然し、半導体集積回路の小型大容量化が進
んでパッドのピッチが狭まると共に、マトリックス形状
よりずれた位置にもパッドを設ける必要性が生じてきた
が、パッドのピッチが400 μm 以下に狭まると切削加工
法によってはこれにフラックスを塗布する転写ピンは形
成できないと云う問題がある。
However, as the semiconductor integrated circuits have become smaller and larger and the pitch of the pads has become narrower, it has become necessary to provide the pads at positions deviated from the matrix shape, but the pitch of the pads becomes 400 μm or less. If it becomes narrow, there is a problem that the transfer pin which applies flux to it cannot be formed depending on the cutting method.

【0010】[0010]

【発明が解決しようとする課題】半導体集積回路は単位
素子の小型化による大容量化が進んでフリップチップタ
イプのLSIやVLSIが実用化されているが、これに
使用されているはんだバンプのピッチは更に狭まり、ま
た、マトリックスよりずれた位置に対してもパッドをパ
ターン形成する必要が生じてきた。
In a semiconductor integrated circuit, flip-chip type LSIs and VLSIs have been put into practical use due to the increase in capacity due to the miniaturization of unit elements. The pitch of solder bumps used in these Has become narrower, and it has become necessary to pattern pads at positions deviated from the matrix.

【0011】そこで、かゝる集積回路を多層回路基板上
にパターン形成してあるパッドに位置合わせして装着す
るには、予め、パッド上にフラックスを塗布しておき、
濡れ性を向上させる必要があるが、そのためには転写ピ
ン列のピッチが狭く加工ができないと云う問題がある。
Therefore, in order to align and mount such an integrated circuit on a pad formed by patterning on a multilayer circuit board, flux is applied to the pad in advance,
Although it is necessary to improve the wettability, there is a problem that the pitch of the transfer pin row is narrow and it cannot be processed.

【0012】[0012]

【課題を解決するための手段】上記の課題は多層回路基
板上にパターン形成してある多数のパッドに同時にフラ
ックスを転写する転写ピン列を、二群に別けて転写ユニ
ットに設置し、それぞれ群ごとにフラックステーブルに
おいて転写ピンの先端にフラックスを付着させた後、移
動させてフラックスをパッド上に転写することを特徴と
してフラックスの転写方法を構成することにより解決す
ることができる。
SUMMARY OF THE INVENTION The above problem is that transfer pin rows for simultaneously transferring flux to a large number of pads patterned on a multilayer circuit board are installed in a transfer unit separately in two groups. This can be solved by configuring the flux transfer method, which is characterized in that the flux is attached to the tips of the transfer pins in each flux table and then moved to transfer the flux onto the pad.

【0013】[0013]

【作用】本発明は転写ピン列を二分割して充分に余裕を
もって切削加工することで問題を解決するものである。
The present invention solves the problem by dividing the transfer pin array into two parts and cutting them with a sufficient margin.

【0014】現在使用されている集積回路の端子数は膨
大であり、例えばLSIの場合、直径が400 μm のはん
だバンプ640 個が450 μm ピッチでマトリックス状に配
列して形成されており、集積回路がVLSI→ULSI
と大容量化されるに従ってはんだバンプの数は増え、一
方、ピッチは縮小してゆく。
The number of terminals of an integrated circuit which is currently used is enormous. For example, in the case of an LSI, 640 solder bumps having a diameter of 400 μm are arranged in a matrix at a pitch of 450 μm. Is VLSI → ULSI
As the capacity increases, the number of solder bumps increases, while the pitch decreases.

【0015】こゝで、多層配線基板上にパターン形成さ
れているパッドは薄膜形成技術と写真蝕刻技術(ホトリ
ソグラフィ)により形成するため小型化に対応できる
が、こパッドにフラックスを供給する転写ピンは機械的
な強度を必要とすることから金属製であることが必要で
あり、また、少なくとも400 μm 以上の高さを必要とす
ることから、切削加工により作り、先端を有機チタンで
樹脂被覆してスタンプ性を向上させている。
Since the pads formed on the multilayer wiring board are formed by the thin film forming technique and the photolithography technique (photolithography), it can be miniaturized, but the transfer pins that supply the flux to the pads. Since it requires mechanical strength, it needs to be made of metal.Since it requires a height of at least 400 μm or more, it is made by cutting and the tip is resin-coated with organic titanium. To improve the stampability.

【0016】こゝで、従来の切削加工方法は先に記した
ように水平方向と垂直方向から切削を行って転写ピンが
マトリックス状に配列する転写ピン列を形成していた
が、ピッチが400 μm 以下に狭まると切削作業は不可能
となる。
Here, in the conventional cutting method, the transfer pin row in which the transfer pins are arranged in a matrix is formed by cutting in the horizontal direction and the vertical direction as described above, but the pitch is 400 If it is less than μm, cutting work becomes impossible.

【0017】そこで、本発明は複写ピン列を切削が可能
なように二分割するものであり、例えば、図1(A)に
示すような不規則なパターンを同図(B)と(C)に示
すような規則的なパターンに分割し、これを合成するこ
とにより微細ピッチのパッドに対しても、フラックス供
給を可能にするものである。
Therefore, the present invention divides the copy pin row into two parts so that it can be cut. For example, an irregular pattern as shown in FIG. By dividing the pattern into regular patterns as shown in (1) and synthesizing the patterns, flux can be supplied even to fine pitch pads.

【0018】[0018]

【実施例】セラミック多層配線基板上に図1に示すよう
に水平方向に300 μm ピッチで第1行目のパッドがあ
り、これより300 μm の間隔をおいて600 μm ピッチで
第2行目のパッドがあり、これより300 μm の間隔をお
き、千鳥状に600 μm ピッチで第3行目のパッドがあ
り、次に、これより300 μm の間隔をおき300 μm ピッ
チで第4行目のパッドが形成されている。
[Example] As shown in FIG. 1, there is a pad of the first row in the horizontal direction at a pitch of 300 μm on a ceramic multilayer wiring board, and a pad of the second row at a pitch of 600 μm with an interval of 300 μm from this. There is a pad, and there is a pad of 300 μm from this, and there is a pad of the 3rd row in a staggered pattern of 600 μm, and then a pad of the 4th row with a gap of 300 μm from this and a pitch of 300 μm. Are formed.

【0019】かゝる微細な形状のパッドに対しては一体
もので切削加工して転写ピン列を作ることは不可能であ
る。そこで、同図(B)と(C)に示すように規則的な
パターンに分解し、矢印で示す方向から切削加工を行な
うことにより容易に高さが400 μm で直径が200 μm の
転写ピン1よりなる転写ピン列8,9を作ることができ
た。
It is impossible to make a transfer pin row by cutting the pad having such a fine shape as an integral body. Therefore, the transfer pin 1 having a height of 400 μm and a diameter of 200 μm can be easily obtained by disassembling it into a regular pattern as shown in FIGS. It was possible to make transfer pin rows 8 and 9 consisting of.

【0020】そして、この転写ピン列8,9を図2に示
すように、従来と同様に位置決めテーブル3にある転写
ユニット4に装着し、従来と同様なシーケンシャル(Se
quential) 制御を行なわせる。すなわち、先ず、位置決
めテーブル3をフラックステーブル5の位置まで移行さ
せた後に降下させて、スキージで一定の厚さに塗布さて
いるフラックスを転写ピン列8で捺印して転写ピン1に
転写し、次に、元の位置まで上昇した後、次に、転写ピ
ン列9がフラックステーブル5の真上にくるように位置
決めテーブル3が移行した後に降下してフラックスを転
写ピン列9の転写ピン1に転写する。
Then, as shown in FIG. 2, the transfer pin rows 8 and 9 are mounted on the transfer unit 4 on the positioning table 3 as in the prior art, and the sequential (Se
quential) Control is performed. That is, first, the positioning table 3 is moved to the position of the flux table 5 and then lowered, and the flux applied to a certain thickness with a squeegee is imprinted on the transfer pin row 8 and transferred to the transfer pin 1. Then, after the positioning table 3 is moved so that the transfer pin row 9 is right above the flux table 5, the flux is transferred to the transfer pin 1 of the transfer pin row 9 after the positioning table 3 is moved so that the transfer pin row 9 is right above the flux table 5. To do.

【0021】次に、位置決めテーブル3を被処理基板6
の位置まで移行させた後に転写ユニット4を降下させ、
転写ピン列8でフラックスを被処理基板6のパッド上に
転写し、次に、同様な動作で転写ピン列9でフラックス
を被処理基板6のパッド上に転写することで塗布が完了
する。
Next, the positioning table 3 is placed on the substrate 6 to be processed.
After moving to the position of, the transfer unit 4 is lowered,
The application is completed by transferring the flux onto the pad of the substrate 6 to be processed by the transfer pin row 8 and then transferring the flux onto the pad of the substrate 6 to be processed by the transfer pin row 9 by the same operation.

【0022】[0022]

【発明の効果】このような方法をとることにより微細ピ
ッチで不規則にパターン形成されているパッドに対して
もフラックスの塗布を行なうことが可能となり、従来と
同様な製造効率を保持することができる。
By adopting such a method, it becomes possible to apply the flux even to a pad on which a pattern is irregularly formed with a fine pitch, and it is possible to maintain the same manufacturing efficiency as the conventional one. it can.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施法を示す転写ピン列の平面図で
ある。
FIG. 1 is a plan view of a transfer pin row showing a method for carrying out the present invention.

【図2】 本発明の実施法を示す断面図(A)と(B)
である。
2A and 2B are sectional views showing a method for carrying out the present invention.
Is.

【図3】 従来の転写ピン列の平面図(A)と実施法を
示す断面図(B)と(C)である。
FIG. 3 is a plan view (A) of a conventional transfer pin row and cross-sectional views (B) and (C) showing an implementation method.

【符号の説明】[Explanation of symbols]

1 転写ピン 2,8,9 転写ピン列 3 位置決めテーブル 4 転写ユニット 5 フラックステーブル 6 被処理基板 1 transfer pin 2,8,9 transfer pin row 3 positioning table 4 transfer unit 5 flux table 6 substrate to be processed

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 被処理基板(6)上に配列してパターン
形成してある複数のパッド上にフラックスを転写する方
法として、 複数のパッドに同時にフラックスを転写する転写ピン列
(8),(9)を、少なくとも二群に別けて転写ユニッ
ト(4)に設置し、該転写ユニット(4)が装着してあ
る位置決めテーブル(3)の移動により、 それぞれ別個にフラックステーブル(5)において転写
ピン(1)の先端にフラックスを付着させた後、次に、
該フラックスをパッド上に転写することを特徴とするフ
ラックスの転写方法。
1. A method of transferring flux onto a plurality of pads arranged and patterned on a substrate (6) to be processed, wherein transfer pin rows (8), ( 9) are installed in the transfer unit (4) separately in at least two groups, and the transfer table (3) mounted on the transfer unit (4) is moved so that transfer pins are separately transferred to the flux table (5). After attaching the flux to the tip of (1), next,
A method of transferring flux, which comprises transferring the flux onto a pad.
JP8700494A 1994-04-26 1994-04-26 Flux transfer method Withdrawn JPH07297238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8700494A JPH07297238A (en) 1994-04-26 1994-04-26 Flux transfer method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8700494A JPH07297238A (en) 1994-04-26 1994-04-26 Flux transfer method

Publications (1)

Publication Number Publication Date
JPH07297238A true JPH07297238A (en) 1995-11-10

Family

ID=13902768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8700494A Withdrawn JPH07297238A (en) 1994-04-26 1994-04-26 Flux transfer method

Country Status (1)

Country Link
JP (1) JPH07297238A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10224027A (en) * 1997-02-04 1998-08-21 Denso Corp Manufacture of semiconductor device
JPH10256713A (en) * 1997-03-13 1998-09-25 Samsung Electron Co Ltd Method of mounting ic package
JP2011009530A (en) * 2009-06-26 2011-01-13 Nec Corp Method of manufacturing flux transfer head

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10224027A (en) * 1997-02-04 1998-08-21 Denso Corp Manufacture of semiconductor device
JPH10256713A (en) * 1997-03-13 1998-09-25 Samsung Electron Co Ltd Method of mounting ic package
JP2011009530A (en) * 2009-06-26 2011-01-13 Nec Corp Method of manufacturing flux transfer head

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