JPH07297084A - Method for manufacturing chip solid electrolytic capacitor - Google Patents

Method for manufacturing chip solid electrolytic capacitor

Info

Publication number
JPH07297084A
JPH07297084A JP6091799A JP9179994A JPH07297084A JP H07297084 A JPH07297084 A JP H07297084A JP 6091799 A JP6091799 A JP 6091799A JP 9179994 A JP9179994 A JP 9179994A JP H07297084 A JPH07297084 A JP H07297084A
Authority
JP
Japan
Prior art keywords
layer
anode
metal layer
cathode
solid electrolytic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6091799A
Other languages
Japanese (ja)
Other versions
JP3429845B2 (en
Inventor
Koichi Mitsui
紘一 三井
Junichi Murakami
村上  順一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nichicon Corp
Original Assignee
Nichicon Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nichicon Corp filed Critical Nichicon Corp
Priority to JP09179994A priority Critical patent/JP3429845B2/en
Publication of JPH07297084A publication Critical patent/JPH07297084A/en
Application granted granted Critical
Publication of JP3429845B2 publication Critical patent/JP3429845B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To prevent a suction mistake on mounting by providing a cut-out so that the resin of the electrode formation part of an encapsulation resin layer becomes thin in the transfer mold system and covering it with an encapsulation resin layer. CONSTITUTION:When forming an encapsulation resin layer 2a at a capacitor element 1 where a dielectric oxide layer, electrolytic layer, carbon layer, and cathode layer are formed successively on the surface of an anode body consisting of a valve-operation metal with an anode leading wire, an encapsulation resin layer where a cut-out 2b is provided so that only the electrode formation part of the encapsulation resin layer on the electrode formation surface of a chip solid electrolytic capacitor becomes thin is covered by the transfer mold system so that the anode lead wire and the cathode layer are partially exposed. Then, by applying silver paste to the cut-out 2b of the encapsulation resin 2a, an electrode ground layer 3 is formed and an electroless plating layer 4 and an electrolytic solder plated layer 5 are formed on the electrode ground layer 3, thus constituting an anode metal layer and a cathode metal layer and hence achieving a positive and automatic packaging.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はチップ状固体電解コンデ
ンサに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip solid electrolytic capacitor.

【0002】[0002]

【従来の技術】従来のチップ状固体電解コンデンサは、
特開平5−226193号公報の実施例のごとく、図3
に一例を示すように、陽極導出線を具備した弁作用金属
からなる陽極体の表面に誘電体酸化皮膜、電解質層、カ
−ボン層、陰極層を形成してコンデンサ素子1を構成
し、このコンデンサ素子1の外側を陽極導出線および陰
極層の一部が表出するように外装樹脂層2aを被覆した
のち電極下地層3、無電解メッキ層4、電解はんだメッ
キ層5などからなる陽極金属層および陰極金属層を形成
していた。
2. Description of the Related Art A conventional chip-shaped solid electrolytic capacitor is
As in the embodiment of Japanese Patent Laid-Open No. 5-226193, FIG.
As shown in FIG. 1, a capacitor element 1 is constructed by forming a dielectric oxide film, an electrolyte layer, a carbon layer and a cathode layer on the surface of an anode body made of a valve metal having an anode lead wire. Anode metal composed of an electrode underlayer 3, an electroless plating layer 4, an electrolytic solder plating layer 5, etc. after covering the outside of the capacitor element 1 with an exterior resin layer 2a so that the anode lead wire and a part of the cathode layer are exposed. Layer and the cathode metal layer were formed.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、前記の
従来のチップ状固体電解コンデンサは、例えば外装樹脂
層上に銀ペ−ストなどの電極下地層、無電解メッキ層、
電解はんだメッキ層により、陽極金属層および陰極金属
層を形成する場合、チップ状固体電解コンデンサの電極
形成面において、電極下地層、無電解メッキ層、電解は
んだメッキ層の各層の厚みが累積し、合計約0.05m
mから0.10mmの陽極金属層および陰極金属層の厚
み分が外装樹脂面より突出する。また、無電解メッキ層
などで多重メッキ層を形成し、陽極金属層および陰極金
属層を構成した場合でも、合計約0.03mmから0.
05mmの陽極金属層および陰極金属層の厚み分が外装
樹脂面より突出する。
However, the above-mentioned conventional chip-shaped solid electrolytic capacitor has, for example, an electrode underlayer such as a silver paste, an electroless plating layer, and
By the electrolytic solder plating layer, when forming the anode metal layer and the cathode metal layer, on the electrode formation surface of the chip-shaped solid electrolytic capacitor, the electrode underlayer, the electroless plating layer, the thickness of each layer of the electrolytic solder plating layer is accumulated, Total about 0.05m
The thickness of the anode metal layer and the cathode metal layer of 0.10 mm from m protrudes from the exterior resin surface. Further, even when a multiple plating layer is formed by an electroless plating layer or the like to form an anode metal layer and a cathode metal layer, a total of about 0.03 mm to 0.
The thickness of the anode metal layer and the cathode metal layer of 05 mm protrudes from the exterior resin surface.

【0004】この為、チップ状固体電解コンデンサの電
極形成面に段差が生じ、自動実装時に吸着ノズルにより
搬送する際、吸着ノズルとチップ状固体電解コンデンサ
の上方表面との間で吸着エアリ−クが生じる場合があ
り、実装時に吸着ミスが生じる一因となっていた。また
チップ状固体電解コンデンサの下方となる基板に接する
面においては基板への装着時に安定性が悪く、実装不良
やはんだ付け時のツ−ムスト−ン現象の発生の一因とな
っていた。それに加え、チップ状固体電解コンデンサの
側面の突出部においては、自動実装時の画像認識エラ−
などの不具合が生じ、その実装作業性は悪いものであっ
た。
For this reason, a step is formed on the electrode forming surface of the chip solid electrolytic capacitor, and when carrying by the suction nozzle during automatic mounting, a suction air leak occurs between the suction nozzle and the upper surface of the chip solid electrolytic capacitor. In some cases, it may occur, which is one of the causes of a suction error during mounting. In addition, the surface of the chip-shaped solid electrolytic capacitor, which is located below the chip solid contacting the substrate, has poor stability when mounted on the substrate, which is one of the causes of the mounting failure and the occurrence of the Tsumstone phenomenon during soldering. In addition, the projection on the side of the chip solid electrolytic capacitor has an image recognition error during automatic mounting.
As a result, the mounting workability was poor.

【0005】本発明は、上記従来の問題点を解決するも
ので、自動実装時の実装性に優れ、ツ−ムスト−ン現象
の発生を防止することができる小形のチップ状固体電解
コンデンサを提供することを目的とするものである。
The present invention solves the above-mentioned conventional problems, and provides a small chip-shaped solid electrolytic capacitor which is excellent in mountability during automatic mounting and which can prevent the occurrence of the Tsumstone phenomenon. The purpose is to do.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するた
め、本発明のチップ状固体電解コンデンサは、金属板で
はなく、導電性塗料やメッキ層によって形成される陽極
金属層及び陰極金属層と外装樹脂層とが同一平面となる
よう陽極金属層と陰極金属層が形成される各部分の外装
樹脂層に切り欠き部を形成し、陽極導出線と陰極層の一
部が表出するように被覆し、その後、導電性塗料とメッ
キ層のいずれか一方またはこれらの組み合わせにより構
成する陽極金属層および陰極金属層を備えたものであ
る。
In order to achieve the above object, the chip solid electrolytic capacitor of the present invention is not a metal plate, but an anode metal layer and a cathode metal layer formed by a conductive paint or a plating layer, and an exterior. Cutouts are formed in the exterior resin layer of each part where the anode metal layer and the cathode metal layer are formed so that the resin layer is flush with the resin layer, and the anode lead wire and the cathode layer are partially exposed. Then, after that, it is provided with an anode metal layer and a cathode metal layer composed of either one of the conductive paint and the plating layer or a combination thereof.

【0007】すなわち、陽極導出線を具備した弁作用金
属からなる陽極体の表面に誘電体酸化皮膜、電解質層、
カ−ボン層、陰極層を順次形成したコンデンサ素子と、
トランスファ−モ−ルド方式でコンデンサ素子を被覆し
た外装樹脂層と、前記外装樹脂層の外部に引き出され、
それぞれ前記陽極導出線及び陰極層と接続する陽極金属
層及び陰極金属層とから成り、前記陽極金属層及び陰極
金属層は導電性塗料層とメッキ層とのいずれか一方また
はこれらの組み合わせにより構成し、かつ上記外装樹脂
層の外表面と同一平面となるように陽極金属層及び陰極
金属層が形成される部分の外装樹脂層に切り欠き部を形
成したことを特徴とするチップ状固体電解コンデンサで
ある。また、上記陽極金属層及び陰極金属層を形成する
部分の外装樹脂層の切り欠き部を形成する位置を実装時
におけるチップ状固体電解コンデンサの基板接地面と吸
着ノズルの吸着面と両側面とに設けたことを特徴として
いる。
That is, a dielectric oxide film, an electrolyte layer, and an electrolyte layer are formed on the surface of an anode body made of a valve metal having an anode lead wire.
A capacitor element in which a carbon layer and a cathode layer are sequentially formed,
An exterior resin layer that covers the capacitor element by a transfer mold method, and is drawn out of the exterior resin layer,
It is composed of an anode metal layer and a cathode metal layer connected to the anode lead wire and the cathode layer, respectively, and the anode metal layer and the cathode metal layer are composed of one or a combination of a conductive paint layer and a plating layer. And a chip-shaped solid electrolytic capacitor characterized in that a notch is formed in the exterior resin layer in a portion where the anode metal layer and the cathode metal layer are formed so as to be flush with the outer surface of the exterior resin layer. is there. Further, the position where the cutout portion of the exterior resin layer of the portion where the anode metal layer and the cathode metal layer are formed is formed on the substrate ground surface of the chip-shaped solid electrolytic capacitor during mounting, the suction surface of the suction nozzle, and both side surfaces. The feature is that it is provided.

【0008】[0008]

【作用】上記構成によれば、外装樹脂層に切り欠き部を
設けているため、例えば電極下地層、無電解メッキ層、
電解はんだメッキ層などからなる陽極金属層と陰極金属
層を形成した場合でもチップ状固体電解コンデンサの各
面が平坦になるので、吸着ノズル接触面からのエアリ−
クが無くなり、かつ、基板装着時の安定性が良くなり実
装不良やツ−ムスト−ン現象の発生を防止でき、又、画
像認識エラ−も生じなくなり、確実な自動実装が可能と
なる。
According to the above structure, since the notch is provided in the exterior resin layer, for example, the electrode underlayer, the electroless plating layer,
Even when an anode metal layer and a cathode metal layer composed of electrolytic solder plating layers are formed, each surface of the chip-shaped solid electrolytic capacitor becomes flat.
In addition, it is possible to prevent the occurrence of a mounting failure and a tombstone phenomenon by improving the stability when mounting on the board, and to prevent the image recognition error from occurring, so that reliable automatic mounting can be performed.

【0009】[0009]

【実施例1】以下に、本発明の一実施例について添付図
面を参照しつつ説明する。図1は、本発明の一実施例に
おけるチップ状固体電解コンデンサの断面図、図2は外
装樹脂層形成後の形状を表す斜視図を示したものであ
る。
Embodiment 1 An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a cross-sectional view of a chip solid electrolytic capacitor according to an embodiment of the present invention, and FIG. 2 is a perspective view showing the shape after forming an exterior resin layer.

【0010】図1、図2において、このコンデンサ素子
1は、陽極導出線を具備した弁作用金属からなる陽極体
の表面に誘電体酸化皮膜、電解質層、カ−ボン層、陰極
層を順次形成したものであり、前記コンデンサ素子1に
外装樹脂層2aを形成するとき、図2のようにチップ状
固体電解コンデンサの電極形成面の外装樹脂層の電極形
成部分のみが約0.070mm薄くなるよう切り欠き部
2bを設けた外装樹脂層を陽極導出線と陰極層の一部が
表出するようトランスファ−モ−ルド方式で被覆した。
In FIG. 1 and FIG. 2, in this capacitor element 1, a dielectric oxide film, an electrolyte layer, a carbon layer, and a cathode layer are sequentially formed on the surface of an anode body made of a valve metal having an anode lead wire. When the exterior resin layer 2a is formed on the capacitor element 1, only the electrode forming portion of the exterior resin layer on the electrode forming surface of the chip solid electrolytic capacitor is thinned by about 0.070 mm as shown in FIG. The exterior resin layer provided with the cutout portion 2b was covered by a transfer mold method so that the anode lead wire and a part of the cathode layer were exposed.

【0011】次に前記外装樹脂層の電極形成部分、即ち
外装樹脂層2aの切り欠き部2bに銀ペ−ストをディッ
ピングで約40μmの膜厚になるように塗布することに
より電極下地層3を形成し、前記電極下地層3上に無電
解メッキ層4が約10μmの膜厚になるように形成し、
膜厚が約20μmの電解はんだメッキ層5を形成して陽
極金属層及び陰極金属層を構成し、チップ状固体電解コ
ンデンサを製作した。
Next, the electrode base layer 3 is formed by applying a silver paste by dipping to the electrode forming portion of the exterior resin layer, that is, the cutout portion 2b of the exterior resin layer 2a so as to have a thickness of about 40 μm. And the electroless plating layer 4 is formed on the electrode base layer 3 to have a film thickness of about 10 μm.
An electrolytic solder plating layer 5 having a film thickness of about 20 μm was formed to form an anode metal layer and a cathode metal layer, and a chip solid electrolytic capacitor was manufactured.

【0012】このとき、電極下地層3、無電解メッキ層
4、電解はんだメッキ層5を形成して陽極金属層および
陰極金属層を構成する場合、外装樹脂層の電極形成部分
を薄くして切り欠き部2bを設けているため、外装樹脂
層2aと陽極金属層及び陰極金属層とが同一平面となっ
た、即ち、チップ状固体電解コンデンサの各面が平坦と
なったので、自動実装時、吸着ノズル接触面からのエア
リ−クが無くなり、かつ、基板への装着時の安定性が良
くなり、実装不良やツ−ムスト−ン現象の発生を防止す
ることができ、又、画像認識エラ−も生じなくなり、確
実な自動実装が可能となる。
At this time, when the electrode base layer 3, the electroless plating layer 4, and the electrolytic solder plating layer 5 are formed to form the anode metal layer and the cathode metal layer, the electrode forming portion of the exterior resin layer is thinned and cut. Since the cutout portion 2b is provided, the exterior resin layer 2a and the anode metal layer and the cathode metal layer are flush with each other, that is, each surface of the chip solid electrolytic capacitor is flat. Air leaks from the contact surface of the suction nozzle are eliminated, the stability when mounted on the board is improved, and it is possible to prevent mounting failures and the occurrence of a tombstone phenomenon. Will not occur and reliable automatic mounting will be possible.

【0013】また、上記実施例1では、陽極金属層と陰
極金属層を導電性塗料とメッキとの組み合わせにより構
成したが、導電性塗料またはメッキのいずれか一方のみ
で少なくとも一層以上形成することにより構成してもよ
い。但し、切り込み部2bの深さ即ち電極形成部分の外
装樹脂層の厚みは、陽極金属層と陰極金属層それぞれの
構成材料の厚みに応じて変更する必要がある。尚、前記
切り欠き部2bの位置、形状は、陽極金属層と陰極金属
層の形成部分、形状に合わせて変更してもよい。
In the first embodiment, the anode metal layer and the cathode metal layer are made of a combination of conductive paint and plating. However, by forming at least one or more layers of either conductive paint or plating. You may comprise. However, the depth of the cut portion 2b, that is, the thickness of the exterior resin layer of the electrode forming portion needs to be changed according to the thickness of the constituent materials of the anode metal layer and the cathode metal layer. The position and shape of the cutout 2b may be changed according to the formation and shape of the anode metal layer and the cathode metal layer.

【0014】[0014]

【発明の効果】以上のように、本発明のチップ状固体電
解コンデンサは、トランスファ−モルド方式で外装樹脂
層2aの電極形成部分の樹脂厚さが薄くなるよう切り欠
き部2bを設けて外装樹脂層を被覆した結果、例えば電
極下地層3、無電解メッキ層4、電解はんだメッキ層5
からなる陽極金属層、陰極金属層を形成した場合でも、
チップ状固体電解コンデンサの各面が平坦になるので、
自動実装時、実装不良やはんだ付け時のツ−ムスト−ン
現象の発生防止を達成し、又、画像認識精度が向上し、
確実な自動実装が可能となる。
As described above, according to the chip solid electrolytic capacitor of the present invention, the cutout portion 2b is provided by the transfer molding method so that the resin thickness of the electrode forming portion of the exterior resin layer 2a is reduced. As a result of coating the layers, for example, the electrode underlayer 3, the electroless plating layer 4, the electrolytic solder plating layer 5
Even when an anode metal layer and a cathode metal layer made of are formed,
Since each surface of the chip solid electrolytic capacitor is flat,
Achieves prevention of defective mounting and tombstone phenomenon during soldering, and improved image recognition accuracy.
Reliable automatic mounting is possible.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示すチップ状固体電解コン
デンサの外装樹脂層形成後の斜視図である。
FIG. 1 is a perspective view of an embodiment of the present invention after forming an exterior resin layer of a chip solid electrolytic capacitor.

【図2】本発明の一実施例を示すチップ状固体電解コン
デンサの断面図である。
FIG. 2 is a sectional view of a chip solid electrolytic capacitor showing an embodiment of the present invention.

【図3】従来のチップ状固体電解コンデンサの断面図で
ある。
FIG. 3 is a cross-sectional view of a conventional chip solid electrolytic capacitor.

【符号の説明】[Explanation of symbols]

1 コンデンサ素子 2a 外装樹脂層 2b 切り欠き部 3 電極下地層 4 無電解メッキ層 5 電解はんだメッキ層 1 Capacitor Element 2a Exterior Resin Layer 2b Notch 3 Electrode Base Layer 4 Electroless Plating Layer 5 Electrolytic Solder Plating Layer

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01G 9/24 C ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01G 9/24 C

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 陽極導出線を具備した弁作用金属からな
る陽極体の表面に誘電体酸化皮膜、電解質層、カ−ボン
層、陰極層を順次形成したコンデンサ素子と、トランス
ファ−モ−ルド方式でコンデンサ素子を被覆した外装樹
脂層と、前記外装樹脂層の外部に引き出され、それぞれ
前記陽極導出線及び陰極層と接続する陽極金属層及び陰
極金属層とから成り、前記陽極金属層及び陰極金属層は
導電性塗料層とメッキ層とのいずれか一方またはこれら
の組み合わせにより構成し、かつ上記外装樹脂層の外表
面と同一平面となるように陽極金属層及び陰極金属層が
形成される部分の外装樹脂層に切り欠き部を形成したこ
とを特徴とするチップ状固体電解コンデンサ。
1. A capacitor element in which a dielectric oxide film, an electrolyte layer, a carbon layer, and a cathode layer are sequentially formed on the surface of an anode body made of a valve metal having an anode lead wire, and a transfer mode method. The external resin layer covering the capacitor element with, and the anode metal layer and the cathode metal layer drawn out of the external resin layer and connected to the anode lead wire and the cathode layer, respectively, the anode metal layer and the cathode metal layer. The layer is composed of either one of a conductive paint layer and a plating layer or a combination thereof, and a portion of the portion where the anode metal layer and the cathode metal layer are formed so as to be flush with the outer surface of the exterior resin layer. A chip solid electrolytic capacitor having a notch formed in an exterior resin layer.
【請求項2】 陽極金属層及び陰極金属層を形成する部
分の外装樹脂層の切り欠き部を形成する位置を実装時に
おけるチップ状固体電解コンデンサの基板接地面と吸着
ノズルの吸着面と両側面とに設けたことを特徴とする請
求項1のチップ状固体電解コンデンサ。
2. A substrate grounding surface of a chip solid electrolytic capacitor, a suction surface of a suction nozzle, and both side surfaces of a chip solid electrolytic capacitor at the time of mounting a position where a cutout portion of an exterior resin layer of a portion where an anode metal layer and a cathode metal layer are formed is mounted. The chip-shaped solid electrolytic capacitor according to claim 1, wherein the chip-shaped solid electrolytic capacitor is provided in and.
JP09179994A 1994-04-28 1994-04-28 Manufacturing method of chip-shaped solid electrolytic capacitor Expired - Fee Related JP3429845B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP09179994A JP3429845B2 (en) 1994-04-28 1994-04-28 Manufacturing method of chip-shaped solid electrolytic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP09179994A JP3429845B2 (en) 1994-04-28 1994-04-28 Manufacturing method of chip-shaped solid electrolytic capacitor

Publications (2)

Publication Number Publication Date
JPH07297084A true JPH07297084A (en) 1995-11-10
JP3429845B2 JP3429845B2 (en) 2003-07-28

Family

ID=14036671

Family Applications (1)

Application Number Title Priority Date Filing Date
JP09179994A Expired - Fee Related JP3429845B2 (en) 1994-04-28 1994-04-28 Manufacturing method of chip-shaped solid electrolytic capacitor

Country Status (1)

Country Link
JP (1) JP3429845B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023120383A1 (en) * 2021-12-23 2023-06-29 パナソニックIpマネジメント株式会社 Electrolytic capacitor and production method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023120383A1 (en) * 2021-12-23 2023-06-29 パナソニックIpマネジメント株式会社 Electrolytic capacitor and production method thereof

Also Published As

Publication number Publication date
JP3429845B2 (en) 2003-07-28

Similar Documents

Publication Publication Date Title
JP3429845B2 (en) Manufacturing method of chip-shaped solid electrolytic capacitor
EP0436224B1 (en) Solid electrolytic capacitor and a method of producing the same
JP2845010B2 (en) Solid electrolytic capacitors
JP3149419B2 (en) Method for manufacturing solid electrolytic capacitor
JPH0132737Y2 (en)
JPH0992575A (en) Chip-type solid-state electrolytic capacitor
JP3396902B2 (en) Solid electrolytic capacitor and method of manufacturing the same
JP3306202B2 (en) Manufacturing method of chip-shaped solid electrolytic capacitor
JP3429837B2 (en) Manufacturing method of chip-shaped solid electrolytic capacitor
JP2773207B2 (en) Manufacturing method of chip-shaped solid electrolytic capacitor
JPS6222250B2 (en)
JPH05226193A (en) Solid-state chip electrolytic capacitor
JP2738183B2 (en) Chip-shaped solid electrolytic capacitor
JP3306200B2 (en) Manufacturing method of chip-shaped solid electrolytic capacitor
JPH07122465A (en) Manufacture of chip type solid electrolytic capacitor
JPH04284617A (en) Manufacture of solid electrolytic capacitor
JPH0345524B2 (en)
JP3208875B2 (en) Chip-shaped solid electrolytic capacitor and its manufacturing method
JP3433479B2 (en) Method for manufacturing solid electrolytic capacitor
JPS59115518A (en) Chip type electronic part and method of producing same
JPH0620885A (en) Chip-type solid-state electrolytic capacitor
JP2887913B2 (en) Chip-shaped solid electrolytic capacitor
JP2707863B2 (en) Chip-shaped solid electrolytic capacitor
JPS5882517A (en) Method of producing chip-shaped condenser
JPH05291087A (en) Chip-type solid electrolytic capacitor

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090516

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100516

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110516

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110516

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120516

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120516

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130516

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130516

Year of fee payment: 10

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130516

Year of fee payment: 10

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130516

Year of fee payment: 10

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130516

Year of fee payment: 10

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees