JPH07288269A - Electric component and manufacture thereof - Google Patents

Electric component and manufacture thereof

Info

Publication number
JPH07288269A
JPH07288269A JP6078502A JP7850294A JPH07288269A JP H07288269 A JPH07288269 A JP H07288269A JP 6078502 A JP6078502 A JP 6078502A JP 7850294 A JP7850294 A JP 7850294A JP H07288269 A JPH07288269 A JP H07288269A
Authority
JP
Japan
Prior art keywords
laminated
metal
exposed
thin plate
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6078502A
Other languages
Japanese (ja)
Other versions
JP3381375B2 (en
Inventor
Shigeo Ikeda
重男 池田
Ken Adachi
研 足立
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP07850294A priority Critical patent/JP3381375B2/en
Publication of JPH07288269A publication Critical patent/JPH07288269A/en
Application granted granted Critical
Publication of JP3381375B2 publication Critical patent/JP3381375B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Measuring Leads Or Probes (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Connecting Device With Holders (AREA)
  • Manufacturing Of Electrical Connectors (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE:To easily obtain an electrode aggregate, etc., wherein electrodes or metal bumps are arranged at a fine pitch, at low cost. CONSTITUTION:A plurality of insulating thin plates 1 which are made of insulating resin, an electric insulator, and a plurality of metal thin plates 2 which are made of a conductor are alternately laminated at a specified pitch to make a cubic laminated block or laminated thin plate 4. The insulating resin 1A exposed from at least one plane of the laminated block or laminated thin plate is eliminated and a recess of the uniform depth is formed on that plane. By this method, an electrode aggregate of such a structure that metal foils 2A of the metal thin plates 2 exposed on one plane can be obtained and then a lead frame or a probe aggregate which has this basic structure can also be obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、例えば、極めて高密
度に電子回路が集積された半導体チップ(以下、単に
「ICチップ」と記す)をパッケージして、多数のアウ
ターリードが導出された半導体集積回路装置(以下、単
に「IC」と記す)などの電子回路素子を電子回路配線
基板に実装できるコネクター、電子回路素子を搭載する
ことができるリードフレーム、IC又はICチップの電
気的諸特性を測定するためのプローブ集合体などの電子
部品及びその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a semiconductor chip in which electronic circuits are integrated with extremely high density (hereinafter simply referred to as "IC chip"), and a large number of outer leads are led out. Connectors for mounting electronic circuit elements such as integrated circuit devices (hereinafter simply referred to as "IC") on an electronic circuit wiring board, lead frames on which electronic circuit elements can be mounted, electrical characteristics of ICs or IC chips The present invention relates to an electronic component such as a probe assembly for measurement and a manufacturing method thereof.

【0002】[0002]

【従来の技術】本出願人が出願し、平成5年2月12日
に公開された特開平5−36457号「電子部品、その
応用装置及びそれらの製造方法」に開示された発明及び
平成5年12月15日に特許願第5─315180「プ
ローブ集合体、その製造方法及びそれを用いたIC測定
用プローブカード」と題して出願した発明では、例え
ば、電子回路素子用コネクターやIC用リードフレー
ム、そしてIC又はICチップの特性を測定、評価する
ためのプローバーなどのファインピッチの電極集合体を
得るために、複数の金属薄板と複数の絶縁薄板とを複数
枚交互に所定のピッチで積層して多層積層体を形成し、
これを適当な厚さに裁断し、得られた立方体状の積層ブ
ロックの少なくとも一平面に露出した複数の金属層をエ
ッチングして均一な深さの凹溝を形成し、これらの凹溝
に所望の加工を施してファインピッチの電極集合体を得
ている。
2. Description of the Related Art The invention disclosed in Japanese Patent Application Laid-Open No. Hei 5-36457, "Electronic Components, Applied Devices and Manufacturing Methods Thereof," filed by the present applicant and published on February 12, 1993, and Heisei 5 In the invention filed on Dec. 15, 2015, entitled “Probe Assembly, Method for Producing the Same, and Probe Card for IC Measurement Using the Same,” Japanese Patent Application No. 5-315180, for example, a connector for an electronic circuit element or an IC lead To obtain a fine-pitch electrode assembly such as a prober for measuring and evaluating the characteristics of the frame and IC or IC chip, a plurality of metal thin plates and a plurality of insulating thin plates are alternately laminated at a predetermined pitch. To form a multilayer laminate,
This is cut into an appropriate thickness, and a plurality of metal layers exposed on at least one plane of the obtained cubic laminated block are etched to form concave grooves having a uniform depth. Is processed to obtain a fine-pitch electrode assembly.

【0003】[0003]

【発明が解決しようとする課題】しかし、この先願の発
明の前記プローブ集合体などの電極集合体は、基本的に
積層ブロックを構成している金属薄板の金属を化学エッ
チングなどを施して凹溝を形成し、それらの凹溝に、例
えば、電極であるプローブを挿入、固定して、それらの
先端部の間隔調整をしなければならず、また、その反対
側の面に露出した金属薄板に別途にバンプを形成しなけ
ればならず、公知の電極集合体の製造よりも製造し易く
なっているものの、依然、このプローブを挿入、固定、
或いはバンプの形成などの面倒な作業が必要とされ、課
題として残っている。
However, in the electrode assembly such as the probe assembly of the invention of the earlier application, the metal of the thin metal plates which basically constitute the laminated block is basically subjected to the chemical etching or the like to form the concave groove. Must be formed, and the electrodes, for example, probes, which are electrodes, must be inserted and fixed in these grooves to adjust the distance between their tips, and to the metal plate exposed on the opposite surface. Although bumps have to be formed separately, it is easier to manufacture than known electrode assemblies, but this probe is still inserted, fixed,
Alternatively, troublesome work such as formation of bumps is required, which remains a problem.

【0004】[0004]

【課題を解決するための手段】そこでこの発明の電極集
合体は、導電材の複数の金属薄板と絶縁材の複数の絶縁
薄板とを交互に所定のピッチで積層した積層ブロック又
は積層薄板の少なくとも一平面に露出した前記絶縁材を
その厚さ方向に一部除去し、その同一露出平面に露出し
た前記金属を突出させて複数の電極を形成するようにし
た。
Therefore, the electrode assembly of the present invention is provided with at least a laminated block or a laminated thin plate in which a plurality of metal thin plates of a conductive material and a plurality of insulating thin plates of an insulating material are alternately laminated at a predetermined pitch. The insulating material exposed on one plane is partially removed in the thickness direction, and the metal exposed on the same exposed plane is projected to form a plurality of electrodes.

【0005】また、この発明のプローブ集合体は、導電
材の複数の金属薄板と絶縁材の複数の絶縁薄板とが交互
に所定のピッチで積層された状態の積層ブロックの長さ
方向における一部分を積層薄板状に構成し、この積層薄
板部の絶縁材を全て除去し、この積層薄板部の各金属の
一端を自由端とし、他端を基部とした複数本のプローブ
を形成するようにして構成した。
In the probe assembly of the present invention, a plurality of metal thin plates of conductive material and a plurality of insulating thin plates of insulating material are alternately laminated at a predetermined pitch to form a part in the length direction of the laminated block. It is configured by forming a laminated thin plate, removing all the insulating material of this laminated thin plate part, and forming a plurality of probes with one end of each metal of this laminated thin plate part as a free end and the other end as a base part did.

【0006】これらいずれの電子部品の前記絶縁体の除
去手段としては、研磨材が混入した液体ホーニング方法
などの物理的手段やウエットエッチング方法などの化学
的手段を用いている。
As a means for removing the insulator of any of these electronic parts, a physical means such as a liquid honing method mixed with an abrasive and a chemical means such as a wet etching method are used.

【0007】[0007]

【作用】従って、この発明によれば、ファインピッチの
電極集合体やプローブ集合体などの電子部品を既存の製
造設備を用いて、極めて容易に、歩留り良く製造するこ
とができ、大幅にコストダウンを計ることができる。
Therefore, according to the present invention, electronic components such as a fine-pitch electrode assembly and a probe assembly can be manufactured very easily with a good yield using existing manufacturing equipment, resulting in a significant cost reduction. Can be measured.

【0008】[0008]

【実施例】以下、図を用いて、この発明の電子部品及び
その製造方法を説明する。先ず、図1乃至図3を用いて
この発明の第1の実施例である電極集合体及びその製造
方法を説明する。図1はこの発明の第1の実施例である
電極集合体の製造方法の各工程を示す斜視図であり、図
2は図1の製造方法で製作されたこの発明の電極集合体
を示していて、同図Aはその斜視図、同図Bは同図Aの
B−B線上における一部断面図であり、そして図3は図
1の製造方法で製作されたこの発明の変形例の電極集合
体を示していて、同図Aはその斜視図、同図Bは金属バ
ンプの並列の一例を示した電極集合体の平面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An electronic component and a method for manufacturing the same according to the present invention will be described below with reference to the drawings. First, an electrode assembly according to a first embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. FIG. 1 is a perspective view showing each step of a manufacturing method of an electrode assembly according to a first embodiment of the present invention, and FIG. 2 shows an electrode assembly of the present invention manufactured by the manufacturing method of FIG. FIG. A is a perspective view thereof, FIG. B is a partial cross-sectional view taken along line BB of FIG. A, and FIG. 3 is an electrode of a modification of the present invention manufactured by the manufacturing method of FIG. FIG. 3A is a perspective view of the assembly, and FIG. 2B is a plan view of the electrode assembly showing an example of parallel metal bumps.

【0009】先ず、図1を用いて電極集合体の製造方法
を説明する。図1Aにおいて、先ず電極集合体を構成す
る材料を用意する。符号1は絶縁薄板を示す。この絶縁
薄板1は、接着剤の厚みも含めて0.15mmの板厚
の、例えば、エポキシ系、フェノール系などの熱硬化性
樹脂(例えば、ガラスエポキシ樹脂、PET、PI)と
かビニール系(例えば、塩化ビニール、酢酸ビニー
ル)、スチロール系などの熱可塑性樹脂を用いる。符号
2は金属薄板を示し、これもやはり接着剤の厚みも含め
て0.15mmの板厚の、前記絶縁薄板1と同一面積
の、例えば、銅、ベリリュームカッパーなどを用いる。
絶縁薄板1は最外層に存在するように積層するとよい。
First, a method of manufacturing an electrode assembly will be described with reference to FIG. In FIG. 1A, first, a material forming the electrode assembly is prepared. Reference numeral 1 indicates an insulating thin plate. The insulating thin plate 1 has a thickness of 0.15 mm including the thickness of the adhesive, and is made of thermosetting resin such as epoxy resin or phenol resin (for example, glass epoxy resin, PET, PI) or vinyl (for example, glass epoxy resin). , Vinyl chloride, vinyl acetate), and styrene-based thermoplastic resins. Reference numeral 2 denotes a metal thin plate, which is also made of a plate having a thickness of 0.15 mm including the thickness of the adhesive and having the same area as the insulating thin plate 1, such as copper or beryllium copper.
The insulating thin plates 1 may be laminated so as to be the outermost layer.

【0010】これらを一枚毎に交互に重ね合わせて真空
加熱成形することにより接着、多層に積層して、同図B
に示したような多層積層体3に仕上げる。この工程で
は、各層間に気泡が生じないように真空プレスを行いな
がら接着する。次に、同図Cに示したように、前記多層
積層体3を、図1Cの工程で、その多層積層体3の積層
方向に、そしてその長辺に沿って、5〜6mmの厚さで
裁断し、短冊状の積層ブロック4に切り出す。この裁断
された積層ブロック4の構造は、結果的には、二平面か
らなる露出面4A、4B(露出面4Bは露出面4Aの反
対面)が形成され、前記金属薄板2が断面角形の金属薄
板になっていて、これら複数の角形金属薄板が所定のピ
ッチで互いに平行に配列され、そしてこれらの角形金属
薄板間が絶縁樹脂で埋め尽くされ、これらの角形金属
(以下、単に「金属箔」と記すが、「箔」というよりも
「線」に近い)2Aと絶縁樹脂1Aとで前記露出面4
A、4Bを形成した状態になっている。
[0010] Each of these sheets is alternately laminated and vacuum heat-molded to bond them, and they are laminated in multiple layers.
The multilayer laminate 3 as shown in FIG. In this step, bonding is performed while vacuum pressing is performed so that air bubbles do not occur between the layers. Next, as shown in FIG. 1C, the multilayer laminate 3 is formed in a thickness of 5 to 6 mm in the stacking direction of the multilayer laminate 3 and along its long side in the step of FIG. 1C. It is cut and cut into strip-shaped laminated blocks 4. As a result, the structure of the cut laminated block 4 is such that the exposed surfaces 4A, 4B (the exposed surface 4B is the opposite surface of the exposed surface 4A) formed of two planes are formed, and the thin metal plate 2 has a rectangular cross section. These rectangular metal thin plates are arranged in parallel with each other at a predetermined pitch, and the space between these rectangular metal thin plates is filled with an insulating resin so that these rectangular metal (hereinafter simply referred to as “metal foil”). 2A and the insulating resin 1A, the exposed surface 4 is closer to the “line” than the “foil”.
A and 4B are formed.

【0011】この短冊状の積層ブロック4の露出面4
A、4Bを洗浄し、必要に応じて所定の箇所の面を、例
えば、シリコーンゴム、レジスト膜でマスキングし、図
1Daに示したように、液体ホーニングの手法を用い
て、ノズルNからSiO2 などの研磨材を含んだ高圧の
液体を噴射し、前記絶縁樹脂1Aを除去する。
The exposed surface 4 of the strip-shaped laminated block 4
A, 4B were washed and optionally a surface of a predetermined portion, for example, masked with silicone rubber, a resist film, as shown in FIG. 1 Da, using the technique of the liquid honing, SiO 2 from the nozzle N The insulating resin 1A is removed by jetting a high-pressure liquid containing an abrasive such as.

【0012】このような処理を施すと、図2に示したよ
うに、前記露出面4A及び又は4Bに、例えば、深さ
0.5mm程度の複数の凹溝5が、従って、複数の電極
6が形成された電極集合体110又は電極集合体120
を容易に得ることができる。図2Aの電極集合体110
は両露出面4A、4Bの前記絶縁樹脂1Aを除去した場
合の構造を示している。この電極集合体110を得るに
は、前記絶縁薄板1にガラスエポキシ樹脂を、前記金属
薄板2に銅を用いて構成した積層ブロック4を用い、そ
の両露出面4A、4Bに液体ホーニング処理を施すこと
により容易に得ることができる。
When this treatment is performed, as shown in FIG. 2, a plurality of recessed grooves 5 having a depth of, for example, about 0.5 mm are formed on the exposed surfaces 4A and / or 4B, and thus a plurality of electrodes 6 are formed. The electrode assembly 110 or the electrode assembly 120 in which the
Can be easily obtained. The electrode assembly 110 of FIG. 2A
Shows the structure when the insulating resin 1A on both exposed surfaces 4A and 4B is removed. In order to obtain this electrode assembly 110, a laminated block 4 configured by using glass epoxy resin for the insulating thin plate 1 and copper for the metal thin plate 2 is used, and both exposed surfaces 4A, 4B are subjected to liquid honing. It can be easily obtained.

【0013】この場合、前記両露出面4A、4Bにマス
キングを施す必要はなく、銅より硬度が柔らかいガラス
エポキシ樹脂の方が早く、大量に研磨、除去されて前記
凹溝5が形成されることになる。この場合の金属箔2A
である銅は、同図Bに示したように、その両側縁が丸く
研磨される程度で、この形状はむしろ好ましい形状であ
って、この電極集合体110をコネクターとして用いた
場合に、電極6が点または線接触の状態で、印刷配線基
板の配線電極と接触することができる。
In this case, it is not necessary to mask both exposed surfaces 4A and 4B, and the glass epoxy resin having a hardness lower than that of copper is faster, and the groove 5 is formed by polishing and removing a large amount. become. Metal foil 2A in this case
As shown in FIG. 3B, the copper is a shape in which both side edges are polished roundly, and this shape is rather preferable, and when the electrode assembly 110 is used as a connector, the electrode 6 Can be in point or line contact with the wiring electrodes of the printed wiring board.

【0014】図3Aに示した電極集合体120は、積層
ブロック4の両露出面4A、4Bの両端部のみをシリコ
ーンゴム、レジスト膜などでマスキングし、その他の部
分の絶縁樹脂1A及び金属箔2Aを除去して複数の金属
バンプ8を形成した構造のものである。これらの金属バ
ンプ8を、図3Bに示したように、電極集合体120の
露出面4A、4Bの中央部でその端部の方に突出させ、
両側縁部でそれらの端部から後退させるように配列、形
成することもでき、このような配列の金属バンプ8を備
えた電極集合体120であれば、印刷配線基板の配線間
隔にゆとりを持たせて設計することができる。前記の凹
溝5、電極6及び金属バンプ8は、前記多層積層体1及
び積層ブロック4の構成から、自ずから等間隔で互いに
平行な位置に形成されることになる。
In the electrode assembly 120 shown in FIG. 3A, only the both ends of both exposed surfaces 4A and 4B of the laminated block 4 are masked with silicone rubber, a resist film or the like, and the other portions of the insulating resin 1A and the metal foil 2A are masked. Is removed to form a plurality of metal bumps 8. As shown in FIG. 3B, these metal bumps 8 are projected toward the ends of the exposed surfaces 4A and 4B of the electrode assembly 120 at the center thereof.
It is also possible to arrange and form the side edge portions so as to recede from their ends, and the electrode assembly 120 provided with the metal bumps 8 of such an arrangement has a space in the wiring interval of the printed wiring board. It can be designed. Due to the configurations of the multilayer laminate 1 and the multilayer block 4, the groove 5, the electrode 6, and the metal bump 8 are naturally formed at equal intervals in parallel with each other.

【0015】これまでの説明では、液体ホーニングの手
法で積層ブロック4を表面処理する方法を挙げたが、前
記絶縁樹脂1Aを研磨、除去する方法は、図1Dbに示
したような化学エッチング手法を用いて行うことができ
る。この場合には、前記絶縁薄板1に熱可塑性樹脂を用
い、金属薄板2と積層した多層積層体3を出発基材にす
る。このような多層積層体3から切り出した複数の積層
ブロック4をメチルエチルケトンなどのケトン系溶剤が
入った槽Vに漬浸すると、前記絶縁樹脂1Aを除去する
ことができ、ほぼ同様の構造の電極集合体110などを
得ることができる。
In the above description, the method of surface-treating the laminated block 4 by the method of liquid honing is mentioned, but the method of polishing and removing the insulating resin 1A is the chemical etching method as shown in FIG. 1Db. Can be done using. In this case, a thermoplastic resin is used for the insulating thin plate 1, and the multilayer laminate 3 laminated with the metal thin plate 2 is used as a starting base material. When a plurality of laminated blocks 4 cut out from such a multilayer laminate 3 are immersed in a bath V containing a ketone solvent such as methyl ethyl ketone, the insulating resin 1A can be removed, and an electrode assembly having substantially the same structure can be obtained. The body 110 or the like can be obtained.

【0016】次に、図4乃至図7を用いてこの発明の第
2の実施例である電極集合体及びその製造方法を説明す
る。図4はこの発明の第2の実施例である電極集合体の
製造方法の各工程を説明する図であり、図5は図4の製
造方法で製作されたこの発明の第2の実施例の電極集合
体であるリードフレームを示す断面図であり、図6は図
5のリードフレームにICチップを搭載してICに構成
した構造を示していて、同図Aはその斜視図、同図Bは
同図AのB−B線上の断面図であり、そして図7は図6
のICを印刷配線基板に実装した場合の構造を示す断面
図である。
Next, an electrode assembly and a method for manufacturing the same according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a view for explaining each step of the manufacturing method of the electrode assembly which is the second embodiment of the present invention, and FIG. 5 shows the second embodiment of the present invention manufactured by the manufacturing method of FIG. FIG. 7 is a cross-sectional view showing a lead frame which is an electrode assembly, and FIG. 6 shows a structure in which an IC chip is mounted on the lead frame of FIG. 5 to form an IC, FIG. 6 is a sectional view taken along the line BB of FIG.
FIG. 6 is a cross-sectional view showing the structure when the IC of FIG.

【0017】先ず、図4を用いて、この発明の第2の実
施例である電極集合体の一つであるリードフレームの製
造方法を説明する。同図E以下の工程は、図1Cの工程
に続く工程ある。従って、この図には、図1の図A乃至
図Cの工程を省略した工程を示した。
First, a method of manufacturing a lead frame, which is one of the electrode assemblies according to the second embodiment of the present invention, will be described with reference to FIG. The process following the process in FIG. 1E is a process subsequent to the process in FIG. 1C. Therefore, in this figure, the steps in which the steps of FIGS. 1A to 1C are omitted are shown.

【0018】図4Eの工程では、図1Cの工程で得られ
た積層ブロック4を4本用意し、2本組の一対を互いに
それらの断面を対向させて、その二対を図のように、支
持盤兼底蓋20で支持し、円筒の成形用型Mの中に収容
する。互いに相対する積層ブロック4は所定の間隔で平
行に、そしてそれぞれの積層ブロック4の各金属箔2A
が一直線上に並ぶように配置することが肝要である。そ
して更に、それらの積層ブロック4の中心部に断面角形
の銅棒30を配置し、同じく支持盤兼底蓋20で支持す
る。
In the step of FIG. 4E, four laminated blocks 4 obtained in the step of FIG. 1C are prepared, and a pair of two is made to have their cross sections facing each other, and the two pairs are as shown in the figure. It is supported by the support board / bottom lid 20 and is housed in a cylindrical molding die M. Laminated blocks 4 facing each other are parallel to each other at a predetermined interval, and each metal foil 2A of each laminated block 4 is parallel to each other.
It is important to arrange so that they are aligned. Further, a copper rod 30 having a square cross section is arranged at the center of each of the laminated blocks 4 and is similarly supported by the support board / bottom lid 20.

【0019】次に、同図Fの工程で樹脂、例えば、エポ
キシ系樹脂35を注入し、硬化させると、同図Gの工程
で示したような成形電極集合円柱体40が得られる。こ
れをその長軸方向に垂直に、例えば、0.3〜0.5m
mの厚さで裁断すると、同図G及びHに図示したような
円板状の、電極集合素体41を一挙に得ることができ
る。
Next, when a resin, for example, an epoxy resin 35 is injected and hardened in the step of FIG. F, a molded electrode assembly cylindrical body 40 as shown in the step of G of the figure is obtained. This is perpendicular to the major axis direction, for example, 0.3 to 0.5 m
By cutting with a thickness of m, it is possible to obtain a disk-shaped electrode assembly element body 41 as shown in FIGS.

【0020】同図Hから明らかなように、金属箔2Aに
相当するものは幅が0.15mm、厚さが0.3〜0.
5mmで、もはや金属箔2Aとは言えない故、これを以
後、角形導電線42と呼ぶ。また、これらの角形導電線
42の一固まりを電極素子43と呼ぶ。更にまた、同図
Dにおける銅棒30は、厚さ0.3〜0.5mmの板状
になっており、これを、後に説明する理由により、放熱
板31と呼ぶ。
As is clear from FIG. 3H, the metal foil 2A has a width of 0.15 mm and a thickness of 0.3 to 0.
Since it is 5 mm and can no longer be said to be the metal foil 2A, this is hereinafter referred to as a square conductive wire 42. Further, a set of these rectangular conductive wires 42 is called an electrode element 43. Furthermore, the copper rod 30 in FIG. 3D has a plate shape with a thickness of 0.3 to 0.5 mm, and is called a heat dissipation plate 31 for the reason described later.

【0021】電極素子43は金属箔2Aの積層枚数の数
に相当する角形導電線42が露出した露出面43A、4
3Bを備え、これらの角形導電線42が互いに平行に配
列され、そして各角形導電線42間には絶縁薄板1のガ
ラスエポキシ樹脂などの絶縁樹脂1Aが充填されてい
て、互いに角形導電線42が絶縁されている。相対する
一対の電極素子43、例えば、同図Hにおいて、符号4
3aと43b及び43cと43dの各角形導電線42は
一直線状に配列されている。これらの電極素子43の相
互間及び放熱板31との間には絶縁樹脂36が充填さ
れ、それぞれ強固に固定されている。
The electrode element 43 has exposed surfaces 43A, 4A and 4A where the rectangular conductive wires 42 corresponding to the number of laminated metal foils 2A are exposed.
3B, these rectangular conductive wires 42 are arranged in parallel to each other, and an insulating resin 1A such as a glass epoxy resin of the insulating thin plate 1 is filled between the rectangular conductive wires 42 so that the rectangular conductive wires 42 are It is insulated. A pair of opposing electrode elements 43, for example, reference numeral 4 in FIG.
The rectangular conductive wires 42 of 3a and 43b and 43c and 43d are arranged in a straight line. An insulating resin 36 is filled between the electrode elements 43 and between the heat dissipation plate 31 and the electrode elements 43 are firmly fixed.

【0022】このような電極集合素体41は、図4Iに
示したように、露出面43A、43Bの内、例えば、露
出面43Bに露出した各電極素子43の角形導電線42
の外方の僅かな端部と放熱板31の表面をシリコーンゴ
ム、レジスト膜などでマスキングし、その他の部分は露
出させたまま、図1Daの工程で説明したような要領で
液体ホーニングする。
As shown in FIG. 4I, such an electrode assembly element body 41 has, for example, the rectangular conductive wire 42 of each electrode element 43 exposed on the exposed surface 43B among the exposed surfaces 43A and 43B.
Liquid honing is carried out in the same manner as described in the step of FIG. 1Da while masking the outer edge of the surface of the heat radiation plate 31 and the surface of the heat dissipation plate 31 with silicone rubber, a resist film, etc. and leaving the other parts exposed.

【0023】一方の露出面43Aはこのような表面処理
を施さない。そうすると、前記露出面43Bに露出した
絶縁樹脂36、絶縁樹脂1A及びマスキングされていな
い部分の角形導電線42は研磨材で研磨、除去されるこ
とになり、前記マスキングされた部分の前記各角形導電
線42は研磨、除去されず、この部分が金属バンプ44
になって、図5に示したような電極集合体の一つである
リードフレーム130を得ることができる。次に、これ
らの角形導電線42、金属バンプ44及び放熱板31に
金メッキ、半田メッキどを表面処理を施す。
One exposed surface 43A is not subjected to such surface treatment. Then, the insulating resin 36 exposed on the exposed surface 43B, the insulating resin 1A, and the non-masked portions of the square conductive wires 42 are polished and removed with an abrasive, and the square conductive portions of the masked portions are removed. The line 42 is not polished or removed, and this portion is a metal bump 44.
As a result, the lead frame 130, which is one of the electrode assemblies shown in FIG. 5, can be obtained. Next, the square conductive wires 42, the metal bumps 44, and the heat dissipation plate 31 are subjected to surface treatment such as gold plating and solder plating.

【0024】次に、図6にこのようなリードフレーム1
30を用いたIC50を示した。ICチップの放熱板3
1への搭載、印刷配線基板への実装が容易に行えるよう
にするための前処理として、このリードフレーム130
の両露出面43A、43Bを洗浄し、放熱板31、各角
形導電線42、金属バンプ44などに金メッキ、半田メ
ッキなどの表面処理を行った後に、ICチップ51を装
着する。このリードフレーム130の中央の放熱板31
は、従来のリードフレームのダイパッドに相当する部分
であるが、この放熱板31にICチップ51を銀ペース
トまたは熱圧着で接着し、ICチップ51に形成されて
いるファインピッチの各電極と前記角形導電線42の各
々とを金ワイヤ52で接続し、必要に応じて樹脂モール
ドするとQFP型IC50が完成する。同図Bは同図A
のB−B線上での断面図である。
Next, FIG. 6 shows such a lead frame 1.
IC50 using 30 is shown. IC chip heat sink 3
1 as a pre-process for facilitating mounting on the printed wiring board and mounting on the lead frame 130.
Both exposed surfaces 43A and 43B are washed, and after the surface treatment such as gold plating and solder plating is performed on the heat dissipation plate 31, each rectangular conductive wire 42, the metal bump 44, etc., the IC chip 51 is mounted. The heat dissipation plate 31 at the center of the lead frame 130
Is a portion corresponding to the die pad of the conventional lead frame. The IC chip 51 is adhered to the heat dissipation plate 31 by silver paste or thermocompression bonding, and each fine-pitch electrode formed on the IC chip 51 and the square shape are formed. The QFP type IC 50 is completed by connecting each of the conductive wires 42 with a gold wire 52 and resin-molding as necessary. The same figure B is the same figure A
3 is a cross-sectional view taken along line BB of FIG.

【0025】前記金属バンプ44は前記と同様の液体ホ
ーニング処理により電極集合素体41の露出面43Aに
も形成してもよい。また、このような金属バンプ44を
金ワイヤ52がボンディングされる前記角形導電線42
の各内端部に形成してもよい。また、前記銅棒30の代
わりに、ICチップ51のシリコンと同一の熱膨張を有
する42鉄ニッケルアロイを用いてもよい。
The metal bumps 44 may be formed on the exposed surface 43A of the electrode assembly element body 41 by the same liquid honing process as described above. In addition, the rectangular conductive wire 42 to which the gold wire 52 is bonded to the metal bump 44.
It may be formed at each inner end of the. Further, instead of the copper rod 30, a 42 iron nickel alloy having the same thermal expansion as the silicon of the IC chip 51 may be used.

【0026】図7に前記IC50を印刷配線基板60に
実装した状態を示した。符号61は印刷配線基板60の
表面に形成された電子回路の配線の端子部61で、これ
ら端子部61の表面上に前記放熱板31と各金属バンプ
44を合わせて配置し、例えば、リフロー炉に通して半
田付けすると、図示のように印刷配線基板60に表面実
装することができる。この実装後に、必要に応じて、I
C50全体を樹脂Rで覆うように封止し、保護する。
FIG. 7 shows a state in which the IC 50 is mounted on the printed wiring board 60. Reference numeral 61 is a terminal portion 61 of the wiring of the electronic circuit formed on the surface of the printed wiring board 60. The heat dissipation plate 31 and each metal bump 44 are arranged on the surface of the terminal portion 61 together, and, for example, a reflow furnace. When soldered through, it can be surface-mounted on the printed wiring board 60 as illustrated. After this implementation, I
The entire C50 is sealed so as to be covered with the resin R and protected.

【0027】以上の説明から明らかなように、この発明
のリードフレーム130のような電極集合体の金属バン
プは角形導電線と同体で一挙に形成するとができ、製造
工程、工数などを大幅に短縮できる。
As is apparent from the above description, the metal bumps of the electrode assembly such as the lead frame 130 of the present invention can be formed at once in the same body as the rectangular conductive wire, and the manufacturing process, man-hours, etc. can be greatly reduced. it can.

【0028】次に、図8乃至図12を用いて、この発明
の第3の実施例である電極集合素体及びその製造方法を
説明する。図8は図1に示した工程Cに続く工程を説明
するための図であって、積層ブロックを切削加工を施し
た状態の斜視図であり、図9は図8の切削加工で得られ
た積層ブロックの全表面にレジストを塗布する工程を説
明するための斜視図であり、図10は図9の工程に続く
露光工程を説明するための斜視図であり、図11は図1
0の露光工程で表面がマスキングされた状態の積層ブロ
ックに液体ホーニングを施す工程を示す斜視図であり、
そして図12は最終的に得られたこの発明のプローブ集
合体の斜視図である。
Next, with reference to FIGS. 8 to 12, an electrode assembly element and a method for manufacturing the same according to a third embodiment of the present invention will be described. FIG. 8 is a view for explaining a step following the step C shown in FIG. 1, and is a perspective view of a state where the laminated block is subjected to the cutting processing, and FIG. 9 is obtained by the cutting processing of FIG. FIG. 11 is a perspective view for explaining a step of applying a resist to the entire surface of the laminated block, FIG. 10 is a perspective view for explaining an exposure step following the step of FIG. 9, and FIG.
FIG. 6 is a perspective view showing a step of performing liquid honing on the laminated block whose surface is masked in the exposure step of 0.
FIG. 12 is a perspective view of the finally obtained probe assembly of the present invention.

【0029】図8Aに図1の裁断工程で多層積層体3を
やや厚めに裁断して積層ブロック4を得る。この積層ブ
ロック4の下面4Bから、点線Dで示した範囲で、その
厚さ方向に切削し、同図Bに示した形状の先端部71と
基部72からなる積層ブロック70に加工する。この場
合、複数の積層ブロック70を一直線状にワックスを用
いて定盤に固定し、切削すると量産できる。この積層ブ
ロック70の基部72の厚さは3mmで、先端部71の
厚さは、0.5mm程度にする。
In FIG. 8A, the multilayer block 3 is slightly thickened in the cutting step of FIG. 1 to obtain a laminated block 4. The lower surface 4B of the laminated block 4 is cut in the thickness direction within a range indicated by a dotted line D to form a laminated block 70 having a tip portion 71 and a base portion 72 having a shape shown in FIG. In this case, a plurality of laminated blocks 70 can be mass-produced by fixing the plurality of laminated blocks 70 in a straight line on a surface plate using wax and cutting. The base 72 of the laminated block 70 has a thickness of 3 mm, and the tip 71 has a thickness of about 0.5 mm.

【0030】次に、図9に示したように、この積層ブロ
ック70を洗浄した後、積層ブロック70の全表面にフ
ォトレジストを塗布してレジスト膜Pを形成する。そし
て次の図10の露光工程で、例えば、前記先端部41の
絶縁樹脂1Aの部分を形成するためのマスク(図示して
いない)を用いて、レジスト膜Pに紫外線を露光し、各
絶縁樹脂1A部分以外のレジストを硬化させ、次に、現
像して露光されなかった各絶縁樹脂1A部分のレジスト
を除去し、先端部71の絶縁樹脂1Aのみを露出させ
る。
Next, as shown in FIG. 9, after washing the laminated block 70, a photoresist is applied to the entire surface of the laminated block 70 to form a resist film P. Then, in the next exposure step of FIG. 10, the resist film P is exposed to ultraviolet rays using, for example, a mask (not shown) for forming the insulating resin 1A portion of the tip portion 41, and each insulating resin is exposed. The resist other than the 1A portion is cured, and then the resist of each insulating resin 1A portion which has not been exposed to light by development is removed to expose only the insulating resin 1A of the tip portion 71.

【0031】次に、図11に示した液体ホーニング工程
で、前記のようにマスキングされた状態の積層ブロック
70の先端部71にノズルNから高圧の研磨材を含んだ
液体を噴射して、前記絶縁樹脂1Aを研磨、除去する。
Next, in the liquid honing process shown in FIG. 11, the liquid containing the high-pressure abrasive is jetted from the nozzle N to the tip portion 71 of the laminated block 70 in the masked state as described above. The insulating resin 1A is polished and removed.

【0032】そうすると図12に示したように、前記先
端部71の各絶縁樹脂1Aが研磨、除去されて複数のプ
ローブ73が形成されたこの発明の電極集合体、即ち、
プローブ集合体140が得られる。これらのプローブ7
3は、各金属層2の一部分であるので、当然のことなが
ら、必然的に、互いに平行で等間隔で形成され、各基部
72の延長線上にある。
Then, as shown in FIG. 12, each insulating resin 1A of the tip portion 71 is polished and removed to form a plurality of probes 73, that is, the electrode assembly of the present invention, that is,
The probe assembly 140 is obtained. These probes 7
Since 3 is a part of each metal layer 2, it is naturally inevitably formed parallel to each other at equal intervals and on the extension of each base 72.

【0033】このように、この発明のプローブ集合体1
40は一挙にプローブ73を形成することができ、従来
技術のプローブ集合体のように、別の工程で製造された
凹溝付きの電極集合体のそれらの凹溝に、これも別途に
製造された単体のプローブを一本一本装着しなければな
らない工程を踏む必要がない。
Thus, the probe assembly 1 of the present invention
40 can form the probe 73 all at once, and like the probe assembly of the prior art, these are also separately manufactured in those concave grooves of the electrode assembly with the concave groove manufactured in another process. There is no need to go through the process of mounting each probe individually.

【0034】図13乃至図15に前記プローブ集合体1
40の改良型プローブ集合体を製造できる一部の製造工
程を示した。図13は図1に示した工程Cに続く工程
で、積層ブロックの切削加工を説明するための斜視図で
あり、図14は図13の切削加工で得られた積層ブロッ
クを示す斜視図、そして図15はこの発明の改良型プロ
ーブ集合体の斜視図である。
The probe assembly 1 is shown in FIGS. 13 to 15.
We have shown some manufacturing steps that can produce 40 improved probe assemblies. 13 is a perspective view for explaining a cutting process of the laminated block in a process following the process C shown in FIG. 1, and FIG. 14 is a perspective view showing the laminated block obtained by the cutting process of FIG. FIG. 15 is a perspective view of the improved probe assembly of the present invention.

【0035】図1の多層積層体3から裁断した積層ブロ
ック4を、図13の点線Dで示したようなラインで切削
し、図14に示した形状の積層ブロック80に仕上げ
る。即ち、この積層ブロック80は厚さが薄い先端部8
1と厚さが厚い基部82と、これらの中間部に形成され
た円弧状のバネ部83とからなり、この実施例において
は、このバネ部83は前記基部82の上面部から上方に
膨出した形状でその基部82に連結された構造になって
おり、更にこのバネ部83の延長線上に水平に先端部8
1が連結された構造で構成されている。
The laminated block 4 cut from the multilayer laminated body 3 in FIG. 1 is cut along a line as shown by the dotted line D in FIG. 13 to complete the laminated block 80 having the shape shown in FIG. That is, the laminated block 80 has a thin tip portion 8
1 and a thick base portion 82, and an arcuate spring portion 83 formed in the intermediate portion between them, and in this embodiment, the spring portion 83 bulges upward from the upper surface portion of the base portion 82. It has a structure in which it is connected to its base portion 82 in a curved shape, and the tip portion 8 is horizontally arranged on the extension line of this spring portion 83.
1 is connected.

【0036】この積層ブロック80に、図9乃至図11
を用いて説明したようなレジスト膜Pを施し、露光して
マスキングし、その後、前記先端部81に液体ホーニン
グを施せば、図15に示したような、先端部81及びバ
ネ部83の絶縁樹脂1Aが除去されて、中央部にバネ部
83が、それらの先端にプローブ84が形成されたプロ
ーブ集合体150を得ることができる。
The laminated block 80 is shown in FIGS.
If the resist film P as described above is applied, exposed and masked, and then liquid honing is applied to the tip portion 81, the insulating resin of the tip portion 81 and the spring portion 83 as shown in FIG. By removing 1A, it is possible to obtain the probe assembly 150 in which the spring portion 83 is formed at the center and the probe 84 is formed at the tip thereof.

【0037】このプローブ集合体150はバネ部83が
存在するので、従来技術のプローブ集合体と同様に、I
Cの測定時、そのICのアウターリードにプローブ84
を当接した場合に生じる衝撃を吸収することができる。
Since the probe assembly 150 has the spring portion 83, the probe assembly 150 has the same I as in the prior art probe assembly.
When measuring C, the probe 84 is attached to the outer lead of the IC.
It is possible to absorb the impact that occurs when abutting against.

【0038】前記プローブ集合体140は、図8におい
て、積層ブロック4を先端部71と基部72とが形成で
きるように切削したが、このプローブ集合体は必ずしも
このような基部72を形成する必要はなく、積層ブロッ
ク4全体を多層積層体3から先端部71の厚さで裁断し
て、厚みの薄い積層ブロックとし、基部72がないプロ
ーブ集合体としてもよく、その他、必要に応じて任意の
構造に形成することができる。
In the probe assembly 140 shown in FIG. 8, the laminated block 4 is cut so that the tip portion 71 and the base portion 72 can be formed, but this probe assembly does not necessarily need to form such a base portion 72. Alternatively, the entire laminated block 4 may be cut from the multilayer laminated body 3 at the thickness of the tip portion 71 to form a laminated block having a small thickness, and a probe assembly without the base portion 72 may be provided. Can be formed.

【0039】また、前記プローブ集合体140、150
の製造においては、液体ホーニングを用いて製造する実
施例を説明したが、絶縁薄板1に熱可塑性樹脂を用いれ
ば、第1の実施例で説明したように化学的エッチングを
用いて製造できる。なお、プローブ集合体では、前記金
属薄板2としてベリリュームカッパーを用いるとよい。
Further, the probe assemblies 140, 150
In the manufacturing of the above, the embodiment in which the liquid honing is used is described, but if the insulating thin plate 1 is made of the thermoplastic resin, it can be manufactured by the chemical etching as described in the first embodiment. In the probe assembly, beryllium copper may be used as the thin metal plate 2.

【0040】[0040]

【発明の効果】以上説明したように、この発明によれ
ば、ファインピッチの電極集合体の各種電極を既存の製
造設備を用いて、極めて容易に、歩留り良く製造するこ
とができ、大幅にコストダウンを計ることができる。特
に、この発明の電極集合体をコネクターやリードフレー
ムに応用した場合、それらの導体のそれぞれの所望の箇
所に金属バンプを同一の工程で一挙に自動的に形成する
ことができ、また、この発明の電極集合体をプローブ集
合体に応用した場合には、絶縁樹脂を除去することで、
相隣なるプローブを接触するなどの不良を生じさせるこ
となく、ファインピッチのプローブを一挙に形成するこ
とができ、従って、量産化に適し、安価にプローブ集合
体を製造することができる。
As described above, according to the present invention, various electrodes of a fine-pitch electrode assembly can be extremely easily manufactured with a high yield using the existing manufacturing equipment, and the cost can be significantly reduced. You can measure down. In particular, when the electrode assembly according to the present invention is applied to a connector or a lead frame, metal bumps can be automatically formed at a desired position of each of the conductors at once in the same step. When the electrode assembly of is applied to the probe assembly, by removing the insulating resin,
Fine-pitch probes can be formed all at once without causing defects such as contact between adjacent probes. Therefore, the probe assembly can be manufactured at low cost, which is suitable for mass production.

【図面の簡単な説明】[Brief description of drawings]

【図1】 この発明の第1の実施例である電極集合体の
製造方法の各工程を示す斜視図である。
FIG. 1 is a perspective view showing each step of a method for manufacturing an electrode assembly according to the first embodiment of the present invention.

【図2】 図1の製造方法で製作されたこの発明の電極
集合体を示していて、同図Aはその斜視図、同図Bは同
図AのB−B線上における一部断面図である。
2 shows an electrode assembly of the present invention manufactured by the manufacturing method of FIG. 1, FIG. 2A is a perspective view thereof, and FIG. 2B is a partial sectional view taken along line BB of FIG. is there.

【図3】 図1の製造方法で製作されたこの発明の変形
例の電極集合体を示していて、同図Aはその斜視図、同
図Bは金属バンプの並列の一例を示した電極集合体の平
面図である。
3 shows an electrode assembly of a modified example of the present invention manufactured by the manufacturing method of FIG. 1, FIG. 3A is a perspective view thereof, and FIG. 3B is an electrode assembly showing an example of parallel metal bumps. It is a top view of a body.

【図4】 この発明の第2の実施例である電極集合体の
製造方法の各工程を説明する図である。
FIG. 4 is a diagram illustrating each step of the manufacturing method of the electrode assembly according to the second embodiment of the present invention.

【図5】 図4の製造方法で製作されたこの発明の第2
の実施例の電極集合体であるリードフレームを示す断面
図である。
5 is a second view of the present invention manufactured by the manufacturing method of FIG.
FIG. 6 is a cross-sectional view showing a lead frame that is an electrode assembly of the embodiment of

【図6】 図5のリードフレームにICチップを搭載し
てICに構成した構造を示していて、同図Aはその斜視
図、同図Bは同図AのB−B線上の断面図である。
6 shows a structure in which an IC chip is mounted on the lead frame of FIG. 5 to form an IC, FIG. 6A is a perspective view thereof, and FIG. 6B is a cross-sectional view taken along line BB of FIG. is there.

【図7】 図6のICを印刷配線基板に実装した場合の
構造を示す断面図である。
7 is a cross-sectional view showing a structure when the IC of FIG. 6 is mounted on a printed wiring board.

【図8】 図1に示した工程Cに続く工程を説明するた
めの図であって、積層ブロックを切削加工を施した状態
の斜視図である。
FIG. 8 is a diagram for explaining a step that follows the step C shown in FIG. 1, and is a perspective view of a state where the laminated block is subjected to the cutting process.

【図9】 図8の切削加工で得られた積層ブロックの全
表面にレジストを塗布する工程を説明するための斜視図
である。
9 is a perspective view for explaining a step of applying a resist to the entire surface of the laminated block obtained by the cutting process of FIG.

【図10】 図9の工程に続く露光工程を説明するため
の斜視図である。
FIG. 10 is a perspective view for explaining an exposure process following the process of FIG.

【図11】 図10の露光工程で表面がマスキングされ
た状態の積層ブロックに液体ホーニングを施す工程を示
す斜視図である。
11 is a perspective view showing a step of performing liquid honing on the laminated block whose surface is masked in the exposure step of FIG.

【図12】 最終的に得られたこの発明のプローブ集合
体の斜視図である。
FIG. 12 is a perspective view of the finally obtained probe assembly of the present invention.

【図13】 図1に示した工程Cに続く工程で、積層ブ
ロックの切削加工を説明するための斜視図である。
FIG. 13 is a perspective view for explaining a cutting process of the laminated block in a step following the step C shown in FIG.

【図14】 図13の切削加工で得られた積層ブロック
を示す斜視図である。
14 is a perspective view showing a laminated block obtained by the cutting process of FIG.

【図15】 この発明の改良型プローブ集合体の斜視図
である。
FIG. 15 is a perspective view of an improved probe assembly of the present invention.

【符号の説明】[Explanation of symbols]

1 絶縁薄板 1A 絶縁樹脂 2 金属薄板 2A 金属箔 3 多層積層体 4 積層ブロック 4A 上面 4B 下面 5 凹溝 6 電極 8 金属バンプ 20 支持盤兼底蓋 30 銅棒 35 樹脂 36 絶縁樹脂 40 成形電極集合円柱体 41 電極集合素体 42 角形導電線 43 電極素子 43A 電極素子43の露出面 43B 電極素子43の露出面 44 金属バンプ 50 IC 51 ICチップ 52 金ワイヤ 60 印刷配線基板 61 端子部 70 積層ブロック 71 先端部 72 基部 73 プローブ 80 積層ブロック 81 先端部 82 基部 83 バネ部 84 プローブ 110 この発明の第1の実施例の電極集合体 120 第1の実施例の変形の電極集合体 130 この発明の第2の実施例の電極集合体である
リードフレーム 140 この発明の第3の実施例の電極集合体である
プローブ集合体 150 第3の実施例の電極集合体である改良型プロ
ーブ集合体 M 成形用型 N ノズル P レジスト膜 R 樹脂 V 槽
DESCRIPTION OF SYMBOLS 1 Insulation thin plate 1A Insulation resin 2 Metal thin plate 2A Metal foil 3 Multilayer laminate 4 Laminated block 4A Upper surface 4B Lower surface 5 Groove 6 Electrode 8 Metal bump 20 Support board / bottom lid 30 Copper rod 35 Resin 36 Insulation resin 40 Molded electrode assembly cylinder Body 41 Electrode Assembly Element 42 Rectangular Conductive Wire 43 Electrode Element 43A Exposed Surface of Electrode Element 43 43B Exposed Surface of Electrode Element 44 Metal Bump 50 IC 51 IC Chip 52 Gold Wire 60 Printed Wiring Board 61 Terminal Part 70 Laminated Block 71 Tip Part 72 Base part 73 Probe 80 Laminated block 81 Tip part 82 Base part 83 Spring part 84 Probe 110 Electrode assembly of the first embodiment of this invention 120 Electrode assembly of the modification of the first embodiment 130 Second of this invention Lead frame which is an electrode assembly of the embodiment 140 Electrode of the third embodiment of the present invention Probe assembly that is an assembly 150 Improved probe assembly that is an electrode assembly of the third embodiment M Molding mold N Nozzle P Resist film R Resin V Tank

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 導電材の複数の金属薄板と絶縁材の複数
の絶縁薄板とを交互に所定のピッチで積層した積層ブロ
ック又は積層薄板の少なくとも一平面に露出した前記絶
縁材を除去し、その同一露出表面に露出している金属を
突出させて電極を構成したことを特徴とする電極集合
体。
1. A laminated block or a laminated thin plate in which a plurality of metal thin plates made of a conductive material and a plurality of insulating thin plates made of an insulating material are alternately laminated at a predetermined pitch, and the insulating material exposed on at least one plane is removed. An electrode assembly characterized in that an electrode is formed by protruding metal exposed on the same exposed surface.
【請求項2】 請求項1に記載の電極集合体の突出した
金属で電極バンプを構成したことを特徴とする請求項1
に記載の電極集合体。
2. An electrode bump is formed of the protruding metal of the electrode assembly according to claim 1.
The electrode assembly according to 1.
【請求項3】 請求項2に記載の電極集合体を複数枚、
それらの露出金属の電極がその長さ方向に向くように所
定の間隔を開けて相対向して配置し、両者の中間に半導
体チップなどの電子回路素子の載置部を設け、前記電極
集合体の少なくとも裏面側の前記露出金属の電極の一部
に、その一部分が隆起した状態の電極バンプを形成した
ことを特徴とする電子回路素子用リードフレーム。
3. A plurality of electrode assemblies according to claim 2,
The exposed metal electrodes are arranged facing each other at a predetermined interval so that they are oriented in the length direction, and a mounting portion for an electronic circuit element such as a semiconductor chip is provided in the middle of the two, and the electrode assembly is provided. A lead frame for an electronic circuit element, characterized in that at least a part of the electrode of the exposed metal on the back surface side is formed with an electrode bump in a state where the part is raised.
【請求項4】 導電材の複数の金属薄板と絶縁材の複数
の絶縁薄板とが交互に所定のピッチで積層された状態の
積層薄板の長さ方向における一部分の前記絶縁材の全部
が除去され、この部分の各金属の一端が自由端として形
成された複数本のプローブで構成されていることを特徴
とするプローブ集合体。
4. A part of the insulating material in the length direction of the laminated thin plate in which a plurality of metal thin plates of a conductive material and a plurality of insulating thin plates of an insulating material are alternately laminated at a predetermined pitch is removed. A probe assembly, characterized in that one end of each metal in this portion is composed of a plurality of probes formed as free ends.
【請求項5】 導電材の複数の金属薄板と絶縁材の複数
の絶縁薄板とが交互に所定のピッチで積層された状態の
積層ブロックの長さ方向における一部分を積層薄板状に
構成し、この積層薄板部の絶縁材を全て除去して、この
積層薄板部の各金属の一端が自由端として形成された複
数本のプローブで構成されていることを特徴とするプロ
ーブ集合体。
5. A part of the laminated block in the length direction in which a plurality of metal thin plates of a conductive material and a plurality of insulating thin plates of an insulating material are alternately laminated at a predetermined pitch, is formed into a laminated thin plate shape. A probe assembly comprising: a plurality of probes each having one end of each metal of the laminated thin plate portion removed as a free end by removing all insulating material of the laminated thin plate portion.
【請求項6】 請求項4又は5に記載の積層薄板の一部
にバネが形成されていることを特徴とするプローブ集合
体。
6. A probe assembly, wherein a spring is formed on a part of the laminated thin plate according to claim 4 or 5.
【請求項7】 導電材の複数の金属薄板と絶縁材の複数
の絶縁薄板とを複数枚交互に所定のピッチで積層した立
方体状の積層ブロック又は積層薄板の少なくとも一平面
に露出した前記金属の全長又はその一部分を残して前記
平面に露出した前記絶縁材の全長又はその一部分及び前
記残余の金属を前記積層ブロック又は積層薄板の厚み方
向に部分的にまたは全部、物理的に又は化学的に除去す
ることを特徴とする電極集合体の製造方法。
7. A cubic laminated block in which a plurality of thin metal plates made of a conductive material and a plurality of insulating thin plates made of an insulating material are alternately laminated at a predetermined pitch, or the metal exposed on at least one plane of the laminated thin plate. Part or all, physically or chemically, of the entire length or a part of the insulating material exposed on the plane leaving the entire length or a part thereof and the residual metal partially or entirely in the thickness direction of the laminated block or laminated thin plate. A method of manufacturing an electrode assembly, comprising:
【請求項8】 導電材の複数の金属薄板と絶縁材の複数
の絶縁薄板とを複数枚交互に積層して所定のピッチの多
層積層体を形成し、その多層積層体を、その積層方向
に、所定の長さ、幅、厚さの立方体状の積層ブロック又
は積層薄板に裁断し、前記積層ブロックの場合はその一
部を切削して積層薄板となし、積層薄板の長さ方向の一
部又は全部の金属の表面をマスキングし、露出した前記
絶縁薄板の絶縁材を物理的に又は化学的に除去して、前
記金属薄板部の各金属を一端を自由端とし、他端を基部
とした複数本のプローブに形成することを特徴とする請
求項4又は5に記載のプローブ集合体の製造方法。
8. A plurality of metal thin plates made of a conductive material and a plurality of insulating thin plates made of an insulating material are alternately laminated to form a multilayer laminate having a predetermined pitch, and the multilayer laminate is arranged in the stacking direction. , Cut into cube-shaped laminated blocks or laminated thin plates having a predetermined length, width, and thickness, and in the case of the laminated blocks, cutting a part thereof to form a laminated thin plate, a part of the laminated thin plate in the longitudinal direction Or, by masking the surface of all the metals and physically or chemically removing the exposed insulating material of the insulating thin plate, each metal of the thin metal plate portion has one end as a free end and the other end as a base. The method for producing a probe assembly according to claim 4, wherein the probe assembly is formed into a plurality of probes.
JP07850294A 1994-04-18 1994-04-18 Electrode assembly, manufacturing method thereof, and lead frame using electrode assembly Expired - Fee Related JP3381375B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP07850294A JP3381375B2 (en) 1994-04-18 1994-04-18 Electrode assembly, manufacturing method thereof, and lead frame using electrode assembly

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07850294A JP3381375B2 (en) 1994-04-18 1994-04-18 Electrode assembly, manufacturing method thereof, and lead frame using electrode assembly

Publications (2)

Publication Number Publication Date
JPH07288269A true JPH07288269A (en) 1995-10-31
JP3381375B2 JP3381375B2 (en) 2003-02-24

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Application Number Title Priority Date Filing Date
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Country Link
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008026027A (en) * 2006-07-18 2008-02-07 Japan Electronic Materials Corp Probe card and manufacturing method of the same
JP2010019616A (en) * 2008-07-09 2010-01-28 Japan Electronic Materials Corp Contact probe complex, manufacturing method therefor, and manufacturing method of probe card
JP2010025861A (en) * 2008-07-23 2010-02-04 Kiyota Seisakusho:Kk Method for manufacturing laminate type probe and laminate type probe manufactured by the process
WO2015016099A1 (en) * 2013-08-02 2015-02-05 オムロン株式会社 Electroformed component and method for manufacturing same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0536457A (en) * 1991-03-15 1993-02-12 Sony Corp Electronic part, its application device, and manufacture thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0536457A (en) * 1991-03-15 1993-02-12 Sony Corp Electronic part, its application device, and manufacture thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008026027A (en) * 2006-07-18 2008-02-07 Japan Electronic Materials Corp Probe card and manufacturing method of the same
JP2010019616A (en) * 2008-07-09 2010-01-28 Japan Electronic Materials Corp Contact probe complex, manufacturing method therefor, and manufacturing method of probe card
JP2010025861A (en) * 2008-07-23 2010-02-04 Kiyota Seisakusho:Kk Method for manufacturing laminate type probe and laminate type probe manufactured by the process
WO2015016099A1 (en) * 2013-08-02 2015-02-05 オムロン株式会社 Electroformed component and method for manufacturing same
JP2015030887A (en) * 2013-08-02 2015-02-16 オムロン株式会社 Electroformed component and method for manufacturing the same
US9598784B2 (en) 2013-08-02 2017-03-21 Omron Corporation Electroformed component production method

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