JPH07283699A - Frequency multiplication circuit and frequency multiplier device using the same - Google Patents

Abstract

PURPOSE:To realize a frequency multiplication circuit whose configuration is simple and scale is small. CONSTITUTION:An input pulse is impressed on a transmission line 5 where the electric length of 1/8 wavelenths of the input pulse is provided and the termination is grounded and the input pulse is synthesized with the reflected wave by this transmission line 5. A half-wave rectification is performed for this pulse by a transistor 7. After this half-wave rectification, the rectified pulse is impressed on a transmission line 6 where the electric length of 1/4 wavelengths of the input pulse is provided and the termination is opened and the pulse which is synthesized with the reflected wave by this transmission line 6 is defined as an output pulse. Therefore, because a differentiating circuit and a delay circuit become unnecessary and the number of element is few, the configuration becomes simple.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency multiplying circuit and a frequency multiplying device using the same, and more particularly to a circuit used in a communication device or the like for multiplying the frequency of an input pulse and outputting the same, and a frequency multiplying circuit using the same. Regarding the device.

[0002]

2. Description of the Related Art In a conventional frequency multiplying circuit, an output pulse having a frequency multiplied is derived by passing an input pulse through a differentiating circuit or a delay circuit and then synthesizing it. This conventional circuit will be described with reference to the drawings.

FIG. 6A is a block diagram showing the structure of a conventional frequency multiplication circuit, and FIG. 6B is a waveform diagram showing its operation. In the figure, the conventional frequency multiplication circuit is
A differentiating circuit 14 for differentiating an input pulse applied to the input terminal 1, a positive / inverting amplifying circuit 15 for normalizing and inverting amplifying the differential output, a transistor 16 which is turned on / off by the normal output, and an on / off by an inverting output. Transistor 17 that operates, two power supplies 3 and 4, and resistor 18
It was composed of and. In addition, 2 is an output terminal.

That is, the input terminal 1 is connected to the input of the positive / inverse amplification circuit 15 via the differentiating circuit 14, and the normal / inverted outputs of the positive / inversion amplification circuit 15 are respectively the bases of the transistors 16 and 17. Connected to the transistor 16,
The collector of 17 is connected to the power supply 3, and the transistor 1
The emitters 6 and 17 are connected to the power supply 4 via the output terminal 2 and the resistor 18 at the contact 19.

In such a circuit configuration, the signal input from the input terminal 1, that is, (a) in FIG. 1 (b), is output as the differential waveform shown in (b) in FIG. This differential waveform is amplified by the positive / inverted amplification circuit 15. The forward-amplified signal has the waveform of (c) in the figure and is input to the base of the transistor 16, and the inverted-amplified signal has the waveform of (d) in the figure.
It is input to the base of 7. The waveforms shown in (c) and (d) of FIG. 6 are output to the output terminal 2 by the wired OR circuit including the transistors 16 and 17 as shown in (e) of FIG. This makes it possible to obtain an output signal having a frequency component that is twice the frequency component of the input signal.

Another conventional circuit is the circuit shown in FIG. 7 (a). That is, the input terminal 1 is connected to the first input terminal of the exclusive OR circuit (EX-OR) 21 and the input terminal of the delay circuit 20, and the second input of the exclusive OR circuit 21 via the delay circuit 20. Connected to the terminals,
Further, the output of the exclusive OR circuit 21 is connected to the output terminal 2. The delay circuit 20 has a function of delaying the phase by 1/4 cycle.

In such a circuit configuration, one of the signals input from the input terminal 1 is directly input to the first input terminal of the exclusive OR circuit 21 with the waveform (a) in FIG. One is the exclusive OR circuit 21 in which the waveform of (b) in FIG.
Is input to the second input terminal of. As a result, the waveforms of (a) and (b) in FIG. 2B are subjected to exclusive OR, and the waveform of (c) in FIG. As a result, a doubled signal is obtained. Incidentally, one using an exclusive OR circuit in the same manner is disclosed in JP-A-1-15281.
It is also disclosed in Japanese Patent Laid-Open No. 5 and No. 2-228810.

[0008]

The above-mentioned conventional frequency multiplier circuit is configured by using a differentiating circuit and a folding circuit, or a delay circuit and a digital circuit, etc., but these circuits include many transistors and resistors. There is a drawback that the device is required, the circuit is complicated and the scale becomes large.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object thereof is to provide a frequency multiplier circuit having a simple circuit configuration and a small scale, and a frequency multiplier device using the same. is there.

[0010]

A frequency multiplication circuit according to the present invention includes a first transmission line having an electrical length of ⅛ wavelength and grounded at a terminal to which an input pulse is applied; the input pulse and the first transmission line. Half-wave rectifying element for half-wave rectifying a composite wave of the reflected wave by the transmission line of the above, and a pulse after half-wave rectification by the half-wave rectifying element, which has an electrical length of 1/4 wavelength and whose end is opened. A second transmission line is included, and a composite wave of the pulse after the half-wave rectification and a reflected wave from the second transmission line is used as an output pulse.

The frequency multiplier according to the present invention comprises a first transmission line having an electrical length of ⅛ wavelength and grounded at the end to which an input pulse is applied; and a reflected wave from the input pulse and the first transmission line. A half-wave rectifying element for half-wave rectifying the composite wave of
A second transmission path having an electrical length of ¼ wavelength and having an end opened and to which a pulse after half-wave rectification by the half-wave rectifier is input, the pulse after half-wave rectification and the second transmission line. It has first and second multiplication circuits that use a composite wave of the reflected wave from the transmission line as an output pulse, and the output pulse of the first multiplication circuit is applied as an input pulse of the second multiplication circuit. Characterize.

[0012]

[Function] A first terminal having an electrical length of ⅛ wavelength and grounded at the end
An input pulse is applied to the transmission line of and is combined with the reflected wave from this transmission line. A half-wave rectified version of this is applied to a second transmission line having an electrical length of ¼ wavelength and having an open end, and a combination with a reflected wave from this transmission line is used as an output pulse.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1A is a block diagram showing the configuration of the first embodiment of the frequency multiplication circuit according to the present invention, and FIG. 1B is a waveform diagram showing its operation. In FIG. 6A, the same parts as those in FIG. 6A are designated by the same reference numerals.

In the figure, the frequency multiplication circuit according to the first embodiment of the present invention has a transmission line 5 whose one end is grounded and which has an electric length corresponding to a wavelength of 1/8 of the signal wavelength, and a reflected wave by this transmission line 5. NPN transistor 7 which is a half-end rectification element for half-wave rectifying the combined wave of the input pulse and the input pulse, and the combined wave after the half-end rectification is input and one end is opened and the signal wavelength is 1
And a transmission line 6 having an electrical length corresponding to a wavelength of / 4. In addition, 8 is a resistance.

That is, the input terminal 1 is connected to the other end of the first transmission line having an electrical length corresponding to 1/8 of the signal wavelength whose one end is grounded and the base of the transistor 7, and the collector of the transistor 7 is connected. Is connected to the power supply 3, and the emitter of the transistor 7 is connected to the output terminal 2 and the other end of the transmission line 6 having an electric length corresponding to a wavelength of ¼ of the opened signal wavelength and one end. Connected to the resistor 8.

The operation of this circuit will be described with reference to FIG. Pulse waveform input from input terminal 1 (b)
In (a), the phase is 1 /
It returns 4 wavelengths later. However, since the reverse reflection occurs at the grounded end, the waveform reflected by the transmission line 5 is shown in FIG. Therefore, at the contact point 9, 2 in (a) and (b) in the same figure.
From the two waveforms, the composite wave shown in (c) of the figure is obtained.

Here, by setting the bias voltage of the transistor 7 so that the transistor 7 conducts only at the center value of the waveform of FIG. 6C, the waveform of FIG. When input, the waveform of FIG. 9D appears at the emitter of the transistor 7. This waveform of (d) passes through the transmission line 6 and is reflected at the open end, resulting in phase 1
/ It returns with a delay of two wavelengths. However, since the light is normally reflected at the open end, the waveform reflected by the transmission line 6 is as shown in FIG. Therefore, at the contact 10, the two waveforms (d) and (e) in the figure become the composite wave in the figure (f).

This waveform (f) appears at the output terminal 2,
Therefore, a frequency component twice the frequency component of the input signal, that is, an output signal frequency doubled, can be obtained.

That is, the waveform appearing at the emitter of the transistor 7 as the half-wave rectifying element in FIG.
And Y12 and reflected as indicated by arrow Y13, and then combined with the original waveform at the contact 10 and indicated by arrow Y13.
It is transmitted like 14.

As described above, according to this embodiment, the frequency multiplication circuit can be constructed by two transmission lines, one transistor, and one resistance, and the circuit can be simplified as compared with the conventional circuit.

Regarding the two transmission lines 5 and 6,
Various types of known coaxial cables, microstrip lines, coplanar lines, etc. can be used. If a transistor or transmission line having a wide frequency band is used, a wider band can be supported.

FIG. 2 shows a second frequency multiplication circuit according to the present invention.
2 is a block diagram showing the configuration of the embodiment of FIG. 1, and the same portions as those in FIG. 1A are indicated by the same reference numerals. The difference from the first embodiment is that the PNP transistor 11 is used as the half-wave rectifying element instead of the NPN transistor. The other points are the same as those of the first embodiment.

In such a configuration, the bias voltage of the transistor 11 is set so that the transistor 11 conducts only at the center value of the waveform (c) of FIG. An output signal having twice the frequency component will appear.

The same output signal can be obtained by using a diode instead of a transistor as the half-wave rectifying element. That is, as shown in FIG. 3 showing the third embodiment of the present invention, if a diode 12 having an anode connected to the transmission line 5 side and a cathode connected to the transmission line 6 side is used, FIG. The same operation as in the above case is performed, and an output signal having a frequency component twice that of the input waveform appears at the output terminal 2.

Further, by changing the direction of the diode, as shown in FIG. 4 showing the fourth embodiment of the present invention, the diode 1 in which the cathode is connected to the transmission line 5 side and the anode is connected to the transmission line 6 side
If 3 is used, an output signal having twice the frequency component of the input waveform appears at the output terminal 2 as in the case of FIG.

Here, in each of the above embodiments, the doubling circuit has been described. However, by connecting the circuits in cascade, a 2 ^N multiplying device (N is a positive integer) can be obtained. For example, in the case of a quadruple multiplication device, a doubling circuit 300 may be provided after the doubling circuit 100 as shown in FIG.

In FIG. 5, a buffer circuit 200 for attenuation compensation is provided between the doubler circuits 100 and 300. However, if attenuation compensation is not required, this may be removed.

Further, in order to remove the DC component, a capacitor C1 is provided between the doubler circuit 100 and the buffer circuit 200, and a capacitor C2 is provided between the buffer circuit 200 and the doubler circuit 300.

It should be noted that three-stage cascade connection may be performed for the 8-times multiplication device, and four-stage cascade connection may be performed for the 16-times multiplication device.

[0031]

As described above, the present invention has an effect that a frequency multiplying circuit having a small scale can be constructed with a simple structure of two transmission lines and one half-wave rectifying element.
Further, if these frequency multiplying circuits are connected in series, there is an effect that a 2 ^N multiplying device can be constructed with a simple configuration. Furthermore, since the structure is simple, there is an effect that the cost of both the multiplication circuit and the device can be reduced.

[Brief description of drawings]

FIG. 1A is a block diagram showing a configuration of a frequency multiplication circuit according to a first embodiment of the present invention, and FIG. 1B is a waveform diagram showing its operation.

FIG. 2 is a block diagram showing a configuration of a frequency multiplication circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a frequency multiplication circuit according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a frequency multiplication circuit according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration example of a frequency multiplication device using any of the frequency multiplication circuits of FIGS.

FIG. 6A is a block diagram showing a configuration of a conventional frequency multiplication circuit, and FIG. 6B is a waveform diagram showing the operation thereof.

FIG. 7A is a block diagram showing the configuration of another conventional frequency multiplication circuit, and FIG. 7B is a waveform diagram showing its operation.

[Explanation of symbols]

 1 Input Terminal 2 Output Terminal 3, 4 Power Supply 5, 6 Transmission Line 7, 11 Transistor 12, 13 Diode

Claims (6)

[Claims] 1. A first transmission line having an electrical length of ⅛ wavelength of a wavelength corresponding to a repetition frequency of an input pulse, which is terminally grounded and to which the input pulse is applied, the input pulse and the first transmission line. After half-wave rectification by the half-wave rectifying element having a half-wave rectifying element for rectifying a composite wave of the reflected wave by the transmission line in half-wave, and having an electrical length of ¼ wavelength of the wavelength corresponding to the frequency And a second transmission line to which the pulse of
A frequency multiplication circuit, wherein a composite wave of the pulse after the half-wave rectification and a reflected wave from the second transmission line is used as an output pulse. 2. The frequency multiplier circuit according to claim 1, wherein the half-wave rectifying element is a transistor. 3. The frequency multiplier circuit according to claim 1, wherein the half-wave rectifying element is a diode. 4. A first transmission line having an electrical length of ⅛ wavelength of a wavelength corresponding to a repetition frequency of an input pulse, which is terminally grounded and to which the input pulse is applied, the input pulse and the first transmission line. After half-wave rectification by the half-wave rectifying element having a half-wave rectifying element for rectifying a composite wave of the reflected wave by the transmission line in half-wave, and having an electrical length of ¼ wavelength of the wavelength corresponding to the frequency And a second transmission line to which the pulse of
It has first and second multiplication circuits that use a composite wave of the pulse after the half-wave rectification and the reflected wave from the second transmission line as an output pulse, and the output pulse of the first multiplication circuit is the first pulse. Two
A frequency multiplication device characterized in that it is applied as an input pulse of a frequency multiplication circuit. 5. The frequency multiplier according to claim 4, wherein the half-wave rectifying element is a transistor. 6. The frequency multiplier according to claim 4, wherein the half-wave rectifying element is a diode.