JP3068044B2 - Differential amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier for outputting differentially amplified power in response to a pair of signal inputs.

[0002]

2. Description of the Related Art Conventionally, a differential amplifier has been used in an oscillation circuit of a cellular phone, and such a differential amplifier is disclosed in, for example, Japanese Patent Application Laid-Open Nos. Hei 7-307625 and Hei 1-232.
806 and Japanese Utility Model Laid-Open No. 1-155521. FIG. 5 shows a conventional example of such a differential amplifier.
This will be described below with reference to FIG. FIG. 5 is a circuit diagram showing a conventional differential amplifier.

The differential amplifier 1 exemplified here includes a differential circuit 2, an output buffer circuit 3, and a regulator circuit 4 as main parts. The differential circuit 2 includes first and second signal input terminals 11 and 12 to which a pair of signals are individually input.
2 is individually connected to the respective base terminals of the first and second differential transistors 13 and 14.

The first and second differential transistors 13,
14 is connected to the first and second differential resistance elements 1
5 and 16 are individually connected. The first and second differential resistance elements 15 and 16 and the first and second differential transistors 1 and 16 are connected to each other.
First and second differential output terminals 17 and 18 are individually provided at connection points between the collector terminals 3 and 14.

Each of the first and second differential transistors 13 and 14 is commonly connected to a pair of power supply terminals 19 and 20 via the above-mentioned first and second differential resistance elements 15 and 16 and the like. I have. More specifically, the first and second differential transistors 1
First and second differential resistance elements 1 having first and third terminals connected to one end
The other ends of 5 and 16 are connected to one, and a positive power supply terminal 19 is connected thereto via one resistance element 21.

The first and second differential transistors 13,
The first and second switching transistors 22 and 23 and the first and second resistance elements 24 and 25 are individually connected to the emitter terminal of the switching element 14.
Are connected to a grounded power supply terminal 20.

A regulator circuit 4 is also connected to the power supply terminals 19 and 20 as described above. This regulator circuit 4 is a switching transistor having both ends connected to the power supply terminals 19 and 20 via resistance elements 31 and 32. 33. The base terminals of the switching transistor 33 of the regulator circuit 4 and the switching transistors 22 and 23 of the differential circuit 2 are connected to one control terminal 34, and a bias control circuit (not shown) is connected to the control terminal 34. Have been.

A bias terminal 35 is provided at a connection point between the resistance element 31 and the switching transistor 33 of the regulator circuit 4. The bias terminal 35 of the regulator circuit 4 and the differential output terminal 17 of the differential circuit 2 are provided. 18
Are connected to the output buffer circuit 3.

The output buffer circuit 3 is formed as a push-pull type, and has first and second output transistors 41,
42 and one output resistance element 43 are connected to a pair of power supply terminals 1.
It is connected in series between 9, 20 in series. The first differential output terminal 17 of the differential circuit 2 is connected to the base terminal of the first output transistor 41, and the second differential output terminal is connected to the base terminal of the second output transistor 42. 18
Are connected via an AC extraction capacitor 44, and the bias terminal 35 of the regulator circuit 4 is also connected via a bias resistance element 45.

The output buffer circuit 3 having the above structure
Is provided with a power output terminal 46 at a connection point between the first and second output transistors 41 and 42, and a predetermined load circuit 48 to be driven is connected to the power output terminal 46 via one capacitor 47. Is connected.

When a pair of signals are input to the first and second signal input terminals 11 and 12, the differential amplifier 1 having the above-described structure outputs power of a voltage corresponding to the difference between these signals to the power output. The signal can be output from a terminal 46 to an external load resistor 48.

In this case, a pair of power supply terminals 1 is provided at both ends of the first and second differential transistors 13 and 14 of the differential circuit 2.
Since a voltage is applied to the first and second signal input terminals 11 and 12 from the first and second signal input terminals 11 and 12, since a voltage is applied from the first and second differential resistance elements 15 and 16 to the first and second differential resistance elements 15 and 16, respectively. When externally input to the base terminals of the driving transistors 13 and 14, respectively, the connection is made to the connection midpoint between the first and second differential transistors 13 and 14 and the first and second differential resistance elements 15 and 16. At the first and second differential output terminals 17 and 18, a differential signal whose voltage corresponds to the difference between the pair of input signals is generated.

The first and second output transistors 41 and 42 of the output buffer circuit 3 to which these signals are individually input to the base terminal are connected to the power supply terminal 1 together with the output resistance element 43.
9 and 20, the power supply output terminal 46 provided at the midpoint of the connection between the first and second output transistors 41 and 42 has a load resistance 48 corresponding to the difference between a pair of input signals. The power of the output voltage is output.

At this time, a positive voltage is applied from the positive power supply terminal 19 to the load circuit 48 via the first output transistor 41, and the second output transistor 42 and the output resistance element 43 are connected from the load circuit 48. Since the voltage of the negative electrode can be drawn into the power supply terminal 20 that is grounded, the output buffer circuit 3 can supply the power corresponding to the input signal to the load circuit 48 by the push-pull operation.

[0015]

In the differential amplifier 1 as described above, a signal corresponding to the difference between a pair of input signals can be generated by the differential circuit 2, and the power corresponding to this signal is output to an output buffer. Since the circuit 3 can supply the load circuit 48 with the push-pull operation by the push-pull operation, the load circuit 48 can be driven with high efficiency.

However, in the differential amplifier 1 as described above,
It has been found that when the input signal has a high frequency, the gain of the output power decreases. That is, in order to accurately execute the push-pull operation of the output buffer circuit 3 as described above, the signals of the emitter terminal of the first output transistor 41 and the collector terminal of the second output transistor need to be in phase. There is.

However, the first and second output transistors 4
1, 42 are not the same in connection relation and the like.
One more base-collector connection is inserted from 1 and 12 to the collector terminal of the second output transistor 42 than to the emitter terminal of the first output transistor 41.

Therefore, the input from the first and second signal input terminals 11 and 12 of the differential circuit 2 to the emitter terminal of the first output transistor 41 and the collector terminal of the second output transistor 42 of the output buffer circuit 3. When the frequency increases, the signal input from the second input terminal 12 to the collector terminal of the second output transistor 42 becomes the first input terminal. The delay from 11 to the signal input to the emitter terminal of the first output transistor 41 is delayed, so that the in-phase relationship is not maintained and the gain is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a differential amplifier in which a decrease in gain of an input signal in a high frequency region is reduced.

[0020]

According to one aspect of the present invention, when a pair of input signals are individually input to a first and second signal input terminals, a pair of differential signals is output from the first and second differential output terminals. And a push-pull type output buffer circuit comprising a first and second output transistor and an output resistance element connected in series, and a differential circuit for outputting the differential signal. A first and second differential output terminal is connected to a base terminal of a first and second output transistor of the output buffer circuit, and a power output terminal is provided at a connection midpoint between the first and second output transistors. In the differential amplifier, a connection midpoint between the second output transistor and the output resistance element and the first signal input terminal are connected via a high-frequency bypass capacitor.

Therefore, when the differential circuit outputs a pair of differential signals from the first and second differential output terminals in response to a pair of input signals individually input to the first and second signal input terminals, Since these differential signals are input to the base terminals of the first and second output transistors of the output buffer circuit, an input signal is provided to a power output terminal provided at a connection point between the first and second output transistors. Is output by the push-pull operation.

At this time, the connection point between the second output transistor and the output resistance element and the first signal input terminal are connected via the high-frequency bypass capacitor. The signal phase at the emitter terminal of the transistor will be preceded.
For this reason, even if the input signal has a high frequency, the signal at the collector terminal of the second output transistor is substantially in phase with the emitter terminal of the first transistor, so that the push-pull operation is maintained at this portion.

The high-frequency bypass capacitor referred to in the present invention is a capacitor that bypasses a high frequency having a predetermined frequency or higher. The bypass frequency is set according to various conditions such as required performance and use environment. For example, 1 GHz is allowed.

In another differential amplifier according to the present invention, a first and second signal input terminals to which a pair of signals are individually input, and the first and second signal input terminals are individually connected to respective base terminals. The first and second differential transistors, the first and second differential resistance elements individually connected to the collector terminals of these first and second differential transistors, and the first and second differential resistance A first second differential output terminal individually connected to a connection midpoint between the element and the first second differential transistor, and an AC extraction capacitor connected to the second differential output terminal; A pair of power supply terminals commonly connected to both ends of the first and second differential transistors via the first and second differential resistance elements, and one of the pair of power supply terminals is connected to a collector terminal A first differential output terminal connected to a base terminal A second output transistor having an emitter terminal connected to the collector terminal of the first output transistor and a second differential output terminal connected to the base terminal via the AC extraction capacitor; An output resistor element having an emitter terminal connected to one end of the second output transistor and the other end of the power supply terminal connected to the other end; and a second differential output terminal connected to a base terminal of the second output transistor. A regulator circuit connected in parallel to generate a DC bias; a power output terminal connected to a connection midpoint between the first and second output transistors; and a connection between the second output transistor and the output resistance element. A high-frequency bypass capacitor connected to the midpoint and the first signal input terminal.

Accordingly, since a voltage is applied to both ends of the first and second differential transistors from the pair of power supply terminals via the first and second differential resistance elements, the pair of signals are applied to the first and second differential transistors. Are individually input to the base terminals of the first and second differential transistors from the signal input terminals of the first and second differential transistors. A differential signal corresponding to the difference between the pair of input signals is output to the first and second differential output terminals.

The output signal of the first differential output terminal is supplied to the base terminal of the first output transistor, and the output signal of the second differential output terminal is extracted from the AC output capacitor only after the AC component is extracted. Is supplied to the base terminal of the output transistor. Since a voltage is applied from the power supply terminal to both ends of the first and second output transistors and the output resistance element connected in series, a differential signal is supplied to the first and second output transistors as described above. Then, the power corresponding to the difference between the pair of input signals and the power corresponding to the difference between the pair of input signals is generated by the push-pull operation at the power output terminals provided at these connection midpoints.

At this time, since the connection point between the second output transistor and the output resistance element and the first signal input terminal are connected via the high-frequency bypass capacitor, the second output transistor is connected by the high-frequency bypass capacitor. The signal phase at the emitter terminal of the transistor will be preceded.
For this reason, even if the input signal has a high frequency, the signal at the collector terminal of the second output transistor is substantially in phase with the emitter terminal of the first transistor, so that the push-pull operation is maintained at this portion.

According to another aspect of the differential amplifier as described above, the output resistor is controlled so that the signal phases of the emitter terminal of the first output transistor and the collector terminal of the second output transistor are substantially the same. The resistance value of the element and the capacitance value of the high frequency bypass capacitor are set.

Therefore, the signal phase of the emitter terminal of the first output transistor and the signal phase of the collector terminal of the second output transistor are made substantially in phase by the resistance value of the output resistance element and the capacitance value of the high-frequency bypass capacitor. The push-pull operation is maintained even if the input signal has a high frequency.

According to another aspect of the above-described differential amplifier, the high-frequency bypass capacitor may have a capacitance of 1.0 pF or less. It is also allowed that the resistance value of the output resistance element is about 100Ω and the capacitance value of the high frequency bypass capacitor is about 0.7 pF.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. Note that the same portions as those of the conventional example described above with respect to the present embodiment are denoted by the same names, and detailed description is omitted.

FIG. 1 is a circuit diagram showing the differential amplifier of the present embodiment, and FIG. 2 is a semilogarithmic graph showing the frequency characteristics of the differential amplifier of the present embodiment and a conventional differential amplifier. is there. FIG. 3 is a semilogarithmic graph showing a phase relationship between respective parts of the differential amplifier according to the present embodiment and a conventional differential amplifier.
FIG. 4 is a time chart showing signal waveforms at respective parts of the differential amplifier of the present embodiment and a conventional differential amplifier.

As shown in FIG. 1, the differential amplifier 51 according to the present embodiment has a differential circuit 52, an output buffer circuit 53, and a regulator circuit as main parts, similarly to the differential amplifier 1 described above as a conventional example. 54. The differential circuit 52 includes first and second signal input terminals 61 and 62 to which a pair of signals are individually input, and the first and second signal input terminals 61 and 62 are connected to the first and second signal input terminals 61 and 62, respectively. Each of the differential transistors 63 and 64 is individually connected to the base terminal.

The first and second differential transistors 63,
64, the first and second differential resistance elements 6
5 and 66 are individually connected. The first and second differential resistance elements 65 and 66 and the first and second differential transistors 6 and 66 are connected to each other.
First and second differential output terminals 67 and 68 are individually provided at connection points between the collector terminals 3 and 64.

Each of the first and second differential transistors 63 and 64 is commonly connected to a pair of power supply terminals 69 and 70 via the above-mentioned first and second differential resistance elements 65 and 66 and the like. I have. More specifically, the first and second differential transistors 6
First and second differential resistance elements 6 having one end connected to one end
The other ends of the reference numerals 5 and 66 are connected to one, and a positive power supply terminal 69 is connected to the other end via one resistance element 71.

Further, the first and second differential transistors 63,
The first and second switching transistors 72 and 73 and the first and second resistance elements 74 and 75 are individually connected to the emitter terminal of the resistance element 64.
Are connected to a grounded power supply terminal 70.

The regulator circuit 54 is also connected to the power terminals 69 and 70 as described above.
And a switching transistor 83 to which a collector terminal and an emitter terminal are connected via the switching transistor 83.

The base terminals of the switching transistor 83 of the regulator circuit 54 and the switching transistors 72 and 73 of the differential circuit 52 are one control terminal 84.
The control terminal 84 is connected to a bias control circuit (not shown).

A bias terminal 85 is provided at a connection point between the resistance element 81 and the switching transistor 83 of the regulator circuit 54.
Bias terminal 85 and the differential output terminal 6 of the differential circuit 52.
7, 68 are connected to the output buffer circuit 53.

This output buffer circuit 53 is formed as a push-pull type, and the first and second output transistors 9
1, 92 and one output resistance element 93 are sequentially connected in series between a pair of power supply terminals 69, 70. A first differential output terminal 67 of the differential circuit 52 is connected to a base terminal of the first output transistor 91, and a second differential output terminal is connected to a base terminal of the second output transistor 92. 68 is connected via an AC extraction capacitor 94, and a bias terminal 85 of the regulator circuit 54 is also connected via a bias resistance element 95.

The output buffer circuit 53 having the above structure
Is provided with a power output terminal 96 at a connection point between the first and second output transistors 91 and 92, and a predetermined load circuit 98 to be driven is connected to the power output terminal 96 via one capacitor 97. Is connected.

However, the differential amplifier 51 of the present embodiment is different from the above-described differential amplifier 1 in that the connection point between the second output transistor 92 and the output resistance element 93 is connected to the first signal input terminal. 61 are connected by a wiring 99, and a high-frequency bypass capacitor 100 for bypassing a high frequency of 1 GHz or more is inserted into the wiring 99.

Since the capacitance value of the high-frequency bypass capacitor 100 and the resistance value of the output resistance element 93 are appropriately set, the signal between the emitter terminal of the first output transistor 91 and the collector terminal of the second output transistor 92 is obtained. The phases are substantially the same.

In the above-described configuration, when a pair of signals are input to the first and second signal input terminals 61 and 62, the differential amplifier 51 of the present embodiment responds to the difference between these signals. Voltage power can be output from a power output terminal 96 to an external load resistor 98.

That is, both ends of the first and second differential transistors 63 and 64 of the differential circuit 52 are connected to a pair of power terminals 6.
Since a voltage is applied from the first and second signal input terminals 61 and 62 to the first and second differential input terminals 61 and 62, a voltage is applied from the first and second differential resistance elements 65 and 66 and the like. When externally input to the base terminals of the active transistors 63 and 64 individually, they are connected to the connection midpoint between the first and second differential transistors 63 and 64 and the first and second differential resistance elements 65 and 66. At the first and second differential output terminals 67 and 68, a differential signal having a voltage corresponding to the difference between the pair of input signals is generated.

The first and second output transistors 91 and 92 of the output buffer circuit 53 to which these signals are individually input to the base terminal are connected to the power supply terminal 6 together with the output resistance element 93.
9 and 70, the power supply output terminal 96 provided at the midpoint of the connection between the first and second output transistors 91 and 92 has a load resistance 98 corresponding to the difference between a pair of input signals. The power of the output voltage is output.

At this time, a positive voltage is applied from the positive power supply terminal 69 to the load circuit 98 via the first output transistor 91, and the second output transistor 92 and the output resistance element 93 are connected from the load circuit 98. Since the voltage of the negative electrode can be drawn into the power terminal 70 grounded through the output terminal, the output buffer circuit 53 can supply the power corresponding to the input signal to the load circuit 98 by the push-pull operation.

At this time, the differential amplifier 51 of the present embodiment
Now, the second output transistor 92 and the output resistance element 93
Is connected to the first signal input terminal 61 via the high-frequency bypass capacitor 100, so that the signal phase of the emitter terminal of the second output transistor 92 precedes.

Therefore, even if the input signal becomes high frequency and the signal phase transmitted to the collector terminal is delayed due to the signal phase of the base terminal of the second output transistor 92, the emitter terminal of the first output transistor 91 will be delayed. Since the signal phase of the second output transistor 92 precedes the signal phase, as a result, the signal phases of the emitter terminal of the first output transistor 91 and the collector terminal of the second output transistor 92 become substantially the same, In this portion, the push-pull operation is maintained.

This will be described in detail below. First, as shown in FIG. 1 and FIG. 5, in the differential amplifiers 51 and 1 of the present embodiment and the conventional example, the output points of the power output terminals 96 and 46 are denoted by ′, the second output transistors 92 and 42
, The base point of ′, the emitter point of ′, and the input of the first signal input terminals 61 and 11.

Then, the output points of the power output terminals 96 and 46 with respect to the inputs of the first signal input terminals 61 and 11
FIG. 3 shows the phase relationship between ′ and the emitter points of the second output transistors 92 and 42 ′.

At this time, in the conventional differential amplifier 1,
The output of the differential circuit 2 which is input to the base point 'of the second output transistor 42 is also delayed because there is one more base-collector connection, so that the phase of the emitter point' of the second output transistor 42 is also the first. This delays the input of the signal input terminal 11.

However, in the differential amplifier 51 of the present embodiment, the input of the first signal input terminal 11 is connected to the second output transistor 9 via the high-frequency bypass capacitor 100.
Since the voltage is applied to the second emitter point, if the capacitance of the high-frequency bypass capacitor 100 is appropriate, the phase in the high-frequency region advances.

That is, as shown in FIG. 4, in the conventional differential amplifier 1, the time difference 出力 between the output point ′ of the power output terminal 46 and the emitter point ′ of the second output transistor 42.
T is very small. However, in the high frequency region, the power output terminal 46 is connected to the emitter point ′ of the second output transistor 42.
The phase is delayed due to the signal transmission time Tpd to the output point ′, and as a result, the push-pull operation at the output point ′ of the power output terminal 46 becomes difficult, and the gain decreases.

However, in the differential amplifier 51 of the present embodiment, because of the high-frequency bypass capacitor 100, the timing when the emitter point of the second output transistor 92 goes high is when the output point of the power output terminal 96 goes low. It precedes the timing by Δt.

Therefore, if the phase of the emitter point of the second output transistor 92 is advanced by the time Δt corresponding to the signal transmission time Tpd to the output point of the power output terminal 96, the output point of the power output terminal 96 can be changed. Is maintained and the gain does not decrease.

Therefore, in the differential amplifier 51 of the present embodiment, by appropriately setting the capacitance of the high-frequency bypass capacitor 100 as described above, the push-pull operation of the second output transistor 92 can be performed even in a desired high-frequency region. Can be maintained. For this reason, as shown in FIG. 2, it is possible to reduce a decrease in gain of the input signal in a high frequency region, and to drive the load circuit 98 with a good gain even in a high frequency region.

For example, the capacitance value C ₁ of the AC extraction capacitor 94 is 3 pF, and the resistance value R ₁ of the bias resistance element 95 is 3 kF.
Ω, when the resistance R ₂ of the output resistance element 93 is 115Ω,
The capacitance value C ₂ of the high-frequency bypass capacitor 100 is set to 0.7
With pF, as shown in FIG. 2, the gain at a frequency of 2 GHz can be improved by about 1.8 dB.

The present invention is not limited to the above-described embodiment, but allows various modifications without departing from the scope of the invention.

[0060]

Since the present invention is configured as described above, it has the following effects.

In the differential amplifier according to the first aspect of the present invention, when a pair of input signals are individually input to the first and second signal input terminals, the pair of differential signals are output from the first and second differential output terminals. And a push-pull output buffer circuit composed of a first and second output transistor and an output resistance element connected in series, and the first and second Differential output terminal is connected to the base terminal of the first and second output transistors of the output buffer circuit, and a power output terminal is provided at a connection midpoint of the first and second output transistors. The connection point between the second output transistor and the output resistance element and the first signal input terminal are connected via a high-frequency bypass capacitor, thereby being connected to the first signal input terminal. High frequency bike Since the signal phase of the emitter terminal of the second output transistor can be advanced by the capacitor, the signal phase of the collector terminal of the second output transistor can be changed even if the input signal has a high frequency. Since the phase can be substantially the same as the signal phase, it is possible to maintain the push-pull operation in this portion and reduce the decrease in gain of the input signal in a high frequency region.

According to a second aspect of the present invention, there is provided a differential amplifier comprising: a first signal input terminal to which a pair of signals are individually input;
These first and second signal input terminals are first and second differential transistors individually connected to respective base terminals, and first and second signal input terminals are individually connected to collector terminals of the first and second differential transistors. A second differential resistance element, and a first and second differential output terminal individually connected to a connection midpoint between the first and second differential resistance elements and the first and second differential transistors. ,
A pair of power supplies commonly connected to both ends of the first and second differential transistors via the first and second differential resistance elements, and an AC extraction capacitor connected to the second differential output terminal; A first output transistor in which one of the pair of power terminals is connected to a collector terminal and the first differential output terminal is connected to a base terminal; and an emitter terminal of the first output transistor is And a second differential output terminal connected to a collector terminal.
A second output transistor connected to the base terminal via the extraction capacitor, an output resistor element having the emitter terminal of the second output transistor connected to one end and the other of the power supply terminals connected to the other end, A regulator circuit connected to the base terminal of the second output transistor in parallel with the second differential output terminal to generate a DC bias; and a power connected to a connection midpoint of the first and second output transistors. An output terminal, a high-frequency bypass capacitor connected to the connection midpoint between the second output transistor and the output resistance element and the first signal input terminal, thereby providing a first signal. Since the signal phase of the emitter terminal of the second output transistor can be advanced by the high-frequency bypass capacitor connected to the input terminal, the input signal is high. Even if it becomes a wave, the signal phase of the collector terminal of the second output transistor can be made substantially the same phase as the signal phase of the emitter terminal of the first transistor. A decrease in gain in a high frequency region can be reduced.

The third aspect of the present invention is the first or second aspect.
The differential amplifier according to claim 1, wherein a resistance value of the output resistance element and the high-frequency bypass are set so that a signal phase between an emitter terminal of the first output transistor and a collector terminal of the second output transistor is substantially in phase. Even if the input signal has a high frequency and the signal phase transmitted to the collector terminal is delayed due to the signal phase of the base terminal of the second output transistor due to the setting of the capacitance value of the capacitor, the output resistance element And the capacitance value of the high-frequency bypass capacitor, the signal phase between the emitter terminal of the first output transistor and the collector terminal of the second output transistor can be made substantially in phase, so that the push-pull operation can be performed satisfactorily. Can be maintained.

According to a fourth aspect of the present invention, in the differential amplifier according to the third aspect, when the capacitance value of the high-frequency bypass capacitor is 1.0 pF or less, for example, the resistance value of the output resistance element is about If it is 100Ω, the gain in the frequency band of 1 GHz or more can be improved.

According to a fifth aspect of the present invention, in the differential amplifier according to the fourth aspect, the resistance value of the output resistance element is about 10%.
0 Ω, and the capacitance value of the high-frequency bypass capacitor is about 0.
With 7 pF, the gain in the frequency band of 1 GHz or more can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a differential amplifier according to an embodiment of the present invention.

FIG. 2 is a semilogarithmic graph showing frequency characteristics of the differential amplifier of the present embodiment and a conventional differential amplifier.

FIG. 3 is a semilogarithmic graph showing a phase relationship between respective parts of the differential amplifier of the present embodiment and a conventional differential amplifier.

FIG. 4 is a time chart showing signal waveforms at respective portions of the differential amplifier of the present embodiment and a differential amplifier of a conventional example.

FIG. 5 is a circuit diagram showing a conventional differential amplifier.

[Explanation of symbols]

 REFERENCE SIGNS LIST 51 differential amplifier 52 differential circuit 53 output buffer circuit 54 regulator circuit 61, 62 first and second signal input terminal 63, 64 first and second differential transistor 65, 66 first and second differential resistance element 67 , 68 first second differential output terminal 69, 70 power supply terminal 85 bias terminal 91, 92 first second output transistor 93 output resistance element 94 AC extraction capacitor 96 power output terminal 100 high frequency bypass capacitor

Continuation of front page (56) References JP-A-7-307625 (JP, A) JP-A-1-232806 (JP, A) JP-A-54-26649 (JP, A) JP-A-61-107804 (JP) JP-A-59-43613 (JP, A) JP-A-8-288811 (JP, A) JP-A-7-307623 (JP, A) JP-A-4-234209 (JP, A) 8-256024 (JP, A) JP-A-5-243861 (JP, A) JP-A-1-155521 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03F 3/30

Claims (5)

(57) [Claims] 1. A differential circuit that outputs a pair of differential signals from a first and second differential output terminals when a pair of input signals are individually input to a first and second signal input terminals. A push-pull output buffer circuit comprising a first and second output transistor and an output resistance element connected in sequence, wherein the first and second differential output terminals of the differential circuit are connected to the output buffer circuit. A differential amplifier connected to a base terminal of the first and second output transistors and having a power output terminal at a connection midpoint of the first and second output transistors, wherein the second output transistor and the output A differential amplifier, wherein a midpoint of connection with a resistance element and the first signal input terminal are connected via a high-frequency bypass capacitor. 2. A first and second signal input terminal to which a pair of signals are individually input, and a first and second signal input terminals respectively connected to the respective base terminals. The first and second differential resistance elements respectively connected to the collector terminals of the first and second differential transistors; the first and second differential resistance elements; and the first and second differential resistance elements. A first and second differential output terminal individually connected to a connection midpoint with the differential transistor; and an AC (Alternatin) terminal connected to the second differential output terminal.
g Current) an extraction capacitor; a pair of power terminals commonly connected to both ends of the first and second differential transistors via the first and second differential resistance elements; one of the pair of power terminals Is connected to a collector terminal and the first differential output terminal is connected to a base terminal; a first output transistor having an emitter terminal connected to a collector terminal; A second output transistor having a differential output terminal connected to the base terminal via the AC extraction capacitor, an emitter terminal of the second output transistor connected to one end, and the other end of the power supply terminal connected to the other end. An output resistance element connected to the base terminal of the second output transistor and a DC (Direct Curre
nt) a regulator circuit for generating a bias, a power output terminal connected to a connection midpoint of the first and second output transistors, and a connection midpoint between the second output transistor and the output resistance element. A high frequency bypass capacitor connected to one signal input terminal. 3. The resistance value of the output resistance element and the capacitance value of the high-frequency bypass capacitor such that the signal phases of the emitter terminal of the first output transistor and the collector terminal of the second output transistor are substantially in phase. 3. The differential amplifier according to claim 1, wherein 4. The differential amplifier according to claim 3, wherein the high-frequency bypass capacitor has a capacitance of 1.0 pF or less. 5. The resistance value of the output resistance element is about 100.
Ω, the capacitance value of the high-frequency bypass capacitor is about 0.7
5. The differential amplifier according to claim 4, wherein the differential amplifier is pF.