JPH07283350A - Packaging structure of semiconductor element - Google Patents

Packaging structure of semiconductor element

Info

Publication number
JPH07283350A
JPH07283350A JP6070537A JP7053794A JPH07283350A JP H07283350 A JPH07283350 A JP H07283350A JP 6070537 A JP6070537 A JP 6070537A JP 7053794 A JP7053794 A JP 7053794A JP H07283350 A JPH07283350 A JP H07283350A
Authority
JP
Japan
Prior art keywords
heat sink
semiconductor element
conductor
mounting
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6070537A
Other languages
Japanese (ja)
Inventor
Toshihiro Kimura
俊広 木村
Tomoyuki Yatsukawa
友志 八津川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP6070537A priority Critical patent/JPH07283350A/en
Publication of JPH07283350A publication Critical patent/JPH07283350A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48475Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48491Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being an additional member attached to the bonding area through an adhesive or solder, e.g. buffer pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PURPOSE:To achieve a high-density packaging, facilitate maintenance, and inspect a semiconductor device before packaging alone by efficiently releasing heat to a metal substrate with a metal base as a heat sink and at the same time mounting the semiconductor element to the metal substrate in advance in the form of a chip compactly. CONSTITUTION:A metal substrate 1 is laminated by a metal base 2, its thin part 2a, an insulation layer 5, a die pad 3, and a wiring layer 4, a semiconductor element 6 is die-bonded on the die pad 3 by solder 7, the electrode part is connected to the wiring layer 4 with a wire 8, and then the semiconductor 6 and the wire 8 are sealed by resin 9. In this manner, the chip semiconductor element 6 on the metal substrate 1 is packaged on a substrate 10 by providing a conductor 11 for mounting base and a printed conductor 12 on the surface of the substrate 10, joining the metal base 2 to the conductor 11 for mounting base, and connecting the wiring layer 4 to the printed conductor 12 in a simple packaging structure.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体素子の実装構造
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element mounting structure.

【0002】[0002]

【従来の技術】図12は、半導体素子の実装構造の第1
の従来例を示している。この従来例は、一般的なベアチ
ップ実装構造であり、半導体素子21がヒートシンク2
2にはんだ24で接合された後、ヒートシンク22の裏
面が基板23におけるヒートシンク取付用導体25には
んだ24で接合されている。半導体素子21の電極部
(図示せず)は基板23におけるプリント導体26にワ
イヤ27で電気的に接続されている。半導体素子21の
周囲を取り囲むようにダムリング28が基板23に接着
剤29で接合され、ダムリング28内には半導体素子2
1及びワイヤ27を保護する目的で封止樹脂30が注入
されている。
2. Description of the Related Art FIG. 12 shows a first mounting structure of a semiconductor device.
The conventional example of is shown. This conventional example has a general bare chip mounting structure, in which the semiconductor element 21 has a heat sink 2
After being soldered to the No. 2 solder 24, the back surface of the heat sink 22 is soldered to the heat sink mounting conductor 25 on the substrate 23. The electrode portion (not shown) of the semiconductor element 21 is electrically connected to the printed conductor 26 on the substrate 23 by the wire 27. A dam ring 28 is bonded to the substrate 23 with an adhesive 29 so as to surround the semiconductor element 21.
A sealing resin 30 is injected for the purpose of protecting the wire 1 and the wire 27.

【0003】また、図13は、半導体素子の実装構造の
第2の従来例を示している。この従来例は、半導体素子
をトランスファモールド法によりパッケージ化した後、
基板上に表面実装する実装構造であり、半導体素子21
がリードフレームの一部であるヒートシンク31上には
んだ24で接合されている。半導体素子21の電極部
(図示せず)はリード32にワイヤ27で電気的に接続
されいる。そして半導体素子21及びワイヤ27を保護
する目的で、トランスファモールド法により半導体素子
21及びワイヤ27等の部分が封止樹脂30で封止され
パッケージ化されている。パッケージ化された後、ヒー
トシンク31の裏面が基板23におけるヒートシンク取
付用導体25にはんだ24で接合され、リード32がプ
リント導体26にはんだ24で電気的に接続されてパッ
ケージが基板23上に表面実装されている。
FIG. 13 shows a second conventional example of a semiconductor element mounting structure. In this conventional example, after packaging the semiconductor element by the transfer molding method,
The semiconductor element 21 has a mounting structure that is surface-mounted on a substrate.
Are soldered onto the heat sink 31 which is a part of the lead frame. The electrode portion (not shown) of the semiconductor element 21 is electrically connected to the lead 32 by the wire 27. Then, in order to protect the semiconductor element 21 and the wire 27, the semiconductor element 21 and the wire 27 and the like are packaged by sealing with a sealing resin 30 by a transfer molding method. After being packaged, the back surface of the heat sink 31 is joined to the heat sink mounting conductor 25 on the substrate 23 by the solder 24, the leads 32 are electrically connected to the printed conductor 26 by the solder 24, and the package is surface-mounted on the substrate 23. Has been done.

【0004】[0004]

【発明が解決しようとする課題】第1の従来例では、ベ
アチップ実装のため、比較的高密度に実装できるが、半
導体素子は基板と一体に樹脂封止されているため、実装
後のリペア性が悪く、また素子単体での電気的な検査が
不可能であり、さらには部品点数が多く、部品コスト、
製造コストが高くなるという問題があった。
In the first conventional example, bare chip mounting allows relatively high-density mounting, but since the semiconductor element is resin-sealed integrally with the substrate, repairability after mounting is improved. Is poor, and it is not possible to perform an electrical test on the element alone. Furthermore, the number of parts is large, the parts cost,
There is a problem that the manufacturing cost becomes high.

【0005】また、第2の従来例は、リードフレームに
パッケージ化しているため、重量が重く、形状が大きく
なるので高密度実装が難しく、またトランスファモール
ド装置等の高価な設備が必要で、多品種少量生産には不
向きであり、少量生産の場合は金型の償却費等がかさん
で製造コストが高くつくという問題があった。
In the second conventional example, since it is packaged in the lead frame, the weight is heavy and the shape is large, so that high density mounting is difficult, and expensive equipment such as a transfer mold device is required, which is often used. It is not suitable for small-lot production of various varieties, and in the case of small-lot production, there is a problem that the depreciation costs of molds are expensive and the manufacturing cost is high.

【0006】本発明は、このような従来の問題点に着目
してなされたもので、放熱性が高く従来のベアチップ実
装並みの高密度実装が可能であり、実装後のリペア性が
良好で、アッセンブリ後の素子単体での電気的な検査が
可能であり、さらにはコスト低減を図ることのできる半
導体素子の実装構造を提供することを目的とする。
The present invention has been made by paying attention to such conventional problems. It has high heat dissipation and enables high-density mounting similar to conventional bare chip mounting, and has good repairability after mounting. It is an object of the present invention to provide a mounting structure for a semiconductor element, which enables electrical inspection of the element after assembly and further enables cost reduction.

【0007】[0007]

【課題を解決するための手段】上記課題を解決するため
に、本発明は、第1に、ヒートシンクとなる肉厚の金属
ベースの周囲に肉薄部を有し前記金属ベースの表面には
ダイパッドが絶縁形成されるとともに該金属ベースの表
面から前記肉薄部の表面にかけて配線層が絶縁形成され
前記肉薄部は折り返し端部における前記配線層の表面が
前記金属ベースの裏面と略同一面となるように折り返さ
れた金属基板と、前記ダイパッド上にダイボンディング
され電極部が前記配線層に適宜に接続された半導体素子
と、ベース取付用導体及びプリント導体を備え前記ベー
ス取付用導体に前記金属ベースがはんだ接合されるとと
もに前記プリント導体には前記折り返し端部における前
記配線層がはんだ接続された基板とを有することを要旨
とする。
In order to solve the above-mentioned problems, according to the present invention, firstly, there is a thin portion around a thick metal base serving as a heat sink, and a die pad is provided on the surface of the metal base. Insulation is formed and a wiring layer is formed from the surface of the metal base to the surface of the thin portion such that the surface of the wiring layer at the folded-back end is substantially flush with the back surface of the metal base. The folded metal substrate, a semiconductor element that is die-bonded on the die pad and has an electrode portion appropriately connected to the wiring layer, a base mounting conductor and a printed conductor, and the metal base is soldered to the base mounting conductor. The gist is that the printed conductor has a substrate to which the wiring layer at the folded-back end is soldered and is joined.

【0008】第2に、函型のヒートシンクと、該ヒート
シンクの内底部にダイボンディングされて樹脂封止され
るとともに電極部に接続されたボンディングパッドが前
記樹脂封止から露出した半導体素子と、ヒートシンク取
付用導体及びプリント導体を備え前記ヒートシンク取付
用導体に前記ヒートシンクの裏面がはんだ接合されると
ともに前記プリント導体にはワイヤを介して前記ボンデ
ィングパッドが接続された基板とを有することを要旨と
する。
Second, a box-shaped heat sink, a semiconductor element that is die-bonded to the inner bottom portion of the heat sink and resin-sealed, and a bonding pad connected to an electrode portion is exposed from the resin sealing, and a heat sink. It is a gist to have a board provided with a mounting conductor and a printed conductor, the back surface of the heat sink being soldered to the heat sink mounting conductor, and the printed conductor being connected to the bonding pad via a wire.

【0009】第3に、函型のヒートシンクと、該ヒート
シンクの内底部にダイボンディングされて樹脂封止され
るとともに電極部に接続されたボンディングパッドが前
記樹脂封止から露出した半導体素子と、ヒートシンク取
付用導体及びプリント導体を備え該プリント導体に前記
ボンディングパッドがはんだ接続されるとともに前記ヒ
ートシンク取付用導体に前記ヒートシンクの周囲端面が
はんだ接合された基板とを有することを要旨とする。
Thirdly, a box-shaped heat sink, a semiconductor element which is die-bonded to the inner bottom portion of the heat sink and is resin-sealed, and a bonding pad connected to an electrode portion is exposed from the resin-sealing, and a heat sink. A gist of the present invention is to have a board having an attachment conductor and a printed conductor, the bonding pad being soldered to the printed conductor, and the peripheral end surface of the heat sink being soldered to the heat sink attachment conductor.

【0010】[0010]

【作用】上記構成において、第1に、半導体素子で発生
した熱は金属ベースがヒートシンクとして機能し効率的
に基板へ放熱される。半導体素子は金属基板に予め搭載
されて小型コンパクトにチップキャリア化され、上記の
ように放熱性の良いことからベアチップ実装並みの高密
度実装が可能となる。また、チップキャリア化されるこ
とで基板からのリペア性が良好となり、基板への実装前
に半導体素子を単体で電気的な検査をすることが可能と
なる。
In the above structure, firstly, the heat generated in the semiconductor element is efficiently radiated to the substrate because the metal base functions as a heat sink. The semiconductor element is preliminarily mounted on the metal substrate and is made into a small and compact chip carrier. Since the heat dissipation is good as described above, high-density mounting comparable to bare chip mounting becomes possible. Further, since the chip carrier is used, the repairability from the substrate is improved, and it becomes possible to electrically test the semiconductor element by itself before mounting on the substrate.

【0011】第2に、半導体素子で発生した熱はヒート
シンクを介して効率的に基板へ放熱される。半導体素子
はヒートシンク内に予め搭載されて小型コンパクトにチ
ップキャリア化され、上記のように放熱性の良いことか
らベアチップ並みの高密度実装が可能となる。また、チ
ップキャリア化されることで基板からのリペア性が良好
となり、基板への実装前の半導体素子単体での電気的な
検査は、ボンディングパッドが樹脂封止から露出してい
ることで極めて容易に行い易くなる。
Secondly, the heat generated in the semiconductor element is efficiently radiated to the substrate via the heat sink. The semiconductor element is preliminarily mounted in the heat sink and is made into a small and compact chip carrier. Since the heat dissipation is good as described above, high density mounting comparable to a bare chip is possible. In addition, since it is made into a chip carrier, the repairability from the board becomes good, and the electrical inspection of the semiconductor element alone before mounting on the board is extremely easy because the bonding pad is exposed from the resin seal. Easier to do.

【0012】第3に、ヒートシンク内に予め搭載され、
小型コンパクトにチップキャリア化された半導体素子
が、基板にフェイスダウンで実装されるので極めてシン
プルな実装構造となり、放熱性が良好となるとともにベ
アチップ実装並みの高密度実装が可能となる。その他、
実装後の基板からのリペア性、半導体素子単体での電気
的な検査容易性等、第2の発明と同様の作用が得られ
る。
Thirdly, it is pre-mounted in the heat sink,
Since the semiconductor element, which is made into a small and compact chip carrier, is mounted face down on the substrate, it has an extremely simple mounting structure, which improves heat dissipation and enables high-density mounting comparable to bare chip mounting. Other,
The same effects as those of the second invention can be obtained, such as repairability from the substrate after mounting and easiness of electrical inspection of the semiconductor element alone.

【0013】[0013]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。図1乃至図5は、本発明の第1実施例を示す図で
ある。まず、図2乃至図5を用いて金属基板の構造及び
金属基板上への半導体素子の搭載から説明する。金属基
板1は、銅、アルミ、鉄等の金属によりヒートシンクと
なる肉厚の金属ベース2の周囲に肉薄部2aが形成さ
れ、この金属ベース2及び肉薄部2aの表面全体にエポ
キシ、シリコーン、ポリイミド、ガラスエポキシ等から
なる絶縁層5が形成されている。金属ベース2上に相当
する絶縁層5の上にはダイパッド3が形成され、金属ベ
ース2の周囲部から肉薄部2a上に相当する絶縁層5の
上には適宜にパターン化された配線層4が形成されてい
る。このように金属基板1は、金属ベース2及び肉薄部
2aの金属、絶縁層5、ダイパッド3及び配線層4の金
属箔でラミネート構造となっている。絶縁層5は厚みが
百μm程度に薄く形成され、ダイパッド3及び配線層4
は銅箔で形成されている。このような材料で薄く形成さ
れた肉薄部2aの部分は折り曲げが可能となっており、
図2に示すように、折り返し端部における配線層4の表
面が金属ベース2の裏面と略同一面となるように、断面
U字状に折り返されている。そして、このように形成さ
れた金属基板1におけるダイパッド3上に、はんだ7の
接着により半導体素子6がダイボンディングされ、その
電極部(図示せず)が配線層4にワイヤ8で電気的に接
続されている。半導体素子6とワイヤ8等は外部環境か
ら保護する目的で封止樹脂9で封止されている。粘度が
高くチキン性の高樹脂の場合は、ガードリング等がなく
てもボンディング方法等により、図示のように封止可能
である。上述の場合は、肉薄部2aを折り返してチップ
キャリア状にした金属基板1に半導体素子6をアッセン
ブリする場合を示しているが、図4、図5に示すよう
に、折り返し前の金属基板1に半導体素子6を搭載しワ
イヤ接続を行ったのちに、肉薄部2aを折り返すような
工程をとってもよい。
Embodiments of the present invention will be described below with reference to the drawings. 1 to 5 are views showing a first embodiment of the present invention. First, the structure of the metal substrate and mounting of the semiconductor element on the metal substrate will be described with reference to FIGS. In the metal substrate 1, a thin portion 2a is formed around a thick metal base 2 serving as a heat sink by a metal such as copper, aluminum or iron, and epoxy, silicone, polyimide An insulating layer 5 made of glass epoxy or the like is formed. The die pad 3 is formed on the insulating layer 5 corresponding to the metal base 2, and the appropriately patterned wiring layer 4 is formed on the insulating layer 5 corresponding to the thin portion 2a from the peripheral portion of the metal base 2. Are formed. In this way, the metal substrate 1 has a laminated structure of the metal base 2, the metal of the thin portion 2a, the insulating layer 5, the die pad 3, and the metal foil of the wiring layer 4. The insulating layer 5 is thinly formed to have a thickness of about 100 μm, and the die pad 3 and the wiring layer 4 are formed.
Is made of copper foil. The thin portion 2a formed thinly with such a material can be bent,
As shown in FIG. 2, the wiring layer 4 is folded back in a U-shape in cross section so that the front surface of the wiring layer 4 at the folded back end is substantially flush with the back surface of the metal base 2. Then, the semiconductor element 6 is die-bonded onto the die pad 3 of the metal substrate 1 thus formed by bonding the solder 7, and its electrode portion (not shown) is electrically connected to the wiring layer 4 by the wire 8. Has been done. The semiconductor element 6, the wire 8 and the like are sealed with a sealing resin 9 for the purpose of protecting from the external environment. If the resin has a high viscosity and a high chicken property, it can be sealed as shown by a bonding method or the like without a guard ring or the like. In the case described above, the thin portion 2a is folded back to assemble the semiconductor element 6 on the metal substrate 1 in the shape of a chip carrier. However, as shown in FIGS. After mounting the semiconductor element 6 and performing wire connection, a step of folding back the thin portion 2a may be taken.

【0014】図1は、上述のように金属基板1にチップ
キャリア化された半導体素子6の基板10への実装構造
を示している。基板10の表面にはベース取付用導体1
1及び適宜にパターン化されたプリント導体12が備え
られ、ベース取付用導体11には金属ベース2がはんだ
13で接合され、プリント導体12には折り返し端部に
おける配線層4がはんだ13で電気的に接続されてい
る。
FIG. 1 shows a mounting structure on a substrate 10 of a semiconductor element 6 which is formed into a chip carrier on the metal substrate 1 as described above. The base mounting conductor 1 is provided on the surface of the substrate 10.
1 and an appropriately patterned printed conductor 12 are provided, the metal base 2 is joined to the base mounting conductor 11 by solder 13, and the wiring layer 4 at the folded back end is electrically connected to the printed conductor 12 by solder 13. It is connected to the.

【0015】次に、上述のように構成された半導体素子
の実装構造の作用を説明する。半導体素子6で発生した
熱は、金属ベース2がヒートシンクとして機能し、効率
的に基板10へ放熱される。半導体素子6を金属基板1
に予め搭載し、チップキャリア化することで、リペア時
に基板10から容易に取り外すことが可能であり、且つ
基板10への実装前にチップキャリア化された半導体素
子6を単体でプリ検査やバーインといったスクリーニン
グ工程を実施することが可能となる。実装密度は従来の
ベアチップ実装並みの高密度化が可能であり、実装に際
しては、金型やトランスファモールド装置等の高価な設
備が不要となって製造コストを安価にすることが可能で
ある。また金属基板1のパターン変更等により、チップ
サイズ、半導体素子の端子数等に左右されずに対応する
ことができ、設計から製造までのTAT(Turn Around
Time)も従来のパッケージ(トランスファモールド)に
比べ、金型設計、製造に要する時間が不要となって著し
く早くできる。
Next, the operation of the semiconductor element mounting structure configured as described above will be described. The metal base 2 functions as a heat sink, and the heat generated in the semiconductor element 6 is efficiently radiated to the substrate 10. Semiconductor element 6 on metal substrate 1
It is possible to easily remove it from the substrate 10 at the time of repair by mounting it in advance and making it into a chip carrier, and to perform the pre-inspection or burn-in of the semiconductor device 6 that has been made into a chip carrier by itself before mounting on the substrate 10. It becomes possible to carry out the screening step. The packaging density can be as high as that of the conventional bare chip packaging, and at the time of packaging, expensive equipment such as a mold and a transfer molding device is not required, and the manufacturing cost can be reduced. In addition, by changing the pattern of the metal substrate 1 etc., it is possible to respond without being influenced by the chip size, the number of terminals of the semiconductor element, etc., and TAT (Turn Around) from design to manufacturing.
Compared with the conventional package (transfer mold), the time required for mold design and manufacturing is also unnecessary and can be made significantly faster.

【0016】図6、図7は、金属基板1の部分の変形例
をそれぞれ示している。図6の例は、肉薄部2aの折り
曲げ形状を断面コ字状(直角曲げ)にして絶縁層5の絶
縁不良の発生を考慮したものである。図7の例は、金属
ベース2の表面部に凹部2bを設け、この凹部2bの部
分に半導体素子をダイボンディングし、封止樹脂9の形
成を容易にしている。粘度が低くチキン性の少ない封止
樹脂9を用いる場合は、このように凹部2bを設けて封
止樹脂9をポッティングするとよい。
FIG. 6 and FIG. 7 respectively show modifications of the portion of the metal substrate 1. In the example of FIG. 6, the bent shape of the thin portion 2a is U-shaped in section (bent at right angles) in consideration of occurrence of insulation failure of the insulating layer 5. In the example of FIG. 7, a recess 2b is provided on the surface of the metal base 2, and a semiconductor element is die-bonded to the recess 2b to facilitate the formation of the sealing resin 9. When the sealing resin 9 having a low viscosity and a low chicken property is used, it is advisable to form the recess 2b and pot the sealing resin 9 as described above.

【0017】図8乃至図10には、本発明の第2実施例
を示す。本実施例では、図8、図9に示すように、ヒー
トシンク14が函型に形成され、このヒートシンク14
の内底部に、はんだ7の接着により半導体素子6がダイ
ボンディングされ、その各電極部(図示せず)にボンデ
ィングパッド15がはんだ7で接続されている。ヒート
シンク14の凹部には半導体素子6を外部環境から保護
する目的で封止樹脂9が充填されている。ボンディング
パッド15は半導体素子6上の電極膜に比べて十分に厚
く形成されており、その上部が封止樹脂9から露出して
いる。
8 to 10 show a second embodiment of the present invention. In this embodiment, as shown in FIGS. 8 and 9, the heat sink 14 is formed in a box shape.
The semiconductor element 6 is die-bonded to the inner bottom of the substrate by bonding the solder 7, and the bonding pads 15 are connected to the respective electrode portions (not shown) by the solder 7. The concave portion of the heat sink 14 is filled with the sealing resin 9 for the purpose of protecting the semiconductor element 6 from the external environment. The bonding pad 15 is formed sufficiently thicker than the electrode film on the semiconductor element 6, and its upper portion is exposed from the sealing resin 9.

【0018】図10は、このようにヒートシンク14に
チップキャリア化された半導体素子6の基板10への実
装構造を示している。基板10の表面にはヒートシンク
取付用導体11a及び適宜にパターン化されたプリント
導体12が備えられ、ヒートシンク取付用導体11aに
はヒートシンク14の裏面がはんだ13で接合され、プ
リント導体12にはワイヤ8を介してボンディングパッ
ド15が接続されている。
FIG. 10 shows a mounting structure of the semiconductor element 6 thus formed into a chip carrier on the heat sink 14 on the substrate 10. A heat sink mounting conductor 11a and an appropriately patterned printed conductor 12 are provided on the front surface of the substrate 10, the back surface of the heat sink 14 is joined to the heat sink mounting conductor 11a with solder 13, and the printed conductor 12 is connected to the wire 8. The bonding pad 15 is connected via.

【0019】次に、上述のように構成された半導体素子
の実装構造の作用を説明する。半導体素子6で発生した
熱はヒートシンク14を介して効率的に基板10へ放熱
される。半導体素子6をヒートシンク14内に搭載して
チップキャリア化し、必要な電極部はボンディングパッ
ド15で封止樹脂9から露出させているため、基板10
への実装前に半導体素子6を単体でプリ検査やバーイン
といったスクリーニング工程を実施することが可能とな
る。ボンディングパッド15へは直接何回でもプロービ
ングすることができるので特に電気的な検査は行い易
い。基板10への実装後のリペアについても、はんだを
溶融することで容易に行うことが可能である。実装密度
は従来のベアチップ実装並みの高密度化が可能であり、
実装に際しては、金型やトランスファモールド装置等の
高価な設備が不要で製造コスト及び材料コストが安価で
ある。ヒートシンク14へ搭載できる半導体素子6のチ
ップサイズ、厚み等には制限はないが、電極部には、は
んだ接続でボンディングパッド15を設けているため、
トランジスタやダイオード等の電極数の少ない半導体素
子の方が適用し易い。半導体素子の電極上にはんだ着け
によりボンディングパッド(金属パッド)を接続するこ
とはフリップチップ等で以前から行われており、既存の
技術で可能である。なお、本実施例では、ボンディング
パッドを用いているが、スタッドバンプやはんだバンプ
のような突起電極を用いることもできる。
Next, the operation of the semiconductor element mounting structure configured as described above will be described. The heat generated in the semiconductor element 6 is efficiently radiated to the substrate 10 via the heat sink 14. Since the semiconductor element 6 is mounted in the heat sink 14 to form a chip carrier, and the necessary electrode portions are exposed from the sealing resin 9 by the bonding pad 15, the substrate 10
It is possible to carry out a screening process such as pre-inspection or burn-in of the semiconductor element 6 alone before mounting on the semiconductor device 6. Since the bonding pad 15 can be directly probed any number of times, an electrical test is particularly easy to perform. The repair after mounting on the substrate 10 can be easily performed by melting the solder. Mounting density can be as high as conventional bare chip mounting,
At the time of mounting, expensive equipment such as a mold and a transfer molding device is not required, and the manufacturing cost and material cost are low. There are no restrictions on the chip size, thickness, etc. of the semiconductor element 6 that can be mounted on the heat sink 14, but since the bonding pad 15 is provided on the electrode portion by solder connection,
A semiconductor element such as a transistor or a diode having a small number of electrodes is easier to apply. Connecting the bonding pad (metal pad) to the electrode of the semiconductor element by soldering has been performed for a long time by flip chip or the like, and can be performed by the existing technology. Although the bonding pad is used in this embodiment, a protruding electrode such as a stud bump or a solder bump can be used.

【0020】図11には、本発明の第3実施例を示す。
函型のヒートシンク14に半導体素子6を搭載し、封止
樹脂9を充填してチップキャリア化するまでは、第2実
施例と同様である。図11は、このようなチップキャリ
ア化された半導体素子6の基板10への実装構造を示し
ている。基板10の表面にはヒートシンク取付用導体1
1b及び適宜にパターン化されたプリント導体12が備
えられ、このような基板10に対し、フリップチップ実
装等のように、半導体素子6がフェイスダウンで実装さ
れている。即ち、プリント導体12にはボンディングパ
ッド15が直接、はんだ13で接続され、ヒートシンク
取付用導体11bにはヒートシンク14の周囲端面部が
はんだ13で接合されている。
FIG. 11 shows a third embodiment of the present invention.
It is the same as the second embodiment until the semiconductor element 6 is mounted on the box-shaped heat sink 14 and the sealing resin 9 is filled to form a chip carrier. FIG. 11 shows a mounting structure of such a chip carrier semiconductor element 6 on a substrate 10. On the surface of the substrate 10, a heat sink mounting conductor 1
1b and an appropriately patterned printed conductor 12 are provided, and a semiconductor element 6 is mounted face down on such a substrate 10 as in flip chip mounting. That is, the bonding pad 15 is directly connected to the printed conductor 12 by the solder 13, and the peripheral end face portion of the heat sink 14 is joined by the solder 13 to the heat sink mounting conductor 11b.

【0021】本実施例は、このように構造がシンプルで
基板10に半導体素子6を高密度に実装可能であるとと
もに、放熱性の優れた実装構造が実現されている。その
他に、本実施例は、第2実施例と略同様の作用、効果を
奏する。
In this embodiment, as described above, the structure is simple, the semiconductor elements 6 can be mounted on the substrate 10 at a high density, and a mounting structure excellent in heat dissipation is realized. In addition, the present embodiment has substantially the same actions and effects as the second embodiment.

【0022】[0022]

【発明の効果】以上説明したように、各請求項記載の発
明によれば、それぞれ次のような効果を奏する。
As described above, according to the invention described in each claim, the following effects are obtained.

【0023】請求項1記載の発明によれば、ヒートシン
クとなる肉厚の金属ベースの周囲に肉薄部を有し前記金
属ベースの表面にはダイパッドが絶縁形成されるととも
に該金属ベースの表面から前記肉薄部の表面にかけて配
線層が絶縁形成され前記肉薄部は折り返し端部における
前記配線層の表面が前記金属ベースの裏面と略同一面と
なるように折り返された金属基板と、前記ダイパッド上
にダイボンディングされ電極部が前記配線層に適宜に接
続された半導体素子と、ベース取付用導体及びプリント
導体を備え前記ベース取付用導体に前記金属ベースがは
んだ接合されるとともに前記プリント導体には前記折り
返し端部における前記配線層がはんだ接続された基板と
を具備させたため、放熱性が良好で半導体素子は金属基
板に予め搭載されて小型コンパクトにチップキャリア化
されることからベアチップ実装並みの高密度実装を実現
することができる。またチップキャリア化されることで
実装後の基板からのリペア性が良好となり、基板への実
装前に半導体素子単体での電気的な検査を容易に行うこ
とができる。さらに実装に際しては、金型やトランスフ
ァモールド装置等の高価な設備が不要となって製造コス
トを低減することができる。
According to the first aspect of the invention, a thin metal base serving as a heat sink has a thin portion around the metal base, and a die pad is formed on the surface of the metal base so as to be insulated from the surface of the metal base. A wiring layer is formed so as to extend over the surface of the thin portion, and the thin portion is folded back so that the surface of the wiring layer at the folded end is substantially flush with the back surface of the metal base, and a die on the die pad. A semiconductor element, which is bonded and whose electrode portion is appropriately connected to the wiring layer, is provided with a base mounting conductor and a printed conductor, the metal base is soldered to the base mounting conductor, and the printed conductor has the folded end. Since the wiring layer in the section is provided with a substrate to which solder connection is made, the heat dissipation is good and the semiconductor element is pre-mounted on the metal substrate. It is possible to realize high-density mounting of bare chip mounting comparable from being chip carrier into a compact size. Further, since the chip carrier is used, the repairability from the substrate after mounting is improved, and the electrical inspection of the semiconductor element alone can be easily performed before mounting on the substrate. Further, when mounting, expensive equipment such as a mold and a transfer molding device is not required, and the manufacturing cost can be reduced.

【0024】請求項2記載の発明によれば、函型のヒー
トシンクと、該ヒートシンクの内底部にダイボンディン
グされて樹脂封止されるとともに電極部に接続されたボ
ンディングパッドが前記樹脂封止から露出した半導体素
子と、ヒートシンク取付用導体及びプリント導体を備え
前記ヒートシンク取付用導体に前記ヒートシンクの裏面
がはんだ接合されるとともに前記プリント導体にはワイ
ヤを介して前記ボンディングパッドが接続された基板と
を具備させたため、請求項1記載の発明の効果に加えて
さらに、アッセンブリ後、基板への実装前の半導体素子
単体での電気的な検査は、ボンディングパッドが樹脂封
止から露出しているので一層行い易くなる。
According to the second aspect of the present invention, the box-shaped heat sink and the bonding pad that is die-bonded to the inner bottom portion of the heat sink and resin-sealed and is connected to the electrode portion are exposed from the resin-sealing. And a substrate having a heat sink mounting conductor and a printed conductor, the back surface of the heat sink being soldered to the heat sink mounting conductor, and the bonding pad being connected to the printed conductor via a wire. Therefore, in addition to the effect of the invention of claim 1, an electrical inspection of the semiconductor element alone after assembly and before mounting on the substrate is further performed because the bonding pad is exposed from the resin sealing. It will be easier.

【0025】請求項3記載の発明によれば、函型のヒー
トシンクと、該ヒートシンクの内底部にボンディングさ
れて樹脂封止されるとともに電極部に接続されたボンデ
ィングパッドが前記樹脂封止から露出した半導体素子
と、ヒートシンク取付用導体及びプリント導体を備え該
プリント導体に前記ボンディングパッドがはんだ接続さ
れるとともに前記ヒートシンク取付用導体に前記ヒート
シンクの周囲端面がはんだ接合された基板とを具備させ
たため、請求項2記載の発明の効果に加えてさらに、ヒ
ートシンク内に予め搭載され、小型コンパクトにチップ
キャリア化された半導体素子が基板にフェイスダウンで
実装されるので実装構造が極めてシンプルになるととも
に放熱性を一層高めることができる。また部品点数が少
なく材料コストを低減することができる。
According to the third aspect of the present invention, the box-shaped heat sink and the bonding pad bonded to the inner bottom portion of the heat sink and sealed with resin and connected to the electrode portion are exposed from the resin seal. Since the semiconductor element and the heat sink mounting conductor and the printed conductor are provided, the bonding pad is soldered to the printed conductor, and the peripheral end face of the heat sink is solder-bonded to the heat sink mounting conductor, In addition to the effect of the invention described in Item 2, in addition, since the semiconductor element which is preliminarily mounted in the heat sink and which is made into a small and compact chip carrier is mounted face down on the substrate, the mounting structure is extremely simple and the heat dissipation is improved. It can be further enhanced. Further, the number of parts is small and the material cost can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る半導体素子の実装構造の第1実施
例を示す構成図である。
FIG. 1 is a configuration diagram showing a first embodiment of a mounting structure of a semiconductor device according to the present invention.

【図2】上記第1実施例において金属基板への半導体素
子の搭載状態を示す構成図である。
FIG. 2 is a configuration diagram showing a mounting state of a semiconductor element on a metal substrate in the first embodiment.

【図3】樹脂封止部分を除いた図2の斜視図である。FIG. 3 is a perspective view of FIG. 2 excluding a resin sealing portion.

【図4】上記第1実施例において金属基板に半導体素子
を搭載後、肉薄部を折り返す工程を説明するための図で
ある。
FIG. 4 is a view for explaining the step of folding back the thin portion after mounting the semiconductor element on the metal substrate in the first embodiment.

【図5】図4の平面図である。FIG. 5 is a plan view of FIG.

【図6】上記第1実施例の第1の変形例を示す構成図で
ある。
FIG. 6 is a configuration diagram showing a first modification of the first embodiment.

【図7】上記第1実施例の第2の変形例を示す構成図で
ある。
FIG. 7 is a configuration diagram showing a second modification of the first embodiment.

【図8】本発明の第2実施例においてヒートシンクへの
半導体素子の搭載状態を示す構成図である。
FIG. 8 is a configuration diagram showing a mounting state of a semiconductor element on a heat sink in the second embodiment of the present invention.

【図9】図8の斜視図である。9 is a perspective view of FIG. 8. FIG.

【図10】本発明の第2実施例を示す構成図である。FIG. 10 is a configuration diagram showing a second embodiment of the present invention.

【図11】本発明の第3実施例を示す構成図である。FIG. 11 is a configuration diagram showing a third embodiment of the present invention.

【図12】半導体素子の実装構造の第1の従来例を示す
構成図である。
FIG. 12 is a configuration diagram showing a first conventional example of a semiconductor element mounting structure.

【図13】第2の従来例を示す構成図である。FIG. 13 is a configuration diagram showing a second conventional example.

【符号の説明】[Explanation of symbols]

1 金属基板 2 金属ベース 2a 肉薄部 3 ダイパッド 4 配線層 5 絶縁層 6 半導体素子 7,13 はんだ 8 ワイヤ 9 封止樹脂 10 基板 11 ベース取付用導体 11a,11b ヒートシンク取付用導体 12 プリント導体 14 ヒートシンク 15 ボンディングパッド DESCRIPTION OF SYMBOLS 1 Metal substrate 2 Metal base 2a Thin part 3 Die pad 4 Wiring layer 5 Insulating layer 6 Semiconductor element 7,13 Solder 8 Wire 9 Sealing resin 10 Substrate 11 Base mounting conductor 11a, 11b Heat sink mounting conductor 12 Print conductor 14 Heat sink 15 Bonding pad

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 ヒートシンクとなる肉厚の金属ベースの
周囲に肉薄部を有し前記金属ベースの表面にはダイパッ
ドが絶縁形成されるとともに該金属ベースの表面から前
記肉薄部の表面にかけて配線層が絶縁形成され前記肉薄
部は折り返し端部における前記配線層の表面が前記金属
ベースの裏面と略同一面となるように折り返された金属
基板と、前記ダイパッド上にダイボンディングされ電極
部が前記配線層に適宜に接続された半導体素子と、ベー
ス取付用導体及びプリント導体を備え前記ベース取付用
導体に前記金属ベースがはんだ接合されるとともに前記
プリント導体には前記折り返し端部における前記配線層
がはんだ接続された基板とを有することを特徴とする半
導体素子の実装構造。
1. A thin metal base serving as a heat sink has a thin portion around the metal base, a die pad is formed on the surface of the metal base, and a wiring layer extends from the surface of the metal base to the surface of the thin portion. The thinned portion is insulated and folded back so that the front surface of the wiring layer at the folded back end is substantially flush with the back surface of the metal base; and the electrode portion is die-bonded on the die pad to form the wiring layer. A semiconductor element appropriately connected to the base mounting conductor and a printed conductor, the metal base is soldered to the base mounting conductor, and the printed conductor is soldered to the wiring layer at the folded end. And a mounted substrate for a semiconductor device.
【請求項2】 函型のヒートシンクと、該ヒートシンク
の内底部にダイボンディングされて樹脂封止されるとと
もに電極部に接続されたボンディングパッドが前記樹脂
封止から露出した半導体素子と、ヒートシンク取付用導
体及びプリント導体を備え前記ヒートシンク取付用導体
に前記ヒートシンクの裏面がはんだ接合されるとともに
前記プリント導体にはワイヤを介して前記ボンディング
パッドが接続された基板とを有することを特徴とする半
導体素子の実装構造。
2. A box-shaped heat sink, a semiconductor element which is die-bonded to the inner bottom portion of the heat sink and is resin-sealed, and a bonding pad connected to an electrode portion is exposed from the resin-sealing, and a heat sink mounting member. A semiconductor element comprising a conductor and a printed conductor, the back surface of the heat sink being soldered to the heat sink mounting conductor, and the printed conductor being connected to the bonding pad via a wire. Mounting structure.
【請求項3】 函型のヒートシンクと、該ヒートシンク
の内底部にダイボンディングされて樹脂封止されるとと
もに電極部に接続されたボンディングパッドが前記樹脂
封止から露出した半導体素子と、ヒートシンク取付用導
体及びプリント導体を備え該プリント導体に前記ボンデ
ィングパッドがはんだ接続されるとともに前記ヒートシ
ンク取付用導体に前記ヒートシンクの周囲端面がはんだ
接合された基板とを有することを特徴とする半導体素子
の実装構造。
3. A box-shaped heat sink, a semiconductor element that is die-bonded to the inner bottom of the heat sink and sealed with resin, and a bonding pad connected to an electrode portion is exposed from the resin sealing, and a heat sink mounting member. A mounting structure for a semiconductor device, comprising: a conductor and a printed conductor; and the bonding pad soldered to the printed conductor, and a substrate to which a peripheral end face of the heat sink is solder-bonded to the heat sink mounting conductor.
JP6070537A 1994-04-08 1994-04-08 Packaging structure of semiconductor element Pending JPH07283350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6070537A JPH07283350A (en) 1994-04-08 1994-04-08 Packaging structure of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6070537A JPH07283350A (en) 1994-04-08 1994-04-08 Packaging structure of semiconductor element

Publications (1)

Publication Number Publication Date
JPH07283350A true JPH07283350A (en) 1995-10-27

Family

ID=13434390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6070537A Pending JPH07283350A (en) 1994-04-08 1994-04-08 Packaging structure of semiconductor element

Country Status (1)

Country Link
JP (1) JPH07283350A (en)

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