JPH07281655A - Video signal generating circuit - Google Patents

Abstract

PURPOSE:To facilitate synchronization between vertical- and horizontal- synchronizing signals and video data which a video signal generating circuit generates and to simplify the circuit. CONSTITUTION:Synchronism information of vertical- and horizontal- synchronizing signals and video data are stored in the same address of a memory 1 and in the address unit of n bits. The CPU 3 increments the address of the memory 1 while setting the address read from a ROM 2 as the first address in accordance with 1/n clocks from a 1/n frequency divider 4 using an internal DAMC to output the vertical- and horizontal-synchronizing signals and video data. The video signals are outputted by parallel/series conversion in a P/S converter 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a character generator (CG: character type) for a color CRT display device or the like.
The present invention relates to a video signal generation circuit used in a video signal input control device of a CRT display device that does not include a generator).

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration example of a conventional video signal generating circuit. In FIG. 4, 12 is RO
M (Read Only Memory) and a horizontal synchronization signal (HS
sync.), vertical sync signal (V.Sync.), and the like, sync signal data that specifies the period, pulse width, etc. of sync signals. Reference numeral 13 is an external control unit (CPU) such as a personal computer for reading out the synchronizing signal data such as the period and the pulse width of the synchronizing signal from the ROM 12 and inputting it to the CRTC 14. Reference numeral 14 inputs the synchronization signal data read from the ROM 12 and the reference clock (CLK),
It is a CRTC (CRT controller) that counts clocks according to the synchronization signal data and outputs a horizontal synchronization signal and a vertical synchronization signal.

Reference numeral 16 receives the horizontal synchronizing signal and the vertical synchronizing signal output from the CRTC 14, a clock, and a clock obtained by dividing the clock by 1 / n by the 1 / n divider 15 to input the vertical synchronizing signal. This is an address generator that reads one address of data from the data memory 11 after a back porch period determined for the horizontal synchronizing signal as a trigger and outputs an address signal that increments the address every 1 / n clock. A video data memory 11 stores data of n dots per address.
Reference numeral 18 denotes a parallel-serial (P) that converts the video data, which is output from the memory 11 in parallel for each address, into parallel-serial by the clock from the gate 17 and outputs it as serial video data (video signal).
/ S) converter. Reference numeral 17 denotes a gate circuit which gives a P / S converter 18 through the input clock during the display period only by the gate signal indicating the display period output from the address generator 16.

The CPU 13 reads out the synchronizing signal data such as the period of the horizontal synchronizing signal and the vertical synchronizing signal and the pulse width from the ROM 12 and sets them in the CRTC 14. The CRTC 14 generates a pulse corresponding to the horizontal synchronizing signal by using the reference clock CLK as the synchronizing width count, and resets when the period width is counted, and the horizontal synchronizing signal (H.Sync.)
Is output. Similarly, H.264. Sync. Is counted and the vertical synchronizing signal (V. Sync.) Is also output. The H.264 output from the CRTC14. Sync. And V. Sync. Is output as a synchronization signal and also input to the address generator 16.

The address generator 16 has a reference clock CL.
K and H. Sync. Is counted, pulses for horizontal back porch and vertical back porch are generated, and H.H. Sync., Horizontal back porch, and V. During the period of Sync. And vertical pack pouch, the address of the memory 11 is not incremented, and a disable signal for turning off the gate 17 is output. Memory 1 except this disable period
It increments every 1 / n clock from the start address of the data of 1 and reads the video data from the memory 11 and outputs it to the parallel-serial converter 18.

Also, the clocks of the horizontal back porch and the vertical back porch output from the address generator 16 S
The count number of ync. is uniformly determined by hardware, but the CPU 13 can also read the data from the ROM 12 and set it. The parallel-serial converter 18 converts the parallel video data output from the memory 11 into serial data with the clock from the gate 17 and outputs the serial data. This serially converted video data is output as a video signal.

[0007]

However, the above-mentioned conventional circuit configuration has the following problems. That is, H. Syn
c. and V. In order to generate the Sync., A counter group such as the CRTC 14, a ROM 12 and a CPU 13 for setting the count number in the CRTC 14 are required. Also,
H. Sync.V. In order to generate a video signal synchronized with a synchronization signal such as Sync., The control of the memory becomes complicated, that is, clock, H.264. Sync., V. When generating the disable signal using Sync., The setup time of the memory 11 and the delay time of the gate 17 are set so that the video signal output from the parallel-serial converter 18 is output at the set timing. It must be generated in consideration.

The object of the invention is to Sync., V. Sync.
Another object of the present invention is to provide a video signal generation circuit capable of easily outputting a synchronizing signal such as. Another object of the present invention is to provide a video signal generation circuit that can easily output a video signal synchronized with the synchronization signal, that is, can easily perform read control of the memory.

[0009]

According to the present invention, a sync signal or sync information for generating a sync signal and a back porch is stored at the same address as video data in a memory, and the same as in reading video data. It is characterized in that the sync signal or the sync signal and the back porch are read and output.

That is, the present invention according to claim 1 is a first memory in which sync signal data designating a period and a pulse width of a vertical sync signal and a horizontal sync signal and video data are stored at the same address, and A second memory in which read address information of the first memory is stored, a CPU having an internal DMAC for controlling the address of the first memory and outputting a reference clock, and a CPU for reading from the first memory. P / P that outputs the video signal according to the reference clock by parallel-serial conversion of the video data
The CPU includes an S converter and a 1 / n frequency divider that divides the reference clock output from the CPU by the bit number n of the video data to output a 1 / n clock.
Uses the DMAC when the read start address of the first memory is designated from the second memory,
The address of the first memory is sequentially incremented by 1 / n clock from the 1 / n frequency divider, and if the sync signal data is 0 according to the sync signal data stored in the first memory, a low level, If it is 1, a high level vertical synchronizing signal and a horizontal synchronizing signal are output, and at the same time, the video data stored in the first memory is output and given to the P / S converter. It is what

Further, in the present invention according to claim 2, video data of all patterns of 2 ⁿ +3 patterns is stored as video data stored in the first memory, and addresses stored in the second memory are stored. As information, the order of addresses for reading the contents of the first memory is stored.
U is configured to read the contents of the first memory according to the address information of the second memory.

[0012]

[Operation] A synchronization signal read from the data memory 1,
Alternatively, since the sync signal and the back porch are read at the same timing as the video data, the video signal, the sync signal, and the back porch can be easily synchronized. Also, for address control of the memory 1, the designated address is stored in advance in the ROM
The address generator is not necessary because the data is written in 2, the data is read out by the CPU 3, and set in the memory 1.

[0013]

1 is a block diagram showing a first embodiment of the present invention. In the figure, 2 is a memory in which read address information of the memory 1 is stored, for example, a ROM. A CPU 3 designates an address of the memory 1 on the basis of the information stored in the ROM 2 and outputs a reference clock CLK. Reference numeral 1 is a memory in which the synchronization signal data and the data for outputting the video signal are stored at the same address. Reference numeral 5 denotes a P / S converter that performs parallel-serial conversion (hereinafter referred to as P / S conversion) of parallel video data read from the memory 1 and outputs the video signal. It is a frequency divider.
One of the features of the first embodiment in FIG. 1 is the ROM 2, which specifies only the start address of the data read from the memory 1 and uses the internal DMAC (direct memory access controller) of the CPU 3 to That is, the address of 1 is sequentially incremented to read out the video signal. One of the other features is ROM2
That is, the CPU 3 specifies the address to be read from the memory 1 every time in accordance with the information.

First, the former operation will be described. FIG. 2 is a memory data and timing chart for explaining the operation of the present invention. The ROM 2 sets the read start address of the memory 1 to the CPU 3 and sets the DMA operation. The CPU 3 increments the address of the memory 1 at the timing of 1 / n clock obtained from the 1 / n frequency divider 4 according to the information from the ROM 2.
Here, if the data in the memory 1 is written as shown in FIG. S, V. If S is 0, it is set to low level, and if S is 1, it is set to high level. In the case of this example, H.264. S is low, V.I.
S becomes high level.

Next, the address is incremented,
H. S goes high and V.S. S also goes high. The video data is H.264. S or V. Write 0 for all S periods. Similarly, during the period of the back porch and front porch, video data, H.264. S, V. All you have to do is write 0 in all S bits. The display period starts from the fourth address in the example of FIG. 2, the video data of the memory 1 is input to the P / S converter 5, where it is P / S converted at the clock timing and output as a video signal. . As described above, since the signals read from the memory 1 are all synchronized with the clock as the basic timing,
The video signal and the sync signal H. S, V. It can be synchronized with S.

Next, the latter operation will be described. Figure 3
Shows an example of contents of memory data for explaining another operation of the present invention. In the latter case, there are 19 kinds of data written in the memory 1 (when the video data is 4 bits) shown in FIG. S. and H.A. When both S are high, (2)
H. When only S is high, (3) is V.S. Only when S is high is shown. (4) has two meanings, one of which indicates a back porch or a front porch, and the other one indicates a case where the video signal during the display period has a low level of 4 dots. (5) to (19) show all the continuous 4-dot patterns during the display period. For the memory 1 in which the above data is written, the CPU 3 sets an address based on the information in the ROM 2 in which the address of the memory 1 is written so that the signal timing to be output is formed. In the same manner as the former, H. S, V. The S-video signal is output. As described above, the H.264 and video signals formed by this method are also used. S, V. S can be easily synchronized. Also, FIG.
The ROM 2 and the memory 1 can also share the same memory.

[0017]

As described above, according to the present invention, since the video data and the sync signal are read from the same memory at the same timing, the timing of the video signal and the sync signal can be easily set. Further, complicated memory control for generating the video signal synchronized with the synchronization signal is not required, and the synchronization signal and the video signal can be easily generated only by reading the data from the memory in which the data is stored.
INDUSTRIAL APPLICABILITY The present invention is particularly effective for a self-test circuit of equipment handling video signals.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a memory data and timing chart for explaining the operation of the present invention.

FIG. 3 is a data content example diagram of a memory for explaining another operation of the present invention.

FIG. 4 is a block diagram showing an example of a conventional circuit configuration.

[Explanation of symbols]

 1 memory 2 ROM 3 CPU 4 1 / n frequency divider 5 P / S converter 11 data memory 12 ROM 13 CPU 14 CRTC 15 1 / n frequency divider 16 address generator 17 gate 18 P / S converter

Claims (2)

[Claims] 1. A first memory in which sync signal data designating a period and a pulse width of a vertical sync signal and a horizontal sync signal and video data are stored at the same address, and read address information of the first memory. A second memory stored therein, a CPU having an internal DMAC for controlling an address of the first memory and outputting a reference clock, and a video data read from the first memory is converted from parallel to serial. And a P / S converter that outputs a video signal according to the reference clock, and 1 / n minutes that divides the reference clock output from the CPU by the bit number n of the video data and outputs a 1 / n clock. A frequency divider, and the CPU, when the read start address of the first memory is designated from the second memory, the CPU
Is used to sequentially increment the address of the first memory with the 1 / n clock from the 1 / n frequency divider,
According to the sync signal data stored in the first memory, a low level vertical sync signal and a horizontal sync signal are output when the sync signal data is 0, and a high level when the sync signal data is 1, and are stored in the first memory. And a video signal generation circuit configured to output the video data and apply the video data to the P / S converter. 2. The 2 ⁿ +3 patterns of video data of all patterns are stored as the video data stored in the first memory, and the contents of the first memory are stored as the address information stored in the second memory. 2. The video signal generating circuit according to claim 1, wherein an order of addresses for reading is stored, and the CPU is configured to read the contents of the first memory according to the address information of the second memory.