JPH0727504Y2 - Input signal determination circuit for liquid crystal display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a circuit for determining an input signal of a liquid crystal display device.

[Prior Art] In an LCD (liquid crystal display) device, a dot clock having an accurate frequency is generated, an input video signal is traced for each dot, and data necessary for display is created to create a frame memory. It is written in, read out and displayed at a timing suitable for the LCD unit.

In this case, the dot clock frequency, the video display position, the display range, etc. are different from each other according to the type of the input signal, and in order to be applicable to a plurality of types of video signals, the input signal is determined, It is necessary to give the dot clock frequency, the video display position, and the display range based on the determination result to the control circuit for operation.

A conventional input signal determination circuit of this type is constructed, for example, as shown in FIG. That is, the input horizontal sync signal
SYNC is applied directly to the comparators 10, 11 and 12. Meanwhile, the comparison reference signals having different values are applied to the comparators 10, 11 and 12, respectively. These comparison reference signals are input to the comparison reference signal generation circuits 14 and 15 which are input after the basic clock CK1 is divided by the counter 13.
16 formed respectively. Each of the comparators determines which of the horizontal synchronization signal HSYNC and the comparison reference signal has a longer cycle, and outputs the result to the selection circuit 17. In the selection circuit 17, based on the comparison result given from some comparators, it is determined in which region the horizontal synchronization signal HSYNC is divided by the comparison reference signal,
As a result, the type of input signal is determined.

[Problems to be Solved by the Invention] According to the conventional input signal determination circuit as described above, by applying the input horizontal synchronization signal HSYNC directly to the comparator, which region is present in the area divided by the comparison reference signal? Is being determined. Therefore, a plurality of signals may belong to the same area, and in such a case, it may be determined that all the signals are of the same type, and there may be a problem that they cannot be distinguished from each other. Further, when the difference between the cycle of the horizontal synchronizing signal to be judged and the cycle of other horizontal synchronizing signals is shorter than the cycle of the basic clock, the conventional method of dividing the basic clock to create the comparison reference signal distinguishes the two. There is also a problem that you cannot do it.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an input signal judging circuit which can surely judge the type of an input signal and can perform the judgment even when the period difference of the horizontal synchronizing signals is very small.

[Means for Solving the Problems] The features of the present invention for achieving the above-described object are a frequency divider for dividing a horizontal synchronizing signal of an input signal by a predetermined dividing ratio, and a period of the divided horizontal synchronizing signal. There is provided a counting means for counting the number of clocks in the internal clock and a means for comparing the counting result from the counting means with a plurality of comparison reference values to determine the type of the input signal.

[Operation] The horizontal synchronizing signal of the input signal is frequency-divided by the frequency divider at a predetermined frequency division ratio and its period is expanded. The number of clocks input in the expanded cycle is counted by the counting means to measure the cycle, and the count result is compared with a plurality of comparison reference values to determine the type of the input signal.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram schematically showing the configuration of the entire LCD device when an embodiment of the present invention is applied to the LCD device.

In the figure, 20 is a frame memory data creation and frame memory writing circuit, 21 is a frame memory circuit, 22
Is a frame memory reading and LCD drive circuit, and 23 is a dot matrix type LCD unit.

The frame memory data creation and frame memory writing circuit 20 outputs the horizontal, vertical and horizontal timing signals HBLA from the horizontal and vertical timing and basic clock creation circuit 24 to the color video signals R, G and B from an external personal computer or the like.
NK, vertical timing signal VBLANK, and basic clock CK1
Are configured to be supplied respectively. This frame memory data creation and frame memory writing circuit
A frame memory data 20 generates a write control signal such as an address signal, a write signal, a chip select signal and a read / write switching signal from these signals and serially combines the color video signals R, G and B. Data is sequentially written to predetermined positions of the frame memory circuit 21.

Horizontal and vertical timing and basic clock generation circuit 24,
It receives the horizontal synchronizing signal HSYNC and the vertical synchronizing signal VSYNC of the above-mentioned color video signal supplied from an external device such as a personal computer, and receives the above-mentioned horizontal timing signal HBL.
ANK, vertical timing signal VBLANK, and basic clock CK1
Create and output.

The frame memory read and LCD drive circuit 22 uses the LCD drive clock CK having a cycle longer than the basic clock CK1.
From 2, the read control signals such as the address signal, the read signal and the chip select signal are generated, and the frame memory circuit is generated.
The frame memory data is sequentially read from 21 in synchronization with the read signal. Furthermore, this frame memory reading and LC
The D drive circuit 22 is an LCD suitable for LCD formats such as LCD sync signals, data shift clock signals, and AC signals.
A drive signal is generated and output to the LCD unit 23 together with the read data. As a result, an image is displayed on the LCD unit 23.

The horizontal sync signal HSYNC and the vertical sync signal VSYNC are also applied to the input signal determination circuit 25 according to the present invention, and as described later,
Determine the type of color video signal to be input. The determination output of the input signal determination circuit 25 is applied to the control signal generation circuit 26 to generate a signal for controlling the dot clock frequency, the video display position, the display range and the like.

FIG. 1 is a block diagram showing a configuration example of the input signal determination circuit 25 of FIG.

In the figure, 251 is a frequency divider, which is a horizontal synchronization signal HSYN supplied from an external device such as a personal computer.
Divide C by a predetermined division ratio M. An output terminal of the frequency divider 251 is connected to a control input terminal of a counter 252 which is an example of counting means. The basic clock CK1 is configured to be applied to the count input terminal of the counter 252, and the basic clock within the period of HSYNC / M output from the frequency divider 251, that is, within the period of the divided HSYNC. The number of CK1 is counted. A comparator 253 is connected to the output terminal of the counter 252, and the count result N of the counter 252 is applied to one input terminal of the comparator 253. The comparison data generation circuit 254 is connected to the other input terminal of the comparator 253. The comparison data generation circuit 254 has a comparison data table in which a plurality of comparison data for discriminating the type of the input signal is stored in advance, and is configured to sequentially output these comparison data. A judgment signal generation circuit 255 is connected to the output terminal of the comparator 253.

H obtained by dividing the horizontal synchronization signal HSYNC by a predetermined division ratio M
The counting result N corresponding to the cycle of SYNC / M is sequentially compared with a plurality of comparison data in the comparator 253. As a result, it is determined in which region the count value N is divided by the comparison data, and the determination signal generating circuit 255 outputs a determination signal representing that region. In this example, the comparator 25
3, comparison data generation circuit 254, and determination signal generation circuit 255
Corresponds to the discrimination means of the present invention.

In addition, in the input signal determination circuit 25 of FIG.
3, comparison data generation circuit 254, and determination signal generation circuit 255
Alternatively, a plurality of comparators as shown in FIG. 5 and a selector circuit connected to their output terminals may be provided.

FIG. 3 is a block diagram showing another configuration example of the input signal determination circuit 25 of FIG.

As shown in the figure, this configuration example includes a counter 252, a comparator 253, a comparison data generation circuit 254 in the configuration example of FIG.
Also, a microcomputer 256 is provided in place of the judgment signal generation circuit 255. The microcomputer 256 includes a CPU (central processing unit) 256a, a ROM (read only memory) 256b, a RAM (random access memory) 256c,
A well-known input / output interface, memory interface, basic clock generation circuit, etc., which are not shown, are provided. A table for comparison data, which will be described later, is prepared in the ROM 256b.

FIG. 4 is a flow chart showing a program of the microcomputer 256, and the operation of this configuration example will be described below with reference to the same figure.

From the frequency divider 251, a signal having a pulse width HSYNC / M obtained by dividing the horizontal synchronizing signal HSYNC by a predetermined dividing ratio M is applied to the microcomputer 256. First, in step S1, the number of basic clocks CK1 generated during the period of HSYNC / M is counted by an internal counter or the like of the microcomputer, and the counted value is stored as N in the memory.
In the next step S2, the comparison data number i is set to the initial value 1.

The comparison data table in the ROM 256b stores comparison data D ₁ , D ₂ , D ₃ , ..., D _n-1 in advance. Each of these comparison data is determined as follows. However, it is assumed that there are n types of signals to be judged.

HSYNC / of various signals to be judged by S ₁ , S ₂ , S ₃ , ..., S _n
Assuming the true count value of M, if S ₁ <S ₂ <S ₃ <... <S _n and D ₁ <D ₂ <D ₃ <... <D _n-1 , then D ₁ = (S ₁ + S ₂ ) / 2 D ₂ = (S ₂ + S ₃ ) / 2 D ₃ = (S ₃ + S ₄ ) / 2: D _n-1 = (S _n-1 + S _n ) / 2 In step S 3, the above-mentioned total Determine if the number N is less than D _i . If N <D _i , step S
Proceed to step 6 and output the current i as the judgment result. If N ≧ D _i, the process proceeds to step S4 and i is incremented by one. In the next step S5, it is determined whether or not i = n. If i = n, the process proceeds to step S6 to output the current i as a determination result, and otherwise returns to step S3.

As described above, the determination signal indicating the type of the input signal can be obtained by the configuration example of FIG. In this example, the internal counter corresponds to the counting means of the present invention, and the part of the program shown in FIG. 4 that performs the processing from step S2 to step S6 corresponds to the determining means of the present invention.

By performing microcomputer control as in the example of FIG. 3, the input signal determination circuit can be configured by using the microcomputer of the LCD device main body together without adding a comparison signal generation circuit and a comparator in the prior art. This configuration is particularly advantageous because there is no increase in hardware when discriminating many types of signals.

Next, the present invention will be described in more detail by an actual operation example.

For example, a case will be described in which video signals of different types from personal computers of respective companies are displayed.

It is assumed that there are the following three frequencies of the horizontal synchronizing signal HSYNC of each input signal.

a) 22.2 KHz b) 21.8 KHz c) 18.0 KHz It is assumed that the basic clock CK1 is 1 MHz. When these horizontal synchronizing signals HSYNC are simply counted by the basic clock CK1, the count value N'is N _a ′ = 45, N _b ′ = 45, N _c ′ = 55,
Since N _a ′ = N _b ′, it becomes impossible to determine.

However, in the present invention, each input signal is first divided and the number of basic clocks in the divided period is counted. Here, if the division ratio M is M = 256, it becomes a) 86.71875 Hz b) 85.15625 Hz c) 70.3125 Hz, and when these are counted by the basic clock CK1, the count value N is N _a = 11531, N _b = 11743, The values are different from each other, such as N _c = 14222.

Therefore, as the comparison data, the following two data are given in consideration of errors and variations in the basic clock and the input signal.

D _a = (N _a + N _b ) / 2 = 11637 D _b = (N _b + N _c ) / 2 = 12982 The determination result is the next 3 divided by the comparison data D _a and D _b.
It is calculated in which of the two areas.

Area a N <11637 Area b 11637 <N <12982 Area c 12982 <N As described above, even when video signals of different types are to be displayed, the types can be automatically and reliably determined.

[Advantages of the Invention] As described in detail above, according to the present invention, a divider for dividing the horizontal synchronizing signal of the input signal by a predetermined dividing ratio, and a clock within the period of the divided horizontal synchronizing signal. Since the counting means for counting the number of the input signals and the means for determining the type of the input signal by comparing the counting result from the counting means with a plurality of comparison reference values are provided, the type of the input signal can be reliably determined. In addition, the type of the input signal can be determined even when the period difference between the horizontal synchronizing signals is very small.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of the configuration of an input signal judgment circuit in an embodiment of the present invention, and FIG. 2 is an LCD of the above embodiment.
3 is a block diagram schematically showing the configuration of the entire apparatus, FIG. 3 is a block diagram showing another configuration example of an input signal determination circuit, FIG. 4 is a flowchart of a program in the input signal determination circuit of FIG. 3, and FIG. FIG. 4 is a block diagram showing a conventional input signal determination circuit. 20 …… Frame memory data creation and frame memory writing circuit, 21 …… Frame memory circuit, 22 …… Frame memory reading and LCD drive circuit, 23 …… LCD unit, 24 …… Horizontal and vertical timing and basic clock creation circuit, 25 …… input signal judgment circuit, 26 …… control signal creation circuit, 251 …… divider, 252 …… counter, 253 …… comparator, 254 …… comparison data generation circuit, 255 …… judgment signal generation circuit, 256 …… Microcomputer.

Claims (1)

[Scope of utility model registration request] 1. A frequency divider for dividing a horizontal synchronizing signal of an input signal by a predetermined dividing ratio, a counting means for counting the number of clocks in a period of the divided horizontal synchronizing signal, and a counting means from the counting means. An input signal determination circuit for a liquid crystal display device, comprising: means for comparing the count result of (1) with a plurality of comparison reference values to determine the type of the input signal.