JPH07270499A - Inspection method for semiconductor device - Google Patents

Abstract

PURPOSE:To provide a convenient and highly accurate inspection method by reducing operating current fed to a semiconductor device by a prescribed amount from a normal value, and making judgement as to whether an output signal from the semiconductor device shows a logical value corresponding to a logical binarized signal. CONSTITUTION:A signal source 1 generates a logical binarized signal having a prescribed timing, and this signal is sent to the base of a transistor Q11. Also, the emitter of the transistor Q11 is grounded. Furthermore, a current source 2 is connected to the emitter of another transistor Q21 and the current from the source 2 is variably controlled. Operating current IINJ is fed from the source 2 to the base of the transistor Q11 through the transistor Q12, and the transistor Q11 operates as the inverter. In a normal operation condition, the operating current IINJ is set as approximately equal to I gamma A, but in this inspection method, the current IINJ from the source 2 is variably controlled at normal temperature and reduced by a prescribed amount.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device inspection method, and more particularly to a semiconductor device inspection method suitable for use in a semiconductor device having a logic circuit formed therein.

[0002]

2. Description of the Related Art A semiconductor device, such as an IIL, which has a large number of inverters connected in cascade to form a logic circuit, has been conventionally known. Such a semiconductor device cannot obtain a correct output signal according to an input logic binary signal if a defect occurs in an element even in one stage during manufacturing.

Therefore, conventionally, a person has inspected a crystal defect visually by using a microscope after emphasizing the diffusion. In this method, the non-uniformity of crystals can be identified by finding the bubble state, and the good product and the defective product are determined.

Alternatively, the semiconductor device is brought into a low temperature or high temperature state to increase the leak current as compared with that at the normal temperature, and an input logic binary signal is given to the semiconductor device, and a correct output corresponding to the input logic binary signal is given. I was checking if I could get a signal. In this way, the output signal is checked to determine whether it is a good product or a defective product. Although the leak current increases in the high temperature state than in the low temperature state, the inspection accuracy increases,
If the temperature is too high, reliability will be a problem.

[0005]

However, according to the former method, the inspection accuracy is limited because it is an inspection by the naked eye, and the inspection accuracy varies depending on individual differences. On the other hand, in the latter method, there is no variation in the inspection accuracy and the inspection accuracy can be improved depending on the environmental temperature, but a facility for bringing the semiconductor device into a low temperature or high temperature state is required and a large-scale inspection method. There was a problem that became.

Therefore, the present invention has been made in view of the above points, and it is an object of the present invention to provide a simple and accurate method for inspecting a semiconductor device.

[0007]

In order to solve the above problems, the present invention has the following configuration.

That is, a semiconductor device formed with a logic circuit is supplied with a logic binary signal and at the same time an operating current is supplied to the semiconductor device, and the semiconductor device is judged as good or bad based on the output signal of the semiconductor device. In the inspection method, the operating current supplied to the semiconductor device is reduced by a predetermined amount from a normal value, and it is determined whether the output signal of the semiconductor device shows a logical value according to the logical binary signal to judge whether the semiconductor device is good or bad. It is configured to judge a defect.

[0009]

According to the present invention having the above structure, the ratio of the leak current in the output current is increased by reducing the operating current supplied to the semiconductor device by a predetermined amount from the normal value. In a defective product, which has a large number of defects, h _fe acts so as to be lower than that in a non-defective product due to the influence of leak current.

[0010]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a circuit diagram for explaining one embodiment of the present invention. The circuit shown in FIG.
The logic circuit IC is called a gated injection logic) and is usually formed on the same semiconductor chip in coexistence with the linear IC by a common process.

The signal source 1 generates a logic binary signal at a predetermined timing. This logical binary signal is supplied to the base of the transistor Q ₁₁ . The emitter of the transistor Q ₁₁ is grounded.

The collector of the transistor Q ₂₁ is connected to the base of the transistor Q ₁₁ , and the base of the transistor Q ₂₁ is grounded. On the other hand, transistor Q
_The current source 2 is connected to the emitter of _21.
The current from is variably controlled.

[0013] With this configuration, the base operating current I _INJ of the transistor Q ₁₁ from the current source 2 via the transistor Q ₂₁ is injected, the transistor Q ₁₁ operates as an inverter. Further, the collector of the transistor Q ₁₁ is connected to the next inverter.

That is, the base of the transistor Q ₁₂ is connected to the collector of the transistor Q ₁₁ . The emitter of the transistor Q ₁₂ is grounded. Moreover, the base of the transistor Q ₁₂ is the collector of the transistor Q ₂₂ is connected, the base of the transistor Q ₂₂ is grounded. On the other hand, the emitter of the transistor Q ₂₂ is connected to the current source 2 for injecting the operating current I _INJ, like the emitter of the transistor Q ₂₁ .

Further, the collector of the transistor Q ₁₂ is connected to a plurality of stages of inverters in the subsequent stage. The final stage inverter is composed of a transistor Q _1n and a transistor Q _2n . If the value of n is an odd number, the inverter circuit is configured as a whole. If the value of n is an even number, a buffer circuit is configured as a whole.

In the present embodiment, the inverter circuit or the buffer circuit is formed because the inverters are connected in cascade, but the connection method of each inverter transistor is not limited to this, and other logic circuits may be formed. Can also be considered. A tester 3, for example, is connected to the collector of the transistor Q _{1n at} the final stage. A waveform monitor such as an oscilloscope may be connected instead of the tester 3.

FIG. 2 shows a ratio (I _C / I) between the collector output current I _C and the operating current I _{IN J} when the operating current I _INJ is varied.
FIG. 7 is a diagram showing _INJ ) of a non-defective transistor without crystal defects.

In a normal operation, I _INJ = 1 μA is set, but in the semiconductor device inspection method according to this embodiment, the current I _{IN J} from the current source 2 is variably controlled at room temperature (that is, room temperature). This is reduced by a predetermined amount. That is, it is reduced to 1 nA as shown.

The ratio (I _C / I _INJ ) between the collector output current I _C and the operating current I _INJ is nothing but the current amplification factor of the grounded emitter, and I _INJ shows a peak value at several μA as shown in the figure,
It decreases linearly on both sides of the peak. Normal operation I
_It is about 20 at _INJ = 1 μA.

When I _INJ is reduced to, for example, several tens of nA, the ratio (I _C / I _INJ ) between the collector output current I _C and the operating current I _INJ is set to 14 to 18, and the transistor has sufficient current driving capability. Have.

Therefore, since the transistor in the next stage can be driven, a correct signal corresponding to the input logic binary signal can be observed by the tester 3 connected to the collector of the transistor Q _{1n in} the final stage. Input logic 2
The logical value of the value signal is switched at a relatively long cycle such that the output signal corresponding to the value signal can be observed by the tester 3.

FIG. 3 shows a ratio (I _C / I) between the collector output current I _C and the operating current I _{IN J} when the operating current I _INJ is varied.
FIG. 3 is a diagram showing _INJ ) of a defective transistor having crystal defects.

In normal operation, I _INJ = 1 μA is set, but in the semiconductor device inspection method of this embodiment, the current I _{IN J} from the current source 2 is variably controlled at room temperature (that is, room temperature). This is reduced by a predetermined amount. That is, it is reduced to 1 nA as shown.

The ratio of the collector output current I _C to the operating current I _INJ (I _C / I _INJ ) is nothing but the current amplification factor of the grounded emitter, and as shown in the figure, I _INJ peaks at several μA as in a good transistor. The value is shown (peak value is a little small), and it decreases linearly in the increasing direction on the right side of the peak. On the other hand, it decreases in a curve in the decreasing direction on the left side of the peak. The value is about 16 at I _INJ = 1 μA in the normal operation, and has a sufficient driving capability.

When I _INJ is reduced to, for example, several tens of nA, the ratio (I _C / I _INJ ) between the collector output current I _C and the operating current I _INJ is set to 4 to 10, which is about half that of a non-defective transistor. It has only current drive capability.

Therefore, it is impossible to drive the transistor of the next stage and normal operation cannot be performed, and even if there is only one defective product in any stage, the correct signal corresponding to the input logic binary signal is finally given. The output of the final stage cannot be observed by the tester 3 connected to the collector of the transistor Q _1n of the stage, and the output of the final stage is a high level signal which does not change.

As described above, according to this embodiment, since the ratio of the leak current in the output current increases by reducing the operating current supplied to the semiconductor device by a predetermined amount from the normal value, the leakage due to the crystal defect. In a defective product that originally has a large current, h _fe is lower than that in a non-defective product due to the influence of leakage current, and the transistor in the next stage cannot be driven.

Therefore, at room temperature, a simple method of varying the current without the need for large-scale equipment,
A good product and a defective product can be distinguished and inspected. Further, since the inspection method does not depend on the naked eye, the inspection accuracy is determined according to the current from the current source, and stable and good inspection accuracy can be obtained.

[0029]

As described above, according to the present invention, when the operating current supplied to the semiconductor device is reduced by a predetermined amount from the normal value, h _fe becomes lower than that of a non-defective product due to the influence of the leak current. The next-stage logic circuit cannot be driven.
Therefore, the output signal does not show a logical value according to the input logical binary signal even at room temperature without requiring a facility for changing the temperature, so that a defective product can be accurately and accurately determined as a good product. There is a feature that can be.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining an embodiment of the present invention.

2 is a diagram showing a transistor of a non-defective without crystal defects ratio (I _C / I _INJ) the collector output current I _C and the operating current I _INJ when the variable operating current I _INJ.

3 is a diagram showing the ratio (I _C / I _INJ) transistors defective in crystal defects of the collector output current I _C and the operating current I _INJ when the variable operating current I _INJ.

[Explanation of symbols]

1 signal source 2 current source 3 tester Q ₁₁ , Q ₁₂ , ~ Q _1n , Q ₂₁ , Q ₂₂ , ~ Q _2n transistor

Claims (1)

[Claims] 1. A logic binary signal is input to a semiconductor device formed with a logic circuit, an operating current is supplied to the semiconductor device, and a pass / fail of the semiconductor device is determined based on an output signal of the semiconductor device. In a method of inspecting a semiconductor device, it is determined whether the operating current supplied to the semiconductor device is reduced by a predetermined amount from a normal value and an output signal of the semiconductor device shows a logical value according to the logical binary signal. Then, a method for inspecting a semiconductor device is characterized by determining whether the semiconductor device is good or bad.