JP3173274B2 - Inspection method for semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting a semiconductor device, and more particularly to a method for inspecting a semiconductor device suitable for a semiconductor device having a logic circuit formed thereon.

[0002]

2. Description of the Related Art A semiconductor device, such as an IIL, in which a plurality of inverters are connected in cascade to form a logic circuit is conventionally known. In such a semiconductor device, if a defect occurs in even one element during manufacturing, a correct output signal corresponding to the input logical binary signal cannot be obtained.

[0003] Conventionally, humans have inspected crystal defects with the naked eye using a microscope after the diffusion is revealed. In this method, the non-uniformity of the crystal can be identified by finding the bubble state, and a good product and a defective product are determined.

Alternatively, an input logic binary signal is given to the semiconductor device by setting the semiconductor device to a low or high temperature state to increase the leakage current from that at normal temperature, and a correct output corresponding to the input logic binary signal is given. I was checking if a signal could be obtained. As described above, the output signal is used to determine whether the product is good or defective. In addition, although the test accuracy is improved in the high temperature state as compared with the low temperature state, the leakage current increases,
If the temperature is too high, reliability becomes a problem.

[0005]

However, according to the former method, since the inspection is performed by the naked eye, the inspection accuracy is limited, and the inspection accuracy is varied due to individual differences. On the other hand, in the latter method, although there is no variation in the inspection accuracy and the inspection accuracy can be improved depending on the environmental temperature, equipment for setting the semiconductor device to a low or high temperature state is required, so that a large inspection method is required. There was a problem.

The present invention has been made in view of the above points, and has as its object to provide a simple and accurate method for inspecting a semiconductor device.

[0007]

In order to solve the above-mentioned problems, the present invention has the following constitution.

That is, a logic binary signal is input to a semiconductor device formed with a logic circuit, an operating current is supplied to the semiconductor device, and the semiconductor device determines good or bad based on an output signal of the semiconductor device. In the inspection method, the operating current supplied to the semiconductor device is reduced by a predetermined amount from a normal value, and it is determined whether or not the output signal of the semiconductor device indicates a logical value corresponding to a logical binary signal to determine whether or not the semiconductor device is good. It was configured to determine a defect.

[0009]

According to the present invention having the above structure, the operating current supplied to the semiconductor device is reduced by a predetermined amount from the normal value, so that the ratio of the leak current in the output current increases. In the case of a defective product originally having a large amount, h _fe acts to be lower than that of a non-defective product due to the influence of the leak current.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram for explaining one embodiment of the present invention. The circuit shown in FIG.
It is composed of a logic circuit IC called graded injection logic, and is usually formed on the same semiconductor chip by coexisting with a linear IC by a common process.

The signal source 1 generates a logical binary signal at a predetermined timing. The logical binary signal is supplied to the base of the transistor Q _11. The emitter of the transistor Q ₁₁ is grounded.

[0012] In addition, the collector of the transistor Q ₂₁ is connected to the base of the transistor Q _11, the base of the transistor Q ₂₁ is grounded. On the other hand, transistor Q
_The current source 2 is connected to the emitter ₂₁ and the current source 2
Is variably controlled.

[0013] With this configuration, the base operating current I _INJ of the transistor Q ₁₁ from the current source 2 via the transistor Q ₂₁ is injected, the transistor Q ₁₁ operates as an inverter. Further, the collector of the transistor Q ₁₁ is connected to the next-stage inverter.

[0014] That is, the base of the transistor Q ₁₂ is connected to the collector of the transistor Q _11. The emitter of the transistor Q ₁₂ is grounded. Moreover, the base of the transistor Q ₁₂ is the collector of the transistor Q ₂₂ is connected, the base of the transistor Q ₂₂ is grounded. On the other hand, to the emitter of the transistor Q ₂₂ is a current source 2 for the operating current I _INJ injection similarly to the emitter of the transistor Q ₂₁ is connected.

Furthermore, downstream inverters are a plurality of stages cascade-connected to the collector of the transistor Q _12. Inverter in the final stage, and a transistor Q _1n and the transistor Q _2n. If the value of n is an odd number, an inverter circuit is constituted as a whole. If the value of n is an even number, a buffer circuit is constituted as a whole.

In this embodiment, an inverter circuit or a buffer circuit is formed because a plurality of inverters are connected in cascade. However, the connection method of each inverter transistor is not limited to this, and other logic circuits may be formed. Is also conceivable. For example, a tester 3 is connected to the collector of the transistor Q _{1n in} the last stage. Of course, a waveform monitor such as an oscilloscope may be connected instead of the tester 3.

[0017] The ratio of 2 and the collector output current I _C at the time of varying the operating current I _INJ and the operating current I _{IN J} (I _C / I
_INJ ) is a diagram showing a non-defective transistor having no crystal defects.

[0018] While in normal operation is set to about I _INJ = 1 .mu.A, the inspection method of a semiconductor device according to the present embodiment, the variable controlling the current I _{IN J} from the current source 2 at room temperature (i.e., room temperature) This is reduced by a predetermined amount. That is, it is reduced to 1 nA as shown in the figure.

The ratio of the collector output current I _C to the operating current I _INJ (I _C / I _INJ ) is nothing less than the current amplification factor of the common emitter, and I _INJ shows a peak value at several μA as shown in the figure.
It decreases linearly on both sides of the peak. I for normal operation
_It is about 20 when _INJ = 1 μA.

When I _INJ is reduced to, for example, several tens of nA, the ratio (I _C / I _INJ ) of the collector output current I _C to the operating current I _INJ is set to 14 to 18, and the transistor has sufficient current driving capability. Have.

Therefore, since the transistor at the next stage can be driven, a correct signal corresponding to the input logic binary signal can be observed by the tester 3 connected to the collector of the transistor Q _1n at the last stage. Note that input logic 2
The logic value of the value signal is switched at a relatively long cycle such that an output signal corresponding to the value signal can be observed by the tester 3.

[0022] The ratio of 3 to the collector output current I _C at the time of varying the operating current I _INJ and the operating current I _{IN J} (I _C / I
_INJ ) is a diagram showing a defective transistor having a crystal defect.

[0023] While in normal operation is set to about I _INJ = 1 .mu.A, the inspection method of a semiconductor device according to the present embodiment, the variable controlling the current I _{IN J} from the current source 2 at room temperature (i.e., room temperature) This is reduced by a predetermined amount. That is, it is reduced to 1 nA as shown in the figure.

The ratio of the collector output current I _C to the operating current I _INJ (I _C / I _INJ ) is nothing less than the current amplification factor of the common emitter, and as shown in the figure, I _INJ peaks at several μA like a good transistor. (The peak value is slightly smaller), and decreases linearly in the increasing direction on the right side of the peak. On the other hand, it decreases in a curve in the decreasing direction on the left side of the peak. It is about 16 when I _INJ = 1 μA in the normal operation, and has a sufficient driving capability.

When I _INJ is reduced to, for example, several tens of nA, the ratio (I _C / I _INJ ) of the collector output current I _C to the operating current I _INJ is set to 4 to 10, which is about half that of a good transistor. It has only current drive capability.

Therefore, it is impossible to drive the transistor at the next stage and normal operation cannot be performed. Even if there is only one defective product at any stage, a correct signal corresponding to the input logic binary signal is finally output. The signal cannot be observed by the tester 3 connected to the collector of the transistor _{Q1n in} the stage, and the output of the final stage is a signal which is fixed at a high level and does not change.

As described above, according to this embodiment, the operating current supplied to the semiconductor device is reduced by a predetermined amount from the normal value, so that the ratio of the leak current in the output current increases. In a defective product originally having a large current, _hfe becomes lower than that of a non-defective product due to the influence of a leak current, so that the transistor of the next stage cannot be driven.

Therefore, a simple method of varying the current at room temperature without requiring a large-scale facility,
Good products and defective products can be discriminated and inspected. In addition, since the inspection method does not use the naked eye, the inspection accuracy is also determined according to the current from the current source, and stable and excellent inspection accuracy can be obtained.

[0029]

As described above, according to the present invention, when the operating current supplied to the semiconductor device is reduced by a predetermined amount from a normal value, _hfe of a defective product becomes lower than that of a nondefective product due to the influence of a leak current. The next stage logic circuit cannot be driven.
Therefore, the output signal does not show a logical value corresponding to the input logical binary signal even at room temperature without the need for a facility for changing the temperature and the like. There is a feature that can be.

[Brief description of the drawings]

FIG. 1 is a circuit diagram for explaining an embodiment of the present invention.

FIG. 2 is a diagram showing the ratio (I _C / I _INJ ) between the collector output current I _C and the operating current I _INJ when the operating current I _INJ is varied, for a non-defective transistor having no crystal defects.

FIG. 3 is a diagram showing the ratio (I _C / I _INJ ) between the collector output current I _C and the operating current I _INJ when the operating current I _INJ is varied for a defective transistor having a crystal defect.

[Explanation of symbols]

1 signal source 2 the current source 3 tester _{Q 11, Q 12, ~Q 1n} , Q 21, Q 22, ~Q 2n transistors

Claims (1)

(57) [Claims] A semiconductor device comprising a logic circuit, a logic binary signal is input to the semiconductor device, an operating current is supplied to the semiconductor device, and the semiconductor device is determined based on an output signal from the semiconductor device. In the method of testing a semiconductor device, the operating current supplied to the semiconductor device is reduced by a predetermined amount from a normal value, and it is determined whether an output signal of the semiconductor device indicates a logical value corresponding to the logical binary signal. And determining whether the semiconductor device is defective or defective.