JPH07264676A - On-vehicle communication equipment - Google Patents

Abstract

PURPOSE:To simplify the circuit configuration of each slave station by setting a communication address based on the reference signal sent from a master station without providing an address setting device on each slave station. CONSTITUTION:This on-vehicle communication equipment is constituted of a master station 1A having a reference signal generation circuit 11, data generation circuit 12 and control part 13, and a slave station 2A having a communication LSI 21A and an oscillator 204. An address setting circuit 207 in the communication LSI 21A measures the periodic length of the reference signal sent from the master station 1A by an original clock from the oscillation circuit 204. A frequency divider circuit 205A in the communication LSI 21A divides the original clock by the frequency dividing ratio according to the communication address and prepares the system clock. Then, an address setting circuit 207 measures the periodic length of the reference clock by the system clock from the frequency divider circuit 205A and inspects whether or not there is an abnormality in the reference clock and the system clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vehicle communication device for connecting a master station and a slave station via a communication line and driving a terminal device connected to the slave station according to driving information from the master station.

[0002]

2. Description of the Related Art A vehicle communication device for transmitting information by connecting various actuators such as motors and various sensors such as vehicle speed sensors to each other via communication lines has been known. This type of vehicle communication device includes a slave station including an actuator and a sensor, and a master station that performs data communication with the slave station. The actuators, sensors, etc. inside the vehicle are distributed and installed in different places of the vehicle, and the functions of the actuators etc. are also different.
Therefore, in the vehicle communication device, each actuator or the like is assigned to a separate slave station according to location or function, and the master station generally controls these slave stations.

As described above, since the vehicle communication device is provided with a plurality of slave stations, an individual address is assigned to each slave station for the purpose of distinguishing each slave station. As a result, the master station can identify each slave station and can communicate only with a specific slave station.

On the other hand, since various devices, harnesses, and the like are complicated inside the vehicle, the places where the above-described vehicle communication device can be mounted are limited, and the master station and the slave stations that constitute the vehicle communication device are limited. Each must be miniaturized.
Therefore, for example, the communication control circuit inside the master station and the slave station is configured by an LSI to reduce the size. Such an LSI is generally called a communication LSI.

FIG. 7 is a block diagram of a conventional vehicle communication device using this type of communication LSI. Reference numeral 2 in FIG. 7 is
It is a slave station connected to the master station 1 by a communication line L, and has a communication LSI 21, an oscillator 22, and an address setter 23 therein. Communication LSI 21 inside this slave station 2
Is a reception buffer 201, a filter circuit 202, a reset circuit 203, an oscillator circuit 204, and a frequency divider circuit 20.
5 and the control unit 206. Of these, the reception buffer 201 amplifies the received communication data, and the filter circuit 202 removes noise included in the output of the reception buffer 201 and inputs the noise to the control unit 206. Reset circuit 203
Immediately after the power is turned on, the reset signal having a predetermined pulse width is input to the control unit 206 to reset the control unit 206.
The oscillation circuit 204 controls the vibration of the oscillator 22 by using, for example, a PLL method, and amplifies and outputs the output of the oscillator 22 that vibrates at the natural frequency. Frequency divider 205
Divides the output of the oscillation circuit 204 by a predetermined dividing ratio, and inputs the divided result to the control unit 206.

The address setter 23 inside the slave station 2 is composed of a DIP switch, a jumper wire, etc., and the communication address of each slave station 2 is set in binary by switching the DIP switch or the like. The communication address set by the address setting unit 23 is input to the control unit 206 inside the communication LSI 21. Although only one slave station 2 is shown in FIG. 7, a plurality of slave stations 2 are actually connected to the master station 1 via the communication line L.

In the conventional vehicular communication device configured as shown in FIG. 7, a communication address is set in the address setting unit 23 provided in each slave station 2 before starting communication. The communication address set in the address setter 23 is input to the control unit 206 in the slave station 2 and stored in a memory (not shown) inside the control unit 206. The address information set in the address setter 23 is also stored in advance in a memory (not shown) inside the master station 1.

After starting the data communication, first, the master station 1 sends out the address of the slave station 2 (hereinafter referred to as the communication target slave station) with which it wants to communicate to the communication line L. Each slave station 2 determines whether the address transmitted from the master station 1 matches the address of its own station. The communication target slave station that has determined that the address matches the address of its own station sends an acknowledge signal to the communication line L and prepares to receive communication data from the master station 1. On the other hand, the other slave stations 2 do not receive communication data from the master station. When the master station 1 receives the acknowledge signal, it determines that the communication target slave station is ready for communication, and sends the communication data to the communication line L. This communication data is received only by the communication target slave station, whereby data communication is performed between the master station 1 and the communication target slave station.

[0009]

Since the slave station of the conventional vehicle communication device is provided with the address setting device 23 inside the slave station 2 as shown in FIG. 7, the circuit of the slave station 2 is correspondingly provided. Larger scale. Further, since the address set in the address setter 23 is input to the communication LSI 21 in parallel,
As the number of slave stations 2 increases, the number of input terminals of the communication LSI 21 increases, and the size of the communication LSI 21 increases accordingly. For this reason, the entire vehicular communication device becomes large, and it becomes difficult to mount it on the vehicle. Further, as the circuit scale increases, the printed circuit board area also increases, which may lead to an increase in cost.

An object of the present invention is to provide a vehicular communication device which sets a communication address for each slave station based on a reference signal transmitted from a master station without providing an address setting device. is there.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to FIGS. 1 and 4 showing an embodiment. In the present invention, a plurality of slave stations 2A for driving and controlling a terminal device and communication with these slave stations 2A. It is applied to a vehicle communication device including a master station 1A that transmits information via a line L, and the master station 1A is configured to include a reference signal output unit 11 that outputs a reference signal of a predetermined frequency, and a slave station 2A. Oscillation means 22 and 204 for outputting reference clocks of different frequencies for each, and frequency comparison means 213 and 21 for comparing respective frequencies of the reference signal and the reference clock.
8 and address setting means 220 for setting a different communication address for each slave station 2A based on the comparison result by the frequency comparing means 213, 218.
By configuring A, the above object is achieved. According to a second aspect of the present invention, in the vehicle communication device according to the first aspect, the oscillation means 22, of the slave station 2A, outputs a reference clock having a frequency higher than the frequency of the reference signal.
204, and the address setting means 220 of the slave station 2A is configured to set a communication address according to the number of reference clocks included in a predetermined cycle of the reference signal. According to a third aspect of the present invention, in the vehicle communication device according to the first or second aspect, the frequency dividing unit 205A that divides the reference clock by the frequency division ratio according to the communication address to generate the divided clock. The slave station 2A is configured to include the master station 1A and the transmission control means 206A for transmitting information in synchronization with the divided clock. According to a fourth aspect of the invention, in the vehicular communication apparatus according to the third aspect, clock number measuring means 217 and 219 for measuring the number of divided clocks included in a predetermined cycle of the reference signal are measured. The slave station 2A is configured so as to include a determination unit 221 that determines whether or not information transmission with the master station 1A is possible based on the number of divided clocks, and the transmission control unit 20 of the slave station 2A.
6A configures the transmission control means 206A of the slave station 2A so as to output the determination result of the determination means 221 to the master station 1A. According to a fifth aspect of the invention, in the vehicle communication device according to the fourth aspect, communication data output means 1 for outputting communication data for information transmission with the slave station 2A.
2 and timing control means 13 for outputting a reference signal before outputting communication data, and for outputting communication data when the judging means 221 of the slave station 2A judges that information transmission with the master station 1A is possible. Thus, the master station 1A is configured.

[0012]

In the invention described in claim 1, the reference signal output from the reference signal output means 11 of the master station 1A is input to the frequency comparison means 213, 218 of the slave station 2A via the communication line L. The reference clocks output from the oscillating means 22 and 204 are also input to the frequency comparing means 213 and 218, and the respective frequencies of the reference signal and the reference clock are compared. This comparison result is input to the address setting means 220, and the address setting means 220 sets a different communication address for each slave station 2A. According to the second aspect of the invention, the oscillating means 22 and 204 output the reference clock having a frequency higher than the frequency of the reference signal, and the address setting means 220 measures the number of reference clocks included in a predetermined cycle of the reference signal. Then, the communication address is set according to this number. In the invention according to claim 3, the communication address set by the address setting means 220 and the oscillating means 2
The frequency dividing means 20 divides the reference clock output from 2, 204.
5A and divides the reference clock by a dividing ratio according to the communication address to create a divided clock. This divided clock is input to the transmission control means 206A, and information transmission with the master station 1A is performed in synchronization with this divided clock. In the invention described in claim 4, the clock number measuring means 21
7, 219 measures the number of frequency-divided clocks included in a predetermined cycle of the reference signal, and the measured value is the determination means 22.
Input to 1. The judgment means 221 judges whether or not information transmission with the master station 1A is possible based on the measured number of divided clocks, and the judgment result is output to the master station 1A by the transmission control means 206A. In the invention described in claim 5, the timing control means 13 controls the output timing of the reference signal output from the reference signal output means 11 and the output timing of the communication data output from the communication data output means 12. The timing control unit 13 first outputs the reference signal before outputting the communication data, and when the determining unit 221 of the slave station 2A determines that the information transmission with the master station 1A is possible, the timing control unit 13 outputs the communication data.

Incidentally, in the section of means and action for solving the above problems for explaining the constitution of the present invention, the drawings of the embodiments are used for making the present invention easy to understand. It is not limited to.

[0014]

1 is a block diagram of an embodiment of a vehicle communication device according to the present invention. In FIG. 1, the same components as those of the conventional vehicle communication device shown in FIG. 7 are denoted by the same reference numerals, and the differences will be mainly described below. 1A is a child station 2
A master station that performs data communication with A, and includes therein a reference signal generation circuit 11, a data generation circuit 12, and a control unit 13.
And a transmission circuit 14. Of these, the reference signal generation circuit 11 outputs a reference signal of a predetermined cycle for 5 cycles before performing data communication with the slave station 2A. This reference signal is input to each slave station 2A via the communication line L, and each slave station 2A sets a communication address using this reference signal. The data generation circuit 12 outputs data used for data communication with the slave station 2A. The control unit 13 controls the output timing of each signal output from the reference pulse generation circuit 11 and the data generation circuit 12.

The slave station 2A includes a communication LSI 21A and an oscillator 22.
And has no address setter unlike FIG. The oscillator 22 vibrates at a natural frequency having a different frequency for each slave station 2A. On the other hand, the communication LSI 21A includes a reception buffer 201, a filter circuit 202, and a reset circuit 203.
, Oscillator circuit 204, frequency divider circuit 205A, and control unit 2
It has 06A and an address setting circuit 207. Of these, the address setting circuit 207 is configured by the circuit of FIG. 4 described later, sets a communication address using a reference signal input through the communication line L, and sets this address to the frequency dividing circuit 205A and the control unit 206A. input. Frequency divider 205
A is a signal obtained by dividing an output (hereinafter, referred to as an original clock) from the oscillation circuit 204 by a division ratio according to the address value of the communication address from the address setting circuit 207 and a divided signal (hereinafter, referred to as a system clock). Call) to the system clock input terminal of the control unit 206A. After that, the control unit 2
06A operates by this system clock.

In FIG. 1, the master station 1A to each slave station 2A.
Although only the components that are relevant when transmitting data are shown in FIG. 1, data can be transmitted from each slave station 2A to the master station 1A. In this case, each slave station 2A sends data to the communication line L according to an instruction from the control unit 206A in the slave station, and this data is input to the control unit 13 of the master station 1A via the communication line L. Further, although only one slave station 2A is shown in FIG. 1, a plurality of slave stations 2A are actually connected to the master station 1A via the communication line L.

FIG. 2 is a flowchart showing the operation of the control unit 13 inside the master station 1A, and the operation of the master station 1A will be described based on this flowchart. When a power switch (not shown) is input, the control unit 13 starts the operation of the flowchart of FIG. In step S1 of FIG. 2, the reference signal output circuit 11 is instructed to output the reference signal. As a result, the reference signal output circuit 11 sends the reference signal to the communication line L. This reference signal is received by each slave station 2A,
Each slave station 2A sets a communication address according to the flowchart of FIG. 3 described later. After completing the setting of the communication address, each slave station 2A sends an address setting end signal to the communication line L.

In step S2, it is determined whether the address setting end signal is received within a predetermined time after the reference signal is transmitted. If the determination is negative, the process returns to step S1 and the reference signal is output again. On the other hand, all child stations 2A
When the address setting end signal is received from step S
In step 3, the data generation circuit 12 is instructed to output the address of the slave station (communication target slave station) with which communication is desired.
As a result, the data generation circuit 12 sends out the address of the communication target slave station to the communication line L. Each slave station 2A receives this address and determines whether this address matches the communication address of its own station, as described later. Then, the slave station 2A, which has determined that the address matches the address of its own station, sends an acknowledge signal to the communication line L.

In step S4, it is determined whether or not an acknowledge signal is received within a predetermined time. If the determination is negative, the process returns to step S3, and if the determination is positive, step S3.
In step 5, the data generating circuit 12 is instructed to send the communication data, whereby the data communication with the communication target slave station specified in step S3 is performed.

FIG. 3 is a flowchart showing the operation of the control unit 206A in the slave station 2A, and the operation of the slave station 2A will be described based on this flowchart. The process of the flowchart of FIG. 3 is also started by inputting a power switch (not shown). In step S11, the address setting circuit 2
The enable signal for starting the operation of 07 is set to the high level. As a result, the address setting circuit 207 starts its operation, and the communication address is set by the circuit of FIG. 4 described later. Then, the set communication address is input to the control unit 206A and the frequency dividing circuit 205A, the frequency dividing circuit 205A creates a system clock using this communication address, and inputs this system clock to the control unit 206A.

In step S12, the address setting circuit 20 outputs a setting end signal indicating that the address setting is completed.
It is determined whether or not it is input from 7. If the determination is negative, the process stays in step S12, and if the determination is positive, the process proceeds to step S13. In step S13, the enable signal is set to low level to stop the operation of the address setting circuit 207.

In step S14, an address setting completion signal is sent to the master station 1A via the communication line L. Step S
At 15, the address data sent from the master station 1A is received, and it is determined whether the address matches the communication address of the local station. If the determination is negative, the process stays in step S15, and if the determination is positive, the process proceeds to step S16, the acknowledge signal is sent to the communication line L, and the master station 1
A state in which data from A can be received (hereinafter referred to as a communication standby state) is set. After that, when communication data is transmitted from the master station 1A, the process proceeds to step S17, and data communication with the master station 1A is performed.

FIG. 4 shows the address setting circuit 207 shown in FIG.
FIG. 5 is a circuit diagram of an embodiment showing the details of FIG. 5, and FIG. 5 is a signal waveform diagram of each part inside the address setting circuit 207. The configuration and operation of the address setting circuit 207 will be described based on these figures.

As shown in FIG. 4, the address setting circuit 207 outputs a low level pulse when the rising edge of the reference signal is detected.
1 and a falling edge detection circuit 21 which outputs a high level pulse when the falling edge of the reference signal is detected.
2, a counter 213 that measures the number of rising edges of the reference signal, a decoder 214 that outputs a high-level signal only during a period when the measured value of the counter 213 is 2, and a decoder 214 that is at a high level only during a period when the measured value of the counter 213 is 4. And a decoder 215 that outputs a signal. The address setting circuit 207 of FIG. 4 includes a pulse generation circuit 216 that outputs a pulse of a predetermined width by the circuit of FIG. 6 described later, and a counter 217 that measures the cycle length of the reference signal using the original clock or the system clock. , A latch circuit 218 and a latch circuit 219 for latching the measured value of the counter 217
A conversion circuit 220 for converting the output of the latch circuit 218 into communication address data, and a decoder 2 for outputting a low level signal only when the output of the latch circuit 219 has a predetermined value.
21 and.

The operation of the address setting circuit shown in FIG. 4 will be described below. When a power switch (not shown) is input, the reset circuit 203 shown in FIG. 1 outputs a low-level reset signal. As a result, the counter 213 and the RS flip-flop 222 are reset, and the composite clock G1 outputs the original clock from the oscillation circuit 204 shown in FIG. Further, a high-level enable signal is input to the counter 217 from the control unit 206A shown in FIG. 1, whereby the counter 217 becomes operable and counts up each time the original clock is input.

Here, when the first reference signal pulse is input (time t1 in FIG. 5), the rising edge detection circuit 2
A low-level pulse is output from 11 and this pulse is input to the reset terminal of the counter 217 via the OR gate G2, whereby the counter 217 is once reset. After that, when the reset is released (time t2 in FIG. 5), the counter 217 restarts the measurement of the number of clocks of the original clock.

After a while (time t3 in FIG. 5), the pulse generation circuit 216 outputs a high level pulse as described later. 2 with this pulse being output
When the rising edge of the reference signal is input (time t4 in FIG. 5), a low level pulse is output from the OR gate G3. At this time, since the measured value of the counter 213 is 2, the output of the decoder 214 becomes high level and the output of the RS flip-flop 222 also becomes high level. Therefore, a low level pulse is output from the OR gate G4, and the latch circuit 2 is output by this pulse.
18 latches the measured value of the counter 217. That is, the latch circuit 218 measures the period length of one clock of the reference signal from time t1 to t4 using the original clock.

The output of the latch circuit 218 is the conversion circuit 220.
Is converted into a communication address and output. Also time t4
At this time point, the output of the RS flip-flop 222 becomes high level, so that the system clock is output from the composite gate G1, and thereafter the counter 217 measures the number of system clocks.

Next, when the third reference signal pulse is input (time t6 in FIG. 5), the rising edge detection circuit 21
The low level pulse is output from 1 and the OR gate G2, the counter 217 is reset once, and then the measurement is restarted. After that, a high level pulse is output from the pulse generation circuit 216 (time t7 in FIG. 5), 4
When the second reference signal pulse is input (time t in FIG.
8), a low-level pulse is output from the rising edge detection circuit 211 and the OR gate G2. At this time, since the measured value of the counter 213 is 4, the output of the decoder 215 goes high and the output of the RS flip-flop 222 also goes low. Therefore, OR
A low level pulse is output from the gate G5, and the latch circuit 219 latches the output of the counter 217 by this pulse. That is, the latch circuit 219 operates at the time t.
The period length of one clock of the reference signal from 6 to t8 is measured by the system clock.

The output of the latch circuit 219 is the decoder 221.
When the latched value that is input to the register matches a predetermined value, the decoder 221 outputs a low level signal. On the other hand, when the output of the decoder 221 does not become low level, that is, when the latched value and the predetermined value do not match, the time point when the fourth falling edge of the reference signal pulse is input (see FIG. 5). At time t9, a high level pulse is output from the AND gate G6 (dotted line waveform at time t9 in FIG. 5), and the counter 213 is reset via the NOR gate G7.

Next, when the fifth reference signal pulse is input (time t10 in FIG. 5), the output of the decoder 223 becomes high level, which shows that the address setting is completed in FIG. The control unit 206A is notified.

The operation of the address setting circuit 207 is summarized as above. The cycle length of one clock from the first clock to the second clock of the reference signal sent from the master station 1A is shown in FIG.
Measurement is performed with the original clock output from the oscillation circuit 204, and this measured value is set as the communication address of each slave station 2A. Next, the period length of 1 clock from the 3rd clock to the 4th clock of the reference signal is divided by the frequency dividing circuit 20 shown in FIG.
The system clock output from 5A is measured, and based on the measured value, it is inspected whether the reference signal and the system clock are normal.

As described above, since the address setting circuit 207 sets the communication address unique to each slave station 2A by using the reference signal from the master station 1A, the address setting device is not provided in the slave station 2A. You can also set the communication address. Further, since it is not necessary to provide the communication LSI with an address terminal for connecting to the address setter, the communication LS
The number of I input terminals can be greatly reduced, and the mounting area of the circuit that constitutes the slave station can be reduced and the cost can be reduced.

Further, since the system clock is created in the frequency dividing circuit 205A based on the address value of the communication address set by the address setting circuit 207, the system clock is sent from the master station 1A to each slave station 2A. There is no need, and the number of communication lines L can be reduced. Further, since the address setting circuit 207 checks whether the system clock and the reference signal from the master station 1A are normal, the reliability of data communication is improved.

FIG. 6 is a circuit diagram of an embodiment showing the details of the pulse generation circuit 216 shown in FIG. As shown in FIG. 6, the pulse generation circuit 216 includes inverters INV11,
INV12, transistor TR, capacitor C,
Comparators CP1 and CP2 and Schmitt inverter SIN
It consists of V and.

When the output of the OR gate G2 shown in FIG. 4 goes low, the output of the inverter INV11 shown in FIG. 6 goes high and the transistor TR turns on. Therefore, the electric charge accumulated in the capacitor C is discharged.
On the other hand, when the output of the inverter INV11 becomes low level, the transistor TR is turned off, the current from the constant current source B flows through the capacitor C, and the charge is accumulated. For example, when the rising edge of the reference signal is input to the address setting circuit 207 shown in FIG. 4 (time t1 in FIG. 5), a low level pulse is output from the OR gate G2 shown in FIG. The electric charge accumulated in the capacitor C is discharged, and the signal line L1 indicating the voltage across the capacitor C is discharged.
Potential becomes low level (see FIG. 5). This signal line L
1 is connected to the non-inverting input terminal of the comparator CP1 and the inverting input terminal of the comparator CP2, and the signal line L1 at this point
Is lower than both the voltage Vref1 at the inverting input terminal of the comparator CP1 and the voltage Vref2 at the non-inverting input terminal of the comparator CP2. Therefore, the output of the comparator CP1 is low level,
The output of the comparator CP2 becomes high impedance, and the output of the inverter INV12, that is, the pulse generation circuit 216.
Output goes low.

On the other hand, when the output of the OR gate G2 shown in FIG. 4 returns to the high level (time t2 in FIG. 5), the transistor TR is turned off and the electric charge is gradually accumulated in the capacitor C, and accordingly the signal line is changed. The potential of L1 becomes high. When the potential of the signal line L1 eventually exceeds the voltage value Vref1 of the non-inverting input terminal of the comparator CP1 (time t3 in FIG. 5), the output of the comparator CP1 becomes high impedance. On the other hand, since the potential of the signal line L1 immediately after the output of the comparator CP2 becomes high impedance is lower than the voltage value Vref2 of the non-inverting input terminal of the comparator CP2, the output of the comparator CP2 remains high impedance. Yes, after all comparators CP1, CP
The output of 2 becomes high level because of the pull-up resistor R. Therefore, the output of the pulse generation circuit 216 becomes high level.

After that, the potential of the signal line L1 changes to the comparator CP2.
When it exceeds the voltage value Vref2 of the inverting input terminal of the pulse generator (time t5 in FIG. 5), the output of the comparator CP2 becomes low level and the output of the pulse generating circuit 216 also becomes low level.

As described above, in the pulse generation circuit 216,
A high-level pulse signal is output every two cycles of the reference signal, and this pulse signal is used to latch the measurement value of the counter 217 shown in FIG.

In the above-mentioned embodiment, an example is shown in which the master station 1A previously recognizes the communication address set by the address setting circuit 207 in each slave station 2A, but each slave station 2A recognizes the communication address. After setting, the address is transmitted to the master station 1A via the communication line L, whereby the master station 1A
May recognize the communication address of each slave station 2A. In addition, steps S1 and S2 in the flowchart of FIG.
Then, until all the slave stations 2A finish address setting,
The master station 1A continues to output the reference signal, but ignores the slave station 2A whose address cannot be set and performs data communication after step S3 only for the slave station 2A whose address has been set. You may do it.

In the above embodiment, the address setting circuit 207 is used.
Although the example in which the frequency divider circuit 205A and the like are integrated into one LSI has been described, each circuit may be dispersed in a plurality of LSIs.
On the contrary, the communication LSI 21A shown in FIG. 1 may include another circuit such as a drive control circuit for driving an actuator or the like. In the above embodiment, the original clock output from the oscillator circuit 204 is divided by the divider circuit 205A to create the system clock, but the original clock may be used as it is as the system clock. In this case, the frequency dividing circuit 205 becomes unnecessary. In the above-mentioned embodiment, the reference signal is transmitted from the master station 1A for 5 cycles, and the communication address is set by using the first one of these, but the cycle length of a plurality of clocks of the reference signal is the original clock. Alternatively, the communication address may be set according to the measured value.

In the embodiment constructed as described above,
The reference signal generation circuit 11 is used as a reference signal output means for the oscillator 2.
2 and the oscillating circuit 204 serve as oscillating means,
And the latch circuit 218 is a frequency comparison means and a conversion circuit 22.
0 is the address setting means, the frequency dividing circuit 205A is the frequency dividing means, the control unit 206A is the transmission control means, and the counter 217.
The latch circuit 219 corresponds to the clock number measuring means, the decoder 221 corresponds to the judging means, the data generating circuit 12 corresponds to the communication data outputting means, and the controller 13 corresponds to the timing controlling means.

[0043]

As described in detail above, according to the present invention, the master station outputs the reference signal of the predetermined frequency to the slave station,
Since the communication address of the slave station is set based on the comparison result between the frequency of this reference signal and the frequency of the reference clock output from the oscillation means in the slave station, it is not necessary to provide an address setter in the slave station. Also, an address terminal for connecting the address setter and the communication LSI in the slave station is not required. This simplifies the circuits that make up the slave station,
The cost can be reduced. According to the second aspect of the present invention, the frequency of the reference clock is set higher than the frequency of the reference signal, so that the number of reference clocks included in a predetermined cycle of the reference signal can be used as the communication address. Setting can be done easily. According to the invention described in claim 3, since the divided clock is created according to the set communication address and the information is transmitted from the master station in synchronization with the divided clock, the information is transmitted from the master station. Since it is not necessary to output a clock for transmission, the number of communication lines is reduced. According to the invention described in claim 4, the number of divided clocks included in the predetermined period of the reference signal is measured, and it is determined whether or not information transmission with the master station is possible by this number.
Communication error can be detected without special equipment. According to the invention of claim 5, the master station outputs the reference signal before outputting the communication data, and after the communication address setting and the communication abnormality determination processing are completed in the slave station, the communication abnormality is detected. Since the communication data is output from the master station to the slave station only when there is no such problem, the reliability of data communication is improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a vehicle communication device according to the present invention.

FIG. 2 is a flowchart showing an operation of a control unit of a master station.

FIG. 3 is a flowchart showing an operation of a control unit of a slave station.

FIG. 4 is a circuit diagram of an embodiment of the address setting circuit shown in FIG.

FIG. 5 is a signal waveform diagram of each part of FIG.

6 is a circuit diagram of an embodiment of the pulse generation circuit shown in FIG.

FIG. 7 is a block diagram of a conventional vehicle communication device.

[Explanation of symbols]

 1A Master station 2A Slave station 11 Reference signal generation circuit 12 Data generation circuit 13 Control unit 14 Transmitter circuit 21A Communication LSI 205A Frequency divider circuit 206A Control unit 207A Address setting circuit

Claims (5)

[Claims] 1. A vehicle communication device comprising: a plurality of slave stations that drive and control a terminal device; and a master station that transmits information to these slave stations via a communication line, wherein the master station is a reference of a predetermined frequency. Reference signal output means for outputting a signal, the slave station, an oscillating means for outputting a reference clock having a different frequency for each slave station, and a frequency comparison means for comparing the reference signal and each frequency of the reference clock. A vehicle communication device comprising: an address setting unit that sets a different communication address for each slave station based on a comparison result by the frequency comparison unit. 2. The vehicle communication device according to claim 1, wherein the oscillation unit of the slave station outputs the reference clock having a frequency higher than the frequency of the reference signal, and the address setting unit of the slave station. The vehicle communication device, wherein the communication address is set according to the number of the reference clocks included in a predetermined cycle of the reference signal. 3. The vehicle communication device according to claim 1, wherein the slave station divides the reference clock by a division ratio according to the communication address to generate a divided clock. A vehicle communication device comprising: a frequency dividing unit; and a transmission control unit that performs information transmission with the master station in synchronization with the divided clock. 4. The vehicle communication device according to claim 3, wherein the slave station measures a clock number for measuring the number of the divided clocks included in a predetermined cycle of the reference signal, and the measurement. Based on the number of divided clocks determined, determining means for determining whether or not information transmission with the parent station is possible, the transmission control means of the slave station, the determination result by the determining means the parent A vehicle communication device characterized by outputting to a station. 5. The vehicle communication device according to claim 4, wherein the master station outputs communication data for outputting communication data for information transmission with the slave station, and outputs the communication data. A vehicle communication, comprising: a timing control unit that outputs the reference signal before and outputs the communication data when the determination unit of the slave station determines that information transmission with the master station is possible. apparatus.