JPH08274845A - Standby time controller for microcomputer - Google Patents

Abstract

PURPOSE: To provide a standby time controller for microcomputer with which fluctuation in the time constant of a time constant circuit composed of resistors and a capacitor can be suppressed. CONSTITUTION: The time constant circuit is constituted by connecting the node of any one of plural serial resistors from 24-2 to 24-n with a capacitor 17 based on the result of comparing the level period of one of rectangular waves provided by shaping the waveform of an output from a frequency divider 29 with a reference clock. Thus, the time constant of the time constant circuit can be kept constant and the standby time of a microcomputer 15 can be fixed. Therefore, by using this device as the slave set of a telephone, the calling state of a base unit is surely detected and a ring back tone can be emitted from a speaker 4 of the slave set.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer standby time adjusting device suitable for controlling the standby time of a microcomputer used in a cordless telephone handset or the like.

[0002]

2. Description of the Related Art At present, the telephone market has become active by the time a telephone consisting of a master unit and a slave unit is used in a general household. In order to expand the market for this type of telephone, it is inevitable to reduce the cost of the telephone itself. Therefore, recently, a master side connected to the telephone line and a slave side wirelessly communicated with the master side. There is also a low-priced model in which both the provision of a speaker for emitting a ringing sound is stopped and the speaker of the master unit side is omitted and the speaker is provided only on the slave unit side. In this case, the child device periodically determines whether the parent device is ready to accept an external call through the telephone line, and outputs the speaker of the child device only when it is accepted. In addition, it is necessary to configure a system between the master unit and the slave unit. Specifically, the slave unit has a microcomputer built therein, and the microcomputer determines whether or not the master unit is in the calling state of the telephone bell. Since the child device is a cordless type and is driven by a battery, it is necessary to use a microcomputer in consideration of the life of the battery. FIG. 2 is a diagram showing an example of a microcomputer that is built in and used in a child device.

In FIG. 2, (1) is a microcomputer, and outside the microcomputer (1),
A resistor (2) and a capacitor (3) and a speaker (4) connected in series between the power supply Vdd and the ground are provided. In particular, the connection point of the resistor (2) and the capacitor (3) is connected to the microcomputer (1). Connected to terminals (5) and (6),
Moreover, the input of the speaker (4) is connected to the terminal (7) of the microcomputer (1). The resistance (2)
And a capacitor (3) constitutes a time constant circuit having a fixed time constant.

In the inside of the microcomputer (1), reference numeral (8) is a Schmitt inverter having hysteresis, the input of which is connected to the terminal (5) and the terminal voltage of the capacitor (3), that is, the charging voltage of FIG. 3 (a). A discharge voltage (sawtooth voltage) is applied. Here, the Schmitt inverter (8) has two different threshold voltages, one high threshold voltage Vth is shown by a chain line, and the other low threshold voltage Vtl is shown by a chain line in FIG. . The resistance value of the resistor (2) and the capacity of the capacitor (3) are such that the charging / discharging period performed once is 1 sec.
Is set so that the charging / discharging operation is performed in a cycle of 1 sec. More specifically, the output of the Schmitt inverter (8) is 990 mse in one second cycle.
c is at a high level, so that the remaining 10 msec is at a low level, that is, charging is performed for 990 msec and then 1
The values of the resistor (2) and the capacitor (3) are determined so that the discharge is performed at 0 mesc. As a result, as a result, the output of the Schmitt inverter (8) becomes as shown in FIG.
As shown in (1), the level becomes high for 990 msec and low level for 10 msec within 1 sec.
(9) is a hold control unit, which receives this high level output from the Schmitt inverter (8)
When the microcomputer (1) is set to the hold mode (standby state) for msec and the low level output of the Schmitt inverter (8) is received, this 10 m
The microcomputer (1) is brought into a normal operation state only for the sec period. This hold control section (9)
In detail, it is a part that performs software processing, and when the output of the Schmitt inverter (8) is recognized as a high level, an interrupt signal is generated, and at this time, a ROM (not shown)
Based on the result of decoding the program data read from, the microcomputer (1) is set to the hold mode for performing the minimum necessary operation to reduce the current consumed by the microcomputer (1). Further, when the hold control section (9) recognizes the output of the Schmitt inverter (8) as a low level, another hold signal is generated,
At this time, the microcomputer (1) is set to the normal operation state based on the result of decoding the program data read from the ROM.

Reference numeral (10) is a call determination unit, which is a circuit unit (not shown) in the preceding stage for carrying out communication signal processing with the master unit built in the slave unit, and the master unit now makes a call at the request of the other party. In order to do so, it receives a signal indicating whether or not it is in a calling state, and controls a charge / discharge control unit described later.
The determination operation of the read determination unit (10) is performed during the 10 msec period during which the microcomputer (1) normally operates. (11) is the charge / discharge control unit described above, and first receives the output of the Schmitt inverter (8) and controls the charge / discharge of the capacitor (3). Reference numeral (12) is an N-channel MOS transistor (hereinafter referred to as an NMOS transistor) that forms a discharge path of the terminal voltage of the capacitor (3), the gate is connected to the output of the charge / discharge control unit (11), and the drain is the terminal. It is connected to the non-grounded side of the capacitor (3) via (6), and the source is grounded. When the output of the Schmitt inverter (8) is at a high level, the charge / discharge control unit (11) basically outputs a low level discharge prohibition signal (for example, 0 volt), and the NMO
The S transistor (12) is turned off to continue the charging operation of the capacitor (3). On the other hand, when the output of the Schmitt inverter (8) is at a low level, a high level discharge permission signal (for example, 5 volts) is output to turn on the NMOS transistor (12) to discharge the electric charge of the capacitor (3). Further, when an output indicating "no call" is applied to the charge / discharge control unit (11) from the call determination unit (10), the charge / discharge control unit (11) outputs a signal output based on the output of the Schmitt inverter (8). To do. On the other hand, when the call determination unit (10) obtains an output indicating "calling", the charge / discharge control unit (11) ignores the output of the Schmitt inverter (8) and continues to output only the discharge inhibition signal. That is, the output of the Schmitt inverter (8) is finally fixed to the low level, and the microcomputer (1) continues the normal operation state. Reference numeral (13) is a ringing tone generating section, which receives a "calling present" output from the calling determining section (10) and generates a ringing tone. The ringing tone output from the ringing tone generator (13) is output from the terminal (7) via the buffer (14) and is emitted from the speaker (4).

The microcomputer (1) configured as described above is built in the slave unit, but the signal for making a call sent from the telephone line to the master unit is usually 1
It is intended to ring a ringing sound at intervals of sec. Therefore, if the microcomputer (1) repeatedly executes each cycle consisting of the hold mode and the normal operation mode every 1 sec in accordance with the time constant of the time constant circuit, it will be intermittently performed in the 10 msec period of the normal operation mode. Make sure to determine whether the base unit is in the calling state,
A ringing tone can be emitted from the speaker (4) without fail at the timing of calling.

[0007]

By the way, in the above-mentioned conventional technique, the resistor (2) and the capacitor (3) are external parts to the microcomputer (1), and ideally, they are charged and discharged in a cycle of 1 sec. It is a fixed time constant in which the resistance value and the capacitance are selected to perform. However, in practice,
The time constant changes due to factors such as fluctuations in the power supply Vdd and temperature changes. If this time constant changes,
The charging / discharging cycle deviates from 1 sec, and the high and low level periods of the Schmitt inverter (8) fluctuate accordingly. In particular, when the time constant becomes large and the high level period of the Schmitt inverter (8) continues for 1 sec or more, the main unit is in the calling state for 1 s.
In the ec period, there may be a defective timing in which the microcomputer (1) cannot shift from the hold mode to the normal operation mode, and there is a problem that the speaker (4) cannot emit the ringing tone at this defective timing.

In order to suppress the fluctuation of the time constant, a crystal resonator having a small fluctuation has been conventionally used, but this is not a preferable measure because of the problem of high cost. Therefore, it is an object of the present invention to provide a standby time adjustment device for a microcomputer capable of suppressing fluctuations in the time constant of a time constant circuit composed of resistors and capacitors.

[0009]

The present invention has been made to solve the above-mentioned problems, and is characterized by a reference clock generating section for generating a reference clock based on an oscillation clock. , A plurality of series resistors forming a time constant circuit by connecting a capacitor to any one of the connection points connected in series, and controlling the charging / discharging operation of the time constant circuit and the time constant. An original clock generator that generates an original clock corresponding to the charging / discharging cycle of the circuit, a frequency divider that divides the original clock by a predetermined frequency, the output of the frequency divider is waveform-shaped, and one cycle output is set to a predetermined duty. A duty setting section, a comparing section for comparing one level period of one cycle output of the frequency divider with the reference clock, and connection of any one of the plurality of series resistors based on the output of the comparing section. point Includes a resistance switching section for connecting to the capacitor, and a hold control section for the microcomputer in the standby state based on the output of the frequency divider, a,
The point is that the cycle of the charge / discharge output of the time constant circuit is controlled so that the standby time of the microcomputer corresponding to one or the other level period of one cycle output of the frequency divider is made constant.

[0010]

According to the present invention, based on the result of comparison between one level period of one cycle output of the frequency divider and the reference clock, one of the plurality of series resistors is connected to the capacitor to connect the time constant. The circuit is configured. As a result, the time constant of the time constant circuit can be kept constant, and the standby time of the microcomputer can be kept constant. Therefore, if the device of the present invention is used in a slave unit of a telephone, the calling state of the master unit can be reliably detected and a ringing tone can be emitted from the speaker of the slave unit. Further, the capacity of the capacitor connected to the microcomputer can be reduced, which also contributes to cost reduction.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing a standby time adjusting device for a microcomputer according to the present invention. In addition, in FIG.
The same numbers are given to the same configurations as those and the description thereof is omitted.

In FIG. 1, reference numeral (15) is a microcomputer, and a vibrator (16) such as ceramic and a capacitor (1) are provided outside the microcomputer (15).
7) is provided. Both ends of the vibrator (16) are connected to the terminals (18) and (19), and one end of the capacitor (17) on the non-grounded side is connected to the terminal (20). Now,
Inside the microcomputer (15), (21)
Reference numeral (22) is an inverter and a resistor connected in parallel, and both ends thereof are connected to terminals (18) and (19).
An external oscillator (16) and an internal inverter (21)
And the resistor (22) constitutes an oscillator. For example, if the oscillation frequency of the oscillator (16) is 4 MHz,
A rectangular original clock of 4 MHz is generated from the output of the inverter (21). Reference numeral (23) is a reference clock generator, which divides an original clock of 4 MHz into, for example, 4 and outputs 1 MHz.
That is, a reference clock having a period of 1 μsec is generated.

On the other hand, (24-1) to (24-n) are resistors connected in series, and one end of the resistor (24-1) is connected to the power supply Vdd. The resistors (24-1) to (2
The resistance values of 4-n) are the same in this embodiment. Further, transmission gates (25-1) to (25-) are connected to the connection points of the resistors (24-1) to (24-n), respectively.
-N) is connected to one end, and the other ends of the transmission gates (25-1) to (25-n) are commonly connected to each other and connected to the non-grounded side of the capacitor (17) via the terminal (20). There is. That is, by selecting any one of the transmission gates (25-1) to (25-n) by the resistance switching unit described later, the resistances (24-1) to (2-1) are selected.
N by any one of 4-n) and the capacitor (17)
This makes it possible to configure various types of time constant circuits.

Further, (26) is a Schmitt inverter having two different threshold voltages Vth and Vtl, and its input is connected to the terminal (20). (2
7) is an NMOS transistor forming a discharge path of the time constant circuit, the drain of which is connected to the terminal (20) and the source of which is grounded. In particular, the gate of the NMOS transistor (27) is connected to the output of the Schmitt inverter (26) via the inverter (28), and on / off control is performed based on the output of the Schmitt inverter (26). As a result, a waveform that repeats charging and discharging is obtained at both ends of the capacitor (17).

The operation of obtaining the terminal voltage of the capacitor (17) will be described with reference to FIG. Incidentally, FIG.
(A) is the charge / discharge output of the capacitor (17), FIG. 4 (b)
Represents the output of the Schmidt inverter (26), and FIG. 4 (c) represents the output of the inverter (28). When the capacitor (17) starts charging according to the time constant of the time constant circuit and its terminal voltage reaches the high threshold voltage Vth, the output of the Schmitt inverter (26) becomes low level. Along with this, the output of the inverter (28) becomes high level, the NMOS transistor (27) is turned on, and the terminal voltage of the capacitor (17) is rapidly discharged. At this time, the terminal voltage of the capacitor (26) instantly reaches the low-side threshold voltage Vtl,
The output of the Schmitt inverter (26) immediately becomes high level, the NMOS transistor (27) is turned off, and the capacitor (17) starts charging again according to the time constant. By repeating this operation, the capacitor (1
A sawtooth charge / discharge voltage is obtained on the non-grounded side of 7).
The frequency of one charge / discharge appearing at the terminal (20) is 13
The time constant of the time constant circuit is determined so that it becomes 0 Hz.
For example, the capacitance of the capacitor (17) may be an external component having a very small value of 0.01 μF.

(29) is a Schmitt inverter (26)
It is a frequency divider that divides the output of. The frequency divider (29) is
256 to divide 130Hz (about 7.7msec)
For example, eight T flip-flops (not shown) are connected in series to perform frequency division. (30) is a control unit,
The frequency-divided output of the frequency divider (29) originally has a waveform obtained by dividing the original clock with one cycle of 130 Hz by 256, but the frequency-divided output of the frequency divider (29) is a low level period of 990 msec and a high level period of 10 msec. The waveform is shaped into 1 and the duty ratio of the 1-divided output is set to 99: 1. This operation will be described with reference to FIG. In addition, in FIG.
(A) is the output of the Schmidt inverter (26), (b)
Represents the output of the frequency divider (29). First, when the output of the Schmitt inverter (26) is divided by 256 while the frequency divider (29) is reset, the frequency divider (29)
The output of is kept low level until the output of 128 cycles of the Schmitt inverter (26) elapses. This low level period is a period in which 7.7 msec is added by 128 cycles, which is about 990 msec. After that, the frequency divider (2
9) The output rises to high level. The control unit (30) incorporates a timer (not shown), counts 10 msec from the time when the high level output of the frequency divider (29) is received, and after counting 10 msec, the overflow signal is divided by the frequency divider (29). Output to. This overflow signal becomes the reset signal RST of the frequency divider (29). Therefore,
Since the output of the frequency divider (29) falls to the low level upon receiving the reset signal RST, a waveform of 1 sec in which one cycle is a combination of the low level for 990 msec and the high level for 10 msec is repeatedly output. Ideally, the output of the Schmitt inverter (26) is 130Hz.
However, in practice, the output of the Schmitt inverter (26) may fluctuate from 130 Hz due to the influence of variations in temperature and element characteristics. Therefore, the following configuration is required to suppress this fluctuation.

Reference numeral (31) is a measuring unit for comparing the reference clock from the reference clock generating unit (23) with the low level output period from the frequency divider (29). Ideally, since the low level period of the frequency divider (29) is 990 msec, the reference clock having a period of 1 μsec is 9 msec during this period.
The basic condition is that there are 90000 pieces. The measurement unit (31) counts the number of reference clocks that fall within the low level output period of the frequency divider (29). Reference numeral (32) is a determination unit that determines whether the number of reference clocks measured by the measurement unit (31) is more or less than 990000. The n-bit table data read from the ROM (not shown) is converted into a resistance switching unit (to be described later) including an n-bit register according to how much or less the number of reference clocks is relative to 990000. To be set to. Here, the measurement unit (31) and the determination unit (32) are software-processed based on the program data from the ROM within the above-mentioned 990 msec period in the normal operation mode.

(33) is the resistance switching unit described above, to which n-bit table data from the ROM is set. Each bit of this table data is connected to each control terminal of transmission gates (25-1) to (25-n). That is, of n bits of table data,
Only 1 bit becomes "1", only the transmission gate suitable for setting the charging / discharging cycle of the time constant circuit to 7.7 msec is opened, and the connection point of a plurality of series resistors corresponding to the transmission gate is a terminal. It is connected to the non-grounded side of the capacitor (17) via (20).
From the above, a plurality of series resistors (24-1) to (24-n) connected to the capacitor (17) to form a time constant circuit
Since it is possible to switch the power supply Vdd fluctuation and ambient temperature change,
Further, even if the element characteristics of the Schmitt inverter (26) vary, the Schmitt inverter (26)
Can always output 130 Hz. That is, the frequency divider (2
From 9), always low level and 1 for 990 msec.
It is possible to obtain an output that repeats one cycle (1 sec) in which the level becomes high only for 0 msec.

Numerals (34) and (35) are a resistor and an NMOS transistor connected in series between the power source Vdd and the ground, and the gate of the NMOS transistor (35) is connected to the output of the control section (30). The control unit (30)
The output of the frequency divider (29) is low level 990 mse
During period c, a high level control signal is output and the frequency divider (2
During the 10 msec period when the output of 9) is high level, a low level control signal is output. (36) is a hold control unit, the input of which is an NMO via an inverter (37).
It is connected to the drain of the S transistor (35).
That is, as shown in FIG. 3B, the input of the hold controller (36) becomes high level when the NMOS transistor (35) is turned on during a low level period of 990 msec of the frequency divider (29), and the 10 msec of the circumference (29)
During the high level period, the level becomes low as the NMOS transistor (35) is turned off.

When the hold controller (36) receives the high level output from the inverter (37), it
When the microcomputer (15) is set to the hold mode (standby state) for 0 msec and the low level output of the inverter (37) is received, this 10 ms
The microcomputer (15) is put into a normal operation state only for the ec period. The hold control unit (36)
More specifically, it is a part that performs software processing, and when the output of the inverter (37) is recognized as a high level, an interrupt signal is generated, and the microcomputer (15) based on the decoding result of the program data read from the ROM at this time. The current consumed by the microcomputer (15) is reduced as a hold mode in which the minimum operation is performed. Further, the hold controller (3
When 6) recognizes the output of the inverter (37) as a low level, another interrupt signal is generated, and based on the decoding result of the program data read from the ROM at this time,
The microcomputer (15) is brought into a normal operation state.

From the above, the output of the frequency divider (29) can be a waveform having a constant duty irrespective of power supply fluctuations, ambient temperature changes, and variations in element characteristics. Therefore, the microcomputer (15) of this embodiment can be used. If it is built into the slave unit of the telephone and is operated intermittently, it can be surely detected whether or not the master unit is in the ringing state without making a detection error, and the speaker of the slave unit (4) in synchronization with the call of the master unit. It is very suitable because it can emit a ringing tone. Further, since the frequency divider (29) is provided, the capacity of the capacitor (17) externally connected to the microcomputer can be reduced, which contributes to cost reduction.

[0022]

According to the present invention, the connection point of any one of a plurality of series resistors is based on the result of comparison between one level period of a rectangular wave obtained by shaping the frequency divider output and the reference clock. Is connected to a capacitor to form a time constant circuit. As a result, the time constant of the time constant circuit can be kept constant, and the standby time of the microcomputer can be kept constant. Therefore, if the device of the present invention is used in a slave unit of a telephone, there is an advantage that the calling state of the master unit can be reliably detected and a ringing tone can be emitted from the speaker of the slave unit. Furthermore,
Since the capacity of the capacitor forming the time constant circuit can be small, it also contributes to cost reduction.

[Brief description of drawings]

FIG. 1 is a diagram showing a device of the present invention.

FIG. 2 is a diagram showing a conventional device.

FIG. 3 is a waveform diagram showing a charge / discharge waveform and a rectangular waveform in FIG.

FIG. 4 is a waveform diagram showing a main waveform of FIG.

5 is a waveform chart showing another main waveform of FIG. 1. FIG.

[Explanation of symbols]

 (17) Capacitor (23) Reference clock generator (24-1) to (24-n) Series resistance (26) Schmitt inverter (27) (35) NMOS transistor (29) Divider (30) Control section (31 ) Measuring unit (32) Judgment unit (33) Resistance switching unit (36) Hold control unit

Claims (2)

[Claims] 1. A plurality of reference clock generators that generate a reference clock based on an oscillation clock, and a plurality of units that form a time constant circuit by connecting in series any one of the connection points and a capacitor. A series resistor, an original clock generator that controls the charge / discharge operation of the time constant circuit and generates an original clock corresponding to the charge / discharge cycle of the time constant circuit, and a divider that divides the original clock by a predetermined frequency. A duty setting unit that shapes the output of the frequency divider to set a one-cycle output to a predetermined duty; a comparison unit that compares one level period of the one-cycle output of the frequency divider with the reference clock; A resistance switching unit that connects any one of the plurality of series resistors to the capacitor based on the output of the comparison unit; and a microcomputer based on the output of the frequency divider. And a hold control unit for setting a standby state of the microcomputer for controlling the cycle of the charge / discharge output of the time constant circuit to correspond to one or the other level period of one cycle output of the frequency divider. A standby time adjustment device for a microcomputer, which is characterized by a constant value. 2. The standby time adjustment device for a microcomputer according to claim 1, wherein the comparison unit performs a comparison operation only for a predetermined one cycle of a plurality of cycles of charge / discharge output of the time constant circuit. .