JPS59100655A - Transmission system - Google Patents

Abstract

PURPOSE:To prevent interference and to improve the transmission speed by transmitting a signal after a certain time is elapsed from the time when the signal supplied from a signal source is not transmitted, in the system transmitting signals from plural signal sources via a common line. CONSTITUTION:A logical signal supplied from a processing circuit 8 is led to a transmission circuit 5 in a slave station 2, and when the signal is a signal specifying the slave station 2 set in a unit code setting circuit 4, a high-frequency signal is superimposed on the logical signal in response thereto and gives the result to a power line 1. The receiving circuit 6 receives a high-frequency signal on the power line 1 to discriminate whether or not the logical signal given from the processing circuit to a transmission circuit 5 is coincident with a receiving signal given to the processing circuit 8. When coincident, the transmission is finished. A master station 3 receives the high-frequency signal superimposed on the power line 1, reads said signal into the processing circuit 11 and displays said signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmission method in which signals are transmitted from a plurality of signal sources via a common line. The present invention relates to a transmission method suitably implemented for the purpose of the present invention.

Traditionally, in order to prevent crime and fire inside a building, a slave station detects when a window or door opens or a fire breaks out, and then superimposes a high-frequency signal on the master station using existing power lines. A transmission method has already been proposed. Conventionally, in such a transmission system, when signals are simultaneously transmitted from a plurality of slave stations and a collision occurs, the master station cannot distinguish between the signals. To solve this problem, the master station sequentially sends out polling address signals to call the desired slave stations, and each slave station receives this polling address and selects the address that matches the preset address. The addressed slave station is configured to transmit a signal when the addressed slave station sends a signal. Such prior art has a problem in that when a large number of slave stations are provided, it takes a long time to perform one round of polling.

An object of the present invention is to provide a transmission method that prevents interference by transmitting signals from multiple signal sources such as slave stations onto a common line without causing collisions, and improves transmission speed. be.

FIG. 1 is an overall system diagram of an embodiment of the present invention. A plurality of slave stations 2 are connected to a commercial power line 1 already installed in a building. A master station 3 is also connected to this power line 1 . The slave station 2 has a function of detecting the opening of a window or door or detecting the occurrence of a fire, for example, in order to prevent crime and fire in a building.

FIG. 2 is a block diagram showing a specific configuration of the slave station 2. As shown in FIG. The slave station 2 includes a unit code setting circuit 4 in which a unit code for individually specifying the slave station 2 is set.
is provided. The power line 1 includes a transmitting circuit 5 for performing power line transport and a receiving circuit 6 for performing power line transport.
and a clock generation circuit 7 that detects the waveform of the voltage of the power line 1 every half cycle and generates a clock signal. These circuits 4 to 7 are connected to a processing circuit 8 including a microcomputer and the like.

FIG. 3 is an electrical circuit diagram showing a specific configuration of the transmitting circuit 5 and the receiving circuit 6. As shown in FIG. The slave station 2 and the master station 3 are connected via the power line 1 as described above, and power is supplied to the power line 1 from a single common transformer. The transmitting circuit 5 includes an inverting amplifier circuit 22 made of a complementary metal oxide film semiconductor, a crystal oscillator 23, a resistor R1, and a capacitor C.
I and C2 constitute an oscillation circuit 24. The output from this oscillation circuit 24 is waveform-shaped by two inversion circuits 25126, and is applied to transistor Q1 via resistor R2. Transistor Q1 is connected to a coil 28 of transformer 27, and this coil 28 is connected to capacitor C3.
are connected in parallel, thus configuring the excitation circuit 30. The coil 29 of the transformer 27 includes a transistor Q2.
Q3, capacitor C4 and coil 33 of transformer 31
are connected to form a power amplification circuit 32. The output from the coil 34 of the transformer 31 is connected to capacitors C5 and C6.
is sent out to the power line 1 via. A transistor Q4 is connected to a resistor R3 in the power amplifier circuit 32. A processing circuit 8 is connected to this transistor Q4 via a resistor R4.
The logic signal to be sent from is derived. The transistor Q4 is turned on and off by the logic signal from the processing circuit 6, so that the power is transmitted from the power amplifier circuit 32 to the power line 1.
A high frequency carrier wave generated by the oscillation circuit 24 is superimposed on the signal.

In the receiving circuit 6, the high frequency signal from the power line 1 is applied to the coil 54 of the transformer 53 via capacitors C7 and C8. This signal is selectively filtered by a tuned circuit 36 formed by coil 35 of transformer 53 and capacitor C9.

The output from this tuning circuit 36 is amplified by an inverting amplifier circuit 37 and a resistor R5 via a capacitor C10, and is also amplified by resistors R6, R7 and amplifier circuits 38 and 39, and envelope-detected by a detection circuit 40.

This detection circuit 40 includes a diode D1, a resistor R8,
and a capacitor C11. The envelope-detected output in the detection circuit 40 is inverted by the inverting circuit 41,
It is amplified by resistors R9 and R1O and amplifier circuits 42 and 43, and is input to the processing circuit 6. The circuit constituted by the resistor R6R7 and the amplifier circuit 38.39, and the circuit constituted by the resistor R9, RIO and the amplifier circuit 42.43 function as a Schmitt circuit having a level discrimination function, thereby also performing waveform urn operation. It will be done again.

FIG. 4 is a block diagram showing a specific configuration of the master station 3. As shown in FIG. The power line 1 includes a transmission circuit 9 for power line transport,
A receiving circuit 10 for power line transport is connected thereto. These transmitting circuit 9 and receiving circuit 10 are connected to a processing circuit 11 including a microcomputer and the like. The output from the processing circuit 11 is given to a display circuit 12 for visual display, and an acoustic display to generate an alarm when a window or door is opened or when a fire occurs.

The transmitting circuit 9 has a similar configuration to the transmitting circuit 5 of the slave station 2,
The receiving circuit 10 has a similar configuration to the receiving circuit 6.

5 and 6 are waveform diagrams for explaining the operation of the above embodiment, respectively, and FIG. 7 is a flow chart for explaining the operation of the processing circuit 8 in the slave station 2. FIG. 5(1) shows the waveform of the voltage supplied to the power line 1 from the commercial power transformer. In this embodiment, each half period of the voltage is a unit of one bit, and the reference character is indicated by b followed by a number.

When a signal is derived to the power line 1 during the first half of the period until the peak value of each voltage is reached in each bit, the logic is “1”.
'', and it is defined that when a signal is derived in the latter half of the period from the time of the peak value, it represents logic "0".

In the slave station 2, a logic signal shown in FIG. 5(2) is derived from the processing circuit 8 to the transistor Q4 of the transmitting circuit 5 via the resistor R4. This logic signal consists of a start signal B1 that is at a high level for the entire period of 1 bit b1, and a unit code signal that follows it! +2.

The unit code signal s2 is the unit code setting circuit 4.
For example, in this embodiment, the binary number r010010J representing 4 is a signal specifying the slave station 2 set by
This means that the slave station 2 from which the unit code signal 82 shown in FIG. 5(2) was derived is named No. 4.

The transmitting circuit 5 superimposes and applies a high frequency signal to the power line 1 in response to the logic signal shown in FIG. 5(2) from the processing circuit 8, so that the waveform of the power line 10 is as shown in FIG. 5(4). become.

In the receiving circuit 6, the detection circuit 40 receives the high frequency signal shown in FIG. 5(5). The fifth wave detected by this
The signal shown in FIG. 6 is applied to the processing circuit 8.

The signal shown in FIG. 5(6) is the same as the signal shown in FIG. 5(2). The processing circuit 8 moves from step n1 to step n2 in FIG. 6 and determines whether or not there is a signal on the power line 1. If there is no signal, the processing circuit 8 goes to step n6 and performs the process shown in FIG. 5 (4) as described above. The signal that is transmitted is derived to the power line 1. In step n7, it is determined whether or not the logic signal given from the processing circuit 8 to the transmitting circuit 5 matches the received signal given to the processing circuit 8 from the receiving circuit 6. If they match, the process proceeds to step n9. Ends the sending operation.

In the master station 3, the receiving circuit 10 receives the high frequency signal superimposed on the power line 1 as shown in FIG. 5(4), and the processing circuit receives a signal similar to the signal shown in FIG. 5(6). 11
Load into. This decodes the unit code signal B2, identifies which slave station 2 has generated the signal, and displays it on the display circuit 12.

For example, in what is named slave station No. 7 of slave station 2,
As shown in FIG. 5(3), it is assumed that at time t1, the processing circuit 8 determines that a signal should be sent. At this time, in step n2, the seventh device determines whether or not there is a high frequency signal from another slave station 2 on the power line 1. 4
Since the high frequency signal from Unit 7 has already been generated,
In the No. 4 machine, the half period of the voltage waveform immediately after that is counted from time t2 by the output of the clock generation circuit 7 in step n3, and the value at time t3 until the high frequency signal from the No. 4 machine disappears is provided in the processing circuit 8. Store to counter. Next, in step n4, it is determined whether or not a high frequency signal is superimposed on the power line 1, and if it is not superimposed, the process moves to step n5, and a time t4 delayed from time t3 by the count value 5 stored in the counter is determined. . In the No. 7 car, at this time t4, the start signal s3 and the unit code signal B4 specifying the No. 7 car are sent.
is sent out from the processing circuit 8. In this way, a voltage waveform on which a high frequency signal is superimposed is obtained from the transmitting circuit 5 of the seventh machine to the power line 1, as shown in FIG. 5(4).

Since there are a plurality of slave stations 2, there is a high probability that the time tl at which the processing circuit 8 of each slave station 2 should perform the sending operation is shifted by one bit or more in most cases. Therefore, there is a high probability that the number of bits from time t2 immediately after time t1 to time t3 when signal transmission from another slave station 2 is completed is different from each other. Since the delay after time t3 is made by the counted number of bits, collision of signals on the power line 1 can be avoided as much as possible.

Referring to Fig. 6, the voltage waveform of power line 1 is shown in Fig. 6 (1).
It is assumed that the logic signal shown in FIG. 6(2) is derived from the processing circuit 8 of the fourth slave station 2 in the direction of the transmitting circuit from the fourth slave station 2. As a result, the transmitting circuit 5 superimposes a high frequency signal on the power line 1 as described above, and as a result, the waveform of the power line 1 becomes as shown in FIG. 6(5). In the receiving circuit 6, the waveform shown in FIG. 6 (6) is given to the detection circuit 40, and thereby the logic signal shown in FIG. 6 (7) is given from the receiving circuit 6 to the processing circuit 8. Figure 6 (6) and Figure 6 (7)
) is generated in the receiving circuit 10 of the master station 3.

FIG. 6 (
Assume that the logic signals shown in (3) and (4) in FIG. 6 are respectively sent out. Processing circuit 8 in the first machine
It is assumed that the time t5 when the processing circuit 8 of the sixth machine attempts to send a signal and the time tlO when the processing circuit 8 of the sixth machine attempts to send a signal are included in the same bit, and are, for example, the same time. In the No. 1 and No. 6 machines, each clock generation circuit 7 counts the number of bits until the signal from the No. 4 machine is sent out, and in this embodiment, only one bit is counted from time t6 to tll. Time t7. At t12, the start signal 85°a7 and the unit code signal a6+s8 are sent out in this order from the first and sixth machines. In the No. 1 and No. 6 machines, it is determined in step n7 that the transmission signal that they sent out and the received signal that they received do not match, and therefore, in step n8, the time t8. From t13, the unit code of each slave station 2 is stored in a counter provided in the processing circuit 8. In the first machine, the value stored in the counter of the processing circuit 8 is "1", and in the fourth machine, the value is "6". In the No. 1 machine, from time t8, the start signal B5 and the unit code are delayed by 1 bit of the value corresponding to the No. 1 machine at step n3.

- the code signal 86 is sent out again. At Unit 6, time t13
At time t14, when 6 bits corresponding to the value "6" have passed since then, the processing circuit 8 performs the operation of step n2. At this time, since a signal is being sent from the first machine to the power line 1, the number of bits 2 until the high frequency signal from the first machine ends is counted in step n3. That is, at time t14 in the No. 6 machine, it is detected in step n2 that the high frequency signal is being sent to power #1 from the No. 1 machine, and in step n3, the transmission of the signal from the No. 1 machine ends at time t15. The number of bits up to 2 is counted. At time t15, the sending of the high frequency signal from No. 1 to power line 1 ends, so next No. 6 is delayed by 2 bits counted from t14 to t15 at time t16t, and from this time t16, the start signal black 9 is delayed. and a unit code signal slO representing the No. 6 machine. In this way, from No. 1 and No. 6, time t7.
Even if the signal is sent to power line 1 at the same time at t12,
At time t8. when the number of bits 1 and 6 of the unit code represented by the No. 1 and No. 6 units ceases to be transmitted on the power line 1. Since the transmission was delayed from t13,
Collisions on the power line 1 are avoided.

In the embodiments described above, the present invention has been described in connection with a system in which a high frequency signal is superimposed on a power line, but the present invention can also be practiced in connection with a system in which transmission is performed using a leased line instead of a power line. be able to.

As described above, according to the present invention, a signal is sent from a slave station to a master station without a polling operation from the master station, so that the transmission speed can be improved. Also, collision of signals from slave stations on the transmission line is avoided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the specific configuration of the slave station 2,
3 is an electric circuit diagram showing the specific configuration of the transmitting circuit 5 and receiving circuit 6 in FIG. 2, FIG. 4 is a block diagram showing the specific configuration of the master station 3, and FIGS. 5 and 6 7 is a waveform diagram for explaining the operation of the above-described embodiment, and FIG. 7 is a flow chart for explaining the operation of the processing circuit 8 in the slave station 2. In FIG. 1... Power line, 2... Slave station, 3... Master station, 4...
・Unit code setting circuit, 5, 9... Transmission circuit, 6
, 10... Receiving circuit, 7... Clock generation circuit, 8
, 11... Processing circuit, 12... Display circuit Fig. 2 Fig. 4

Claims (1)

[Claims] In a transmission system that transmits signals from a signal source via a common line, it detects that a signal is being sent from the signal source that is a line, and performs a predetermined operation to send the signal. It is characterized by measuring the time from the time to the time when the signal from the signal source consisting of the above is no longer transmitted, and transmitting the signal when the above-mentioned time has elapsed after the time when the signal from the signal source consisting of the aforementioned ceases to be transmitted. Transmission method.