JPH07264257A - Pi/4 shift qpsk synchronization circuit - Google Patents

Abstract

PURPOSE:To reduce the size of the circuit and to adapt the circuit for circuit integration processing by reducing the circuit scale of the pi/4 shift QPSK syn chronization circuit. CONSTITUTION:An IF signal is given to a distributer 1, in which the signal is distributed into two, each is modulated with an orthogonal local signal obtained from an output of a VCO 2 at a 90 deg. distributer 3 by balanced modulators 4-1, 4-2 and I, Q signals are obtained through LPFs 5-1, 5-2. The I, Q signals are binary-shaped at comparators 6-1, 6-2 and signals (i), (q) are outputted. On the other hand, the quantity of the signal I and that of the signal Q-bar are compared and the quantity of the signal I and that of the signal Q are compared to obtain an output of signals i', q'. An output of an exclusive OR (9-4) between a symbol rate 1/2 clock signal and an exclusive OR (9-3) (between an EX-OR (9-1) of the signals i, q and an EX-OR (9-2) of the signals i', q') is used for a control voltage input to the VCO 2 via a loop filter 10.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a π / 4 shift QPSK.
The present invention relates to an improvement in miniaturization of a synchronous circuit used for synchronous detection of a (four-phase phase modulation) signal.

[0002]

2. Description of the Related Art A configuration conventionally used as a synchronizing circuit used for synchronous detection of a phase modulation signal such as BPSK, QPSK, 8PSK has (1) a received signal frequency multiplication method, (2) an inverse modulation method, Known are (3) re-modulation method and (4) Costas loop method. Of these, (1) is a means for multiplying the frequency of the received signal, (2) is means for modulating the reverse phase of the received signal, and (3) is means for modulating the phase of the local signal separately from the detection means. It is necessary and there is a problem in the circuit scale. The Costas loop of (4) is known to contribute to miniaturization because the multiplication processing of the received signal frequency of (1) is equivalently realized on a complex baseband signal using a part of the detection circuit. .

FIG. 1 shows a conventional configuration example of the Costas loop system in the case of QPSK. In the figure, IF is a received intermediate frequency signal. 101 is a 4 divider, and IF is 4
Distribute. A VCO (voltage controlled oscillator) 102 obtains an oscillation output having a frequency corresponding to a frequency control voltage input. Reference numeral 103 denotes a four-phase distributor, which distributes and outputs local signals of four-phase components of 0 °, 90 °, 45 °, and 135 ° from the output of the VCO 102. 104-1 to 104-
4 is a balanced modulator, which has a phase of 0 ° with IF,
Balanced modulation with local signals of 90 °, 45 °, and 135 ° is performed. 105-1 to 105-4 are low-pass filters (LP
F), and the phase of each local signal is 0 °, 90 °, 45
Baseband signal components I, Q, I ′ and Q ′ having the same phase as ° and 135 ° are extracted. 106-1 to 106-
A balanced modulator 3 performs balanced modulation of I and Q, I ′ and Q ′ and balanced modulation of these outputs to extract a carrier synchronization phase error signal. Reference numeral 107 denotes a loop filter, which removes harmonic components and noise components contained in the phase error signal and feeds them back to the frequency control voltage input of the VCO 102.

In the above structure, the balance flattening device 106-
1 to 106-3, the complex baseband signals I, Q,
The quadruple processing of the received signal frequency is equivalently realized on I ′ and Q ′.

[0005]

However, in the above-mentioned conventional configuration, the four distributor 101, the four-phase distributor 103 for VCO output, the total of seven balanced modulators and the total of four low-pass filters are installed. There is a limit to miniaturization and IC integration.

The above is the problem of the conventional synchronous circuit applied to QPSK, but the synchronous circuit applied to π / 4 shift QPSK requires further measures.

FIG. 2 is a signal space diagram on the I and Q coordinates of π / 4 shift QPSK. As shown, π
The / 4 shift QPSK is a signal space diagram in which the orthogonal reference coordinates of the QPSK are discretely rotated by π / 4 radian in one direction for each symbol, and the symbol changes are as shown by the bold line in the figure. .

That is, in the constellation (signal arrangement) of π / 4 shift QPSK, a set of four phase points (circle mark; an odd multiple of π / 4 radian) of ,,,,
A set of four phase points of “,” and “(● mark; an even multiple of π / 4 radian) alternates with alternate symbols. Therefore, the conventional Costas loop method for QPSK is π / 4 shift QP.
Not applicable to SK.

As a conventional configuration for solving this problem, in addition to an inverse modulation system, a remodulation system, etc., a system for multiplying the received signal frequency by 8 and a system for 8PSK, focusing on the fact that the constellation has 8 phases in total. A loop method or the like can be considered. However, both of them have a drawback that the circuit scale becomes extremely large.

An object of the present invention is to provide a π / 4 shift QPSK synchronization circuit which is suitable for downsizing and IC reduction by reducing the circuit scale which is a problem in the conventional circuit.

[0011]

Π / 4 shift Q of the present invention
The PSK synchronization circuit has a divider for dividing the received intermediate frequency signal into two, a VCO for generating a local signal having the same frequency as the received intermediate frequency signal, and an output of the VCO having a phase difference of 90 ° with each other. A 90 ° distributor for distributing signals, first and second balanced modulators for performing balanced flatness of one of the signals of the distributor and the other of the 90 ° distributor, and of the other signal, respectively, and the first and second First and second low-pass filters that extract the modulation components I and Q from the output of the second balanced modulator, and binary outputs of the outputs of the first and second low-pass filters, respectively. Comparing the output of the first and second comparators and the output of the first and second low-pass filters, and performing the magnitude comparison after reversing the polarity of one of the third, fourth Comparator and the first and First and second exclusive OR gates for obtaining an exclusive OR between outputs of the second comparator and between outputs of the third and fourth comparators, and the first and second exclusive OR gates, respectively. A third exclusive OR gate for obtaining an exclusive OR of the outputs of the OR gates, an exclusive logic of the output of the third exclusive OR gate, and the clock divided by ½ of the symbol rate Fourth to get the sum
Of the exclusive OR gate, a loop filter for smoothing the output of the fourth exclusive OR gate and feeding back to the frequency control voltage input of the VCO, and an output of the first and second low-pass filters. A change point detection circuit for extracting the timing of a symbol change from a motion, a bit rate clock phase-synchronized with the output of the change point detection circuit, a symbol rate clock and a symbol rate of 1 supplied to the fourth exclusive OR gate. And a reception timing synchronization circuit for generating a 1/2 frequency-divided clock.

[0012]

【Example】

(Structure) FIG. 3 is a structural example of a π / 4 shift QPSK synchronization circuit according to the present invention. In the figure, 1 is a divider for dividing the received intermediate frequency signal IF into 2 and 2 is a VCO (Voltage Controll) for generating a local signal having the same frequency as the IF.
ed Oscillator), 3 is the output of VCO2 90 ° to each other
It is a 90 ° distributor that distributes to two signals having a phase difference of. Balanced modulators 4-1 and 4-2 perform balanced modulation of each output of the distributor 1 and each output of the 90 ° distributor. 5-1 and 5-2 are balanced modulators 4-1 respectively.
And a low-pass filter (LPF) that extracts the modulation components I (in-phase component) and Q (quadrature component) from the outputs of 4-2. 6-1 and 6-2 respectively add the above I and Q to 2
It is a comparator for obtaining signals i and q whose values are shaped.
7-1 and 7-2 are I and the polarity inversion signal of Q above-
This is a comparator that outputs the magnitude comparison result with Q and the magnitude comparison result with I and Q at a binary logic level.
Reference numeral 8 is a polarity reversal device for obtaining the above-Q. 9-1,
9-2, 9-3 and 9-4 are exclusive OR (EX-O
R) gate, 9-1 is between the above i and q, 9-2
Is between the outputs of the comparators 7-1 and 7-2, 9-3 is between the outputs of the EX-OR gates 9-1 and 9-2, and 9-4 is E.
The output of the X-OR gate 9-3 and 1 / the symbol rate
The exclusive OR between the divided-by-two clock (1/2) f _s is output. Reference numeral 10 is a loop filter for removing harmonic components and noise components of the output of the EX-OR gate 9-4, and its output is fed back to the frequency control voltage input of the VCO 2. 11 is a change point detection circuit,
A binary signal indicating the timing of symbol change is output from the I and Q movements. The timing of symbol change can be extracted from the zero-cross point of I and Q, the maximum point of I ² + Q ² , and the like.
Reference numeral 12 is a reception timing synchronization circuit, which is a change point detection circuit 11
The bit rate clock 2f _s , the symbol rate clock f _s , and the symbol rate ½ divided clock (½) f _s are output in phase with the output of the above. The above function can be realized by a known PLL (Phaase Locked Loop) technique.

(Operation) Based on the configuration example of the π / 4 shift QPSK synchronous detection circuit of the present invention shown in FIG. 3, its detection operation and effect will be described in detail with reference to FIG.

4 (1), (2) and (3) show the logical polarities of the outputs of the EX-OR gates 9-1, 9-2 and 9-3 on the I and Q Lissajous planes, respectively. In the figure shown, the hatched portion has the logical polarity “1”.
In addition, the blank portion which is not applied corresponds to the logical polarity “0”. Also, the circle in the figure is the received symbol at the time of determination (the complex vector I + on the Lissajous plane of I and Q
jQ) indicates a possible region, and the circles on the circle are the four phase points (first quadrant), (second quadrant), as in FIG.
(3rd phenomenon) and (4th phenomenon) are represented, respectively.

First, since the logical polarity of the output of the EX-OR gate 9-1 is "0" when I and Q have the same polarity and "1" when they have different polarities, it is shown in FIG. 4 (1). like,
The first and third quadrants are "0" (blank), and the second and fourth quadrants are "1" (hatched). On the other hand, the output of the EX-OR gate 9-2 is "0" when (I-Q) and (I + Q) have the same polarity, and "1" when they have different polarities.
Therefore, as shown in (2) of FIG. 4, the straight line Q =
The left and right of the four areas partitioned by I and Q = -I are "0", and the top and bottom are "1". Therefore, the output of the EX-OR gate 9-3 is given by the exclusive OR condition of (1) and (2) of FIG.
The polarity classification is shown in (3).

Since the output of the EX-OR gate 9-4 is the exclusive OR of the output of the EX-OR gate 9-3 and (1/2) f _s , (1/2) f Corresponding to the polarities "0" and "1" of _s, the polarities are the same and opposite to the output of the EX-OR gate 9-3, respectively. Therefore,
When the output polarity of 9-4 is (1/2) f _s = “0”, it is as shown in FIG. 4 (3), but when it is “1”, it is as shown in FIG.
As shown in FIG. 4 (4), the division is obtained by inverting FIG. 4 (3), and (1/2) f _s is a signal which alternates between “0” and “1” in alternate symbols. (3)
It can be seen that the sections of (4) and (4) are alternated with alternate symbols.

The control voltage of the VCO 2 is originally applied to the control of frequency increase / decrease, and this frequency increase / decrease is to the left of the complex vector I + jQ on the I and Q Lissajous plane, or Since it is expressed as right rotation, here, I + jQ is rotated left when the logic polarity of the output of the EX-OR gate 9-4 is "0", and conversely, it is set right rotation when it is "1". I will keep it. Therefore,
The rotation directions on the respective regions shown in (3) and (4) of FIG. 4 are as shown by arrows. From the figure, the four phase points of (3) ,,, and the four phase points of (4) ',',
Both of the 'and' are located at the positions where the left rotation and right rotation arrows face each other, and it can be seen that the two sets of these four phase points alternately become stable retention points with the alternate symbols in the closed loop configuration of FIG. In the configuration of the present invention, since the synchronous phase error of I + jQ from the four phase points is binarized, the magnitude of the error amount cannot be detected, but the rotation direction indicated by the arrow is always given, A negative feedback loop in which the two four phase points of the π / 4 shift QPSK shown in FIG. 2 are alternately set as stable points is formed, and stable synchronous operation is obtained without causing any essential synchronization problems. Is possible.

FIG. 5 shows measured values of bit error rate characteristics when the π / 4 shift QPSK synchronization circuit according to the present invention is used in a demodulator. The vertical axis of the figure is the bit error rate, and the horizontal axis is 1.
It is the ratio (energy contrast ratio) between the received energy E _b per bit and the noise spectrum density N ₀ . The bit rate in this actual measurement example is 15 Mbps, and the modulation waveform shaping uses a 100% Nyquist roll-off filter on the transmission side (roll-off factor-α = 1.0). As shown in the figure, the bit error rate of the measured value (thick line) is 1
It can be seen that the deterioration with respect to the theoretical value (thin line) at the point of 0 ⁻⁴ is about 1 dB or more, and good characteristics are obtained.

[0019]

As described above in detail, according to the present invention, two balanced modulators and two low-pass filters are used, and the VCO outputs are 0 ° and 90 °. Two-phase distribution is sufficient, and it can be realized on an extremely small scale as compared with the conventional method, so that the practical effect is large.

[Brief description of drawings]

FIG. 1 is a configuration example diagram of a conventional Costas loop system for QPSK.

FIG. 2 is a signal space diagram of π / 4 shift QPSK.

FIG. 3 is a configuration example diagram of a π / 4 shift QPSK synchronization circuit according to the present invention.

FIG. 4 shows EX-OR gates 9-1, 9-2, 9-4 ((1/2) f _s = on the Lissajous plane of I and Q).
"0"), showing the logical polarity of _{9-4 ((1/2) f s =} "1").

FIG. 5 is an actual measurement example diagram of bit error rate characteristics when the π / 4 shift QPSK synchronization circuit according to the present invention is used in a demodulator.

[Explanation of symbols]

 1 divider 2 VCO 3 90 degree divider 4-1 and 4-2 balanced modulator 5-1 and 5-2 LPF 6-1, 6-2, 7-1, 7-2 comparator 8 polarity inverter 9- 1, 9-2, 9-3, 9-4 EX-OR gate 10 Loop filter 11 Change point detection circuit 12 Reception timing synchronization circuit 101 4 distributor 102 VCO 103 4 phase distributor 104-1 to 104-4 Balanced modulation 105-1 to 105-4 Low-pass filter 106-1 to 106-3 Balanced modulator 107 Loop filter

Claims (1)

[Claims] 1. A divider that divides a received intermediate frequency signal into two, a VCO that generates a local signal having the same frequency as the received intermediate frequency signal, and an output of the VCO that has a phase difference of 90 ° from each other. A 90 ° distributor for distributing signals, first and second balanced modulators for performing balanced flat adjustment between signals of one of the distributor and the 90 ° distributor, and of the other signal, respectively, and First and second low-pass filters that extract modulation components I and Q from the output of the second balanced modulator, and binary outputs of the outputs of the first and second low-pass filters, respectively. The first and second comparators, the magnitude comparison of the outputs of the first and second low-pass filters, and the magnitude comparison after inverting one of the polarities, the third and fourth The comparator, and the first and First and second exclusive-OR gates for obtaining an exclusive-OR between outputs of the second comparator and between outputs of the third and fourth comparators, and the first and second exclusive-OR gates, respectively. A third exclusive OR gate for obtaining an exclusive OR of the outputs of the OR gates, an exclusive logic of the output of the third exclusive OR gate and the clock divided by ½ of the symbol rate A fourth exclusive OR gate for obtaining a sum, and the VCO for smoothing the output of the fourth exclusive OR gate
A loop filter which feeds back to the frequency control voltage input, a change point detection circuit for extracting the timing of symbol change from the movements of the outputs of the first and second low pass filters, and an output of the change point detection circuit. And a reception timing synchronization circuit for generating a phase-synchronized bit rate clock, a symbol rate clock, and a symbol rate divided by 1/2 clock supplied to the fourth exclusive OR gate. π / 4 shift QPSK synchronization circuit.