JPH07273824A - Qpsk synchronizing circuit - Google Patents
Qpsk synchronizing circuitInfo
- Publication number
- JPH07273824A JPH07273824A JP6081120A JP8112094A JPH07273824A JP H07273824 A JPH07273824 A JP H07273824A JP 6081120 A JP6081120 A JP 6081120A JP 8112094 A JP8112094 A JP 8112094A JP H07273824 A JPH07273824 A JP H07273824A
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- Prior art keywords
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- exclusive
- output
- distributor
- Prior art date
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- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＱＰＳＫ（４相位相変
調）信号の同期検波に供せられる同期回路の小形化改良
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to miniaturization and improvement of a synchronous circuit used for synchronous detection of a QPSK (four phase modulation) signal.
【０００２】[0002]
【従来の技術】ＢＰＳＫ，ＱＰＳＫ，８ＰＳＫ等の位相
変調信号の同期検波に供せられる同期回路として従来用
いられている構成に、（１） 受信信号周波数の逓倍方
式、（２）逆変調方式、（３）再変調方式、（４）コス
タスループ方式等が知られている。このうち、（１）は
受信信号周波数の逓倍手段を、（２）は受信信号の逆位
相変調手段を、また（３）はローカル信号の位相変調手
段を、それぞれ検波手段とは別個に設備する必要があ
り、回路規模に問題がある。（４）のコスタスループは
（１）の受信信号周波数の逓倍処理を検波回路の一部を
利用してベースバンド信号上で等価的に実現するので小
形化に寄与することが知られている。2. Description of the Related Art A configuration conventionally used as a synchronizing circuit used for synchronous detection of a phase modulation signal such as BPSK, QPSK, 8PSK has (1) a received signal frequency multiplication method, (2) an inverse modulation method, Known are (3) re-modulation method and (4) Costas loop method. Of these, (1) is a means for multiplying the frequency of the received signal, (2) is means for modulating the reverse phase of the received signal, and (3) is means for modulating the phase of the local signal separately from the detection means. It is necessary and there is a problem in the circuit scale. The Costas loop of (4) is known to contribute to miniaturization because the multiplication processing of the received signal frequency of (1) is equivalently realized on a baseband signal by using a part of the detection circuit.
【０００３】図１はＱＰＳＫの場合のコスタスループ方
式の従来の一構成例を示す。図において、ＩＦは受信中
間周波信号を示す。１０１は４分配器であり、ＩＦを４
分配する。１０２はＶＣＯ（電圧制御発振器）であっ
て、周波数制御電圧入力に応じた周波数の発振出力を得
る。１０３は４位相分配器であり、ＶＣＯ１０２の出力
から各々０°，９０°，４５°，１３５°の４位相成分
のローカル信号を分配出力する。１０４−１〜１０４−
４は平衡変調器であり、それぞれ４分配されたＩＦと位
相が０°，９０°，４５°，１３５°の各ローカル信号
との平衡平調を行う。１０５−１〜１０５−４は低域ろ
波器（ＬＰＦ）であり、各ローカル信号の位相０°，９
０°，４５°，１３５°と同相のベースバンド信号成分
Ｉ，Ｑ，Ｉ’，Ｑ’をそれぞれ抽出する。１０６−１〜
１０６−３は平衡変調器であり、ＩとＱ，Ｉ’とＱ’の
平衡変調とこれらの出力同士の平衡変調を行いキャリア
同期の位相誤差信号を抽出する。１０７はループフィル
タであり、上記位相誤差信号に含まれている高調波成分
および雑音成分を除去し、ＶＣＯ１０２の周波数制御電
圧入力にフィードバックする。以上の構成において、平
衡平調器１０６−１〜１０６−３により、複素ベースバ
ンド信号Ｉ，Ｑ，Ｉ’，Ｑ’上で受信信号周波数の４逓
倍処理が等価的に実現されている。FIG. 1 shows a conventional configuration example of the Costas loop system in the case of QPSK. In the figure, IF indicates a received intermediate frequency signal. 101 is a 4 divider, and IF is 4
Distribute. A VCO (voltage controlled oscillator) 102 obtains an oscillation output having a frequency corresponding to a frequency control voltage input. Reference numeral 103 denotes a four-phase distributor, which distributes and outputs local signals of four-phase components of 0 °, 90 °, 45 °, and 135 ° from the output of the VCO 102. 104-1 to 104-
Reference numeral 4 denotes a balanced modulator, which performs balanced flat adjustment between the four-divided IF and each local signal having a phase of 0 °, 90 °, 45 °, 135 °. Reference numerals 105-1 to 105-4 are low-pass filters (LPFs), which have the phases of 0 ° and 9 ° of each local signal.
Baseband signal components I, Q, I ′ and Q ′ in phase with 0 °, 45 ° and 135 ° are extracted, respectively. 106-1 to
A balanced modulator 106-3 performs balanced modulation of I and Q, I ′ and Q ′ and balanced modulation of these outputs to extract a carrier synchronization phase error signal. Reference numeral 107 denotes a loop filter, which removes harmonic components and noise components contained in the phase error signal and feeds them back to the frequency control voltage input of the VCO 102. In the above configuration, the balanced flatteners 106-1 to 106-3 equivalently realize the quadruple processing of the received signal frequency on the complex baseband signals I, Q, I ′ and Q ′.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記従
来の構成では４分配器１０１，ＶＣＯ出力の４位相分配
器１０３や合計７個の平衡変調器および合計４個の低域
ろ波器等を設備する必要があり、小形化，ＩＣ化に限界
がある。However, in the above-mentioned conventional configuration, the four distributor 101, the four-phase distributor 103 for VCO output, the total of seven balanced modulators and the total of four low-pass filters are installed. There is a limit to miniaturization and IC integration.
【０００５】本発明の目的は、前記従来の回路において
問題となる回路規模を削減し、小形化，ＩＣ化に適する
ＱＰＳＫ同期回路を提供することにある。It is an object of the present invention to provide a QPSK synchronization circuit which is suitable for miniaturization and IC reduction, while reducing the circuit scale which is a problem in the conventional circuit.
【０００６】[0006]
【課題を解決するための手段】本発明のＱＰＳＫ同期回
路は、受信中間周波信号を２分配する分配器と、前記受
信中間周波信号と同一の周波数を有するローカル信号を
発生するＶＣＯと、該ＶＣＯの出力を互いに９０°の位
相差を有する２信号に分配する９０°分配器と、前記分
配器および９０°分配器の一方の信号同士および他方の
信号同士の平衡変調をそれぞれ行う第１および第２の平
衡変調器と、該第１および第２の平衡変調器の出力から
変調成分ＩおよびＱをそれぞれ抽出する第１および第２
の低域ろ波器と、該第１および第２の低域ろ波器の出力
をそれぞれ２値整形する第１および第２のコンパレータ
と、前記第１および第２の低域ろ波器の出力の大小比
較、およびいずれか一方の極性を反転させたのちの大小
比較をそれぞれ行う第３，第４のコンパレータと、前記
第１および第２のコンパレータの出力間、および前記第
３および第４のコンパレータの出力間の排他的論理和を
それぞれ得る第１および第２の排他的論理和ゲートと、
該第１および第２の排他的論理和ゲートの出力同士の排
他的論理和を得る第３の排他的論理和ゲートと、該第３
の排他的論理和ゲートの出力を平滑化し前記ＶＣＯの周
波数制御電圧入力に帰還するループフィルタとで構成さ
れたことを特徴とするものである。SUMMARY OF THE INVENTION A QPSK synchronization circuit of the present invention comprises a divider for dividing a received intermediate frequency signal into two, a VCO for generating a local signal having the same frequency as the received intermediate frequency signal, and the VCO. 90 ° distributor for distributing the outputs of the two signals into two signals having a phase difference of 90 ° from each other, and first and first for performing balanced modulation of one signal of the distributor and one signal of the other of the 90 ° distributor, respectively. 2 balanced modulators, and 1st and 2nd respectively extracting modulation components I and Q from the outputs of said 1st and 2nd balanced modulators, respectively.
Of the first and second low-pass filters, and first and second comparators for binarizing the outputs of the first and second low-pass filters, respectively. The third and fourth comparators for respectively performing the magnitude comparison of the outputs and the magnitude comparison after inverting one of the polarities, the outputs of the first and second comparators, and the third and the fourth comparators. First and second exclusive-OR gates for respectively obtaining an exclusive-OR between the outputs of the comparators,
A third exclusive-OR gate for obtaining an exclusive-OR between outputs of the first and second exclusive-OR gates;
And a loop filter for smoothing the output of the exclusive-OR gate of (1) and feeding back to the input of the frequency control voltage of the VCO.
【０００７】[0007]
（構成）図２は本発明によるＱＰＳＫ同期回路の一構成
例図である。図中、１は受信中間周波信号ＩＦを２分配
する分配器、２はＩＦと同一の周波数を有するローカル
信号を発生するＶＣＯ（Voltage Controlled Oscillato
r ）、３はＶＣＯ２の出力を互いに９０°の位相差を有
する２信号に分配する９０°分配器である。４−１，４
−２は平衡変調器で、分配器１の各々の出力と９０°分
配器３の各々の出力との平衡変調を行う。５−１，５−
２は、それぞれ平衡変調器４−１および４−２の出力か
ら変調成分Ｉ（同相成分）およびＱ（直交成分）を抽出
する低域ろ波器（ＬＰＦ）である。６−１および６−２
はそれぞれ上記ＩおよびＱを２値整形して信号ｉおよび
ｑを得るコンパレータである。７−１および７−２は、
Ｉと、上記Ｑの極性反転信号−Ｑとの大小比較結果、お
よびＩとＱの大小比較結果をそれぞれ２値論理レベルで
出力するコンパレータである。８は上記−Ｑを得るため
の極性反転器である。９−１，９−２および９−３は排
他的論理和（ＥＸ−ＯＲ）ゲートであって、９−１は上
記ｉとｑの間、９−２はコンパレータ７−１と７−２の
出力間、さらに９−３はＥＸ−ＯＲゲート９−１と９−
２の出力間の排他的論理和をそれぞれ出力する。１０は
ＥＸ−ＯＲゲート９−３の出力から高調波成分や雑音成
分を除去するループフィルタで、その出力は上記ＶＣＯ
２の周波数制御電圧入力にフィードバックされる。(Structure) FIG. 2 is a structural example of a QPSK synchronization circuit according to the present invention. In the figure, 1 is a divider for dividing the received intermediate frequency signal IF into 2 and 2 is a VCO (Voltage Controlled Oscillato) for generating a local signal having the same frequency as the IF.
r) and 3 are 90 ° dividers for dividing the output of the VCO 2 into two signals having a phase difference of 90 °. 4-1 and 4
Reference numeral -2 is a balanced modulator, which performs balanced modulation of each output of the distributor 1 and each output of the 90 ° distributor 3. 5-1 and 5-
Reference numeral 2 is a low-pass filter (LPF) that extracts the modulation components I (in-phase component) and Q (quadrature component) from the outputs of the balanced modulators 4-1 and 4-2, respectively. 6-1 and 6-2
Is a comparator for binary-shaping I and Q to obtain signals i and q. 7-1 and 7-2 are
It is a comparator that outputs the magnitude comparison result of I and the polarity inversion signal -Q of Q and the magnitude comparison result of I and Q at a binary logic level. Reference numeral 8 is a polarity reversal device for obtaining the above-Q. 9-1, 9-2 and 9-3 are exclusive OR (EX-OR) gates, 9-1 is between the above i and q, 9-2 is the comparator 7-1 and 7-2. Between outputs, further 9-3 is EX-OR gates 9-1 and 9-.
The exclusive OR between the two outputs is output. Reference numeral 10 denotes a loop filter for removing harmonic components and noise components from the output of the EX-OR gate 9-3, the output of which is the VCO.
2 is fed back to the frequency control voltage input.
【０００８】（作用）図２に示した本発明のＱＰＳＫ同
期検波回路の構成例に基づき、その検波動作と効果を図
３によって詳しく説明する。(Operation) Based on the configuration example of the QPSK synchronous detection circuit of the present invention shown in FIG. 2, its detection operation and effect will be described in detail with reference to FIG.
【０００９】図３の（１），（２）および（３）は、そ
れぞれＩとＱのリサージュ平面上でのＥＸ−ＯＲゲート
９−１，９−２および９−３の出力の論理極性を示した
図であって、ハッチングを施した部分は論理極性“１”
に、また施していない空白の部分は論理極性“０”に該
当している。また、図中の円は判定時点における受信シ
ンボル（ＩとＱのリサージュ平面上の複素ベクトルＩ＋
ｊＱ）の存在しうる領域を示しており、円上の〇印はＱ
ＰＳＫ信号の４位相点（第１象限），（第２象
限），（第３現象），（第４現象）をそれぞれ表し
ている。3 (1), (2) and (3) show the logical polarities of the outputs of the EX-OR gates 9-1, 9-2 and 9-3 on the I and Q Lissajous planes, respectively. In the figure shown, the hatched portion has the logical polarity “1”.
In addition, the blank portion which is not applied corresponds to the logical polarity “0”. Also, the circle in the figure is the received symbol at the time of determination (the complex vector I + on the Lissajous plane of I and Q
jQ) can exist, and the circle on the circle is Q.
The four phase points (first quadrant), (second quadrant), (third phenomenon), and (fourth phenomenon) of the PSK signal are shown, respectively.
【００１０】まず、ＥＸ−ＯＲゲート９−１の出力の論
理極性はＩとＱが同極性のとき“０”となり異極性のと
き“１”となるので、図３の（１）に図示したように、
第１象限と第３象限が“０”（空白）となり、第２
象限と第４象限が“１”（ハッチング）となる。一
方、ＥＸ−ＯＲゲート９−２の出力は、（Ｉ−Ｑ）と
（Ｉ＋Ｑ）が同極性のとき“０”、異極性のとき“１”
となるから、図３の（２）に図示したように直線Ｑ＝
Ｉ，Ｑ＝−Ｉで仕切った４領域の左右が“０”、上下が
“１”となる。従って、ＥＸ−ＯＲゲート９−３の出力
は、上記（１）と（２）の排他的論理和条件により、
（３）に図示した極性区分となる。First, since the logical polarity of the output of the EX-OR gate 9-1 is "0" when I and Q have the same polarity and "1" when they have different polarities, it is shown in FIG. 3 (1). like,
The first and third quadrants are "0" (blank), and the second
The quadrant and the fourth quadrant are "1" (hatched). On the other hand, the output of the EX-OR gate 9-2 is "0" when (I-Q) and (I + Q) have the same polarity, and "1" when they have different polarities.
Therefore, as shown in (2) of FIG. 3, the straight line Q =
The left and right of the four areas partitioned by I and Q = -I are "0", and the top and bottom are "1". Therefore, the output of the EX-OR gate 9-3 is given by the exclusive OR condition of (1) and (2) above.
The polarity classification is shown in (3).
【００１１】さて、ＶＣＯ２の制御電圧は、元来、周波
数の増大，減少の制御に適用されるものであり、この周
波数の増減は上記ＩとＱのリサージュ面上の複素ベクト
ルＩ＋ｊＱの左、もしくは右回転となって表されるの
で、ここでは、ＥＸ−ＯＲゲート９−３の出力の論理極
性が“０”のときＩ＋ｊＱが左回転、逆に“１”のとき
右回転するように設定しておくものとする。このとき、
図３の（３）に示した各領域上の回転方向は矢印のよう
になる。同図より、ＱＰＳＫの４位相点，，，
はいずれも矢印が向き合う位置にあり、これら４位相点
が図２の閉ループ構成において安定な滞留点であること
がわかる。なお、本発明の構成では、上記４位相点から
のＩ＋ｊＱの同期位相誤差は２値化されているため、誤
差量の大小は検出できないが、上述の矢印が示す回転方
向は常に与えられるので、ＱＰＳＫの４位相点を安定点
とする負帰還ループが形成されて、同期上の本質的な問
題を全く生じることなく安定した同期動作を行う。The control voltage of the VCO 2 is originally applied to the control of frequency increase / decrease, and this frequency increase / decrease is to the left of the complex vector I + jQ on the I and Q Lissajous plane, or Since it is expressed as right rotation, here, I + jQ is set to rotate left when the logical polarity of the output of the EX-OR gate 9-3 is "0", and conversely, it is set to rotate right when it is "1". I will keep it. At this time,
The rotation direction on each area shown in (3) of FIG. 3 is as shown by an arrow. From the figure, the four phase points of QPSK ,,,
In each case, the arrows point to each other, and it can be seen that these four phase points are stable retention points in the closed loop configuration of FIG. In the configuration of the present invention, since the synchronous phase error of I + jQ from the four phase points is binarized, the magnitude of the error amount cannot be detected, but the rotation direction indicated by the arrow is always given, A negative feedback loop whose stable points are the four phase points of QPSK is formed, and stable synchronous operation is performed without causing any essential synchronization problems.
【００１２】図４は、本発明の構成によるＱＰＳＫ同期
回路を復調器に用いた時のビット誤り率特性の実施例を
示す。図の縦軸はビット誤り率、横軸は１ビット当りの
受信エネルギＥb と雑音スペクトラム密度Ｎ0 との比
（エネルギコントラスト比）である。本実測例のビット
レートは１５Ｍｂｐｓであり、変調波形シェーピングは
送信側１００％ナイキストロールオフフィルタ（ロール
オフファクタ−α＝１．０）を使用している。図示した
ように、実測値（太線）のビット誤り率１０-4の点にお
ける理論値（細線）に対する劣化はおよそ１ｄＢ強であ
り、良好な特性が得られていることがわかる。FIG. 4 shows an embodiment of bit error rate characteristics when the QPSK synchronization circuit according to the present invention is used in a demodulator. The vertical axis of the figure is the bit error rate, and the horizontal axis is the ratio (energy contrast ratio) between the received energy E b and the noise spectrum density N 0 per bit. The bit rate in this actual measurement example is 15 Mbps, and the modulation waveform shaping uses a 100% Nyquist roll-off filter on the transmission side (roll-off factor-α = 1.0). As shown in the figure, the deterioration of the measured value (thick line) with respect to the theoretical value (thin line) at the bit error rate of 10 −4 is about 1 dB or more, which shows that good characteristics are obtained.
【００１３】[0013]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、使用する平衡変調器と低域ろ波器の個数が各々
２個ずつであり、ＶＣＯ出力も０°と９０°の２相分配
でよく、従来に比べ極めて小規模で実現できるため、実
用上の効果は大きい。As described above in detail, according to the present invention, two balanced modulators and two low-pass filters are used, and the VCO outputs are 0 ° and 90 °. Two-phase distribution is sufficient, and it can be realized on an extremely small scale as compared with the conventional method, so that the practical effect is large.
【図１】従来のＱＰＳＫ用コスタスループ方式の構成例
図である。FIG. 1 is a configuration example diagram of a conventional Costas loop system for QPSK.
【図２】本発明によるＱＰＳＫ同期回路の一構成例図で
ある。FIG. 2 is a diagram showing a configuration example of a QPSK synchronization circuit according to the present invention.
【図３】本発明におけるＩとＱのリサージュ平面上での
ＥＸ−ＯＲゲート９−１，９−２，９−３の論理極性を
示す図である。FIG. 3 is a diagram showing logical polarities of EX-OR gates 9-1, 9-2, 9-3 on the I and Q Lissajous planes according to the present invention.
【図４】本発明によるＱＰＳＫ同期回路を復調器に使用
したときのビット誤り率特性の実測例図である。FIG. 4 is a measurement example diagram of bit error rate characteristics when the QPSK synchronization circuit according to the present invention is used in a demodulator.
１ 分配器 ２ ＶＣＯ ３ ９０°分配器 ４−１，４−２ 平衡変調器 ５−１，５−２ ＬＰＦ ６−１，６−２，７−１，７−２ コンパレータ ８ 極性反転器 ９−１，９−２，９−３ ＥＸ−ＯＲゲート １０ ループフィルタ １０１ ４分配器 １０２ ＶＣＯ １０３ ４位相分配器 １０４−１〜１０４−４ 平衡変調器 １０５−１〜１０５−４ 低域ろ波器 １０６−１〜１０６−３ 平衡変調器 １０７ ループフィルタ 1 divider 2 VCO 3 90 degree divider 4-1 and 4-2 balanced modulator 5-1 and 5-2 LPF 6-1, 6-2, 7-1, 7-2 comparator 8 polarity inverter 9- 1, 9-2, 9-3 EX-OR gate 10 loop filter 101 4 distributor 102 VCO 103 4 phase distributor 104-1 to 104-4 balanced modulator 105-1 to 105-4 low-pass filter 106 -1 to 106-3 Balanced modulator 107 Loop filter
Claims (1)
と、 前記受信中間周波信号と同一の周波数を有するローカル
信号を発生するＶＣＯと、 該ＶＣＯの出力を互いに９０°の位相差を有する２信号
に分配する９０°分配器と、 前記分配器および９０°分配器の一方の信号同士および
他方の信号同士の平衡変調をそれぞれ行う第１および第
２の平衡変調器と、 該第１および第２の平衡変調器の出力から変調成分Ｉお
よびＱをそれぞれ抽出する第１および第２の低域ろ波器
と、 該第１および第２の低域ろ波器の出力をそれぞれ２値整
形する第１および第２のコンパレータと、 前記第１および第２の低域ろ波器の出力の大小比較、お
よびいずれか一方の極性を反転させたのちの大小比較を
それぞれ行う第３，第４のコンパレータと、 前記第１および第２のコンパレータの出力間、および前
記第３および第４のコンパレータの出力間の排他的論理
和をそれぞれ得る第１および第２の排他的論理和ゲート
と、 該第１および第２の排他的論理和ゲートの出力同士の排
他的論理和を得る第３の排他的論理和ゲートと、 該第３の排他的論理和ゲートの出力を平滑化し前記ＶＣ
Ｏの周波数制御電圧入力に帰還するループフィルタとで
構成されたことを特徴とするＱＰＳＫ同期回路。1. A divider that divides a received intermediate frequency signal into two, a VCO that generates a local signal having the same frequency as the received intermediate frequency signal, and an output of the VCO that has a phase difference of 90 ° from each other. A 90 ° distributor for distributing signals, first and second balanced modulators for performing balanced modulation of one signal of the distributor and one signal of the other of the 90 ° distributor, respectively, and the first and second First and second low-pass filters for extracting the modulation components I and Q from the outputs of the two balanced modulators, and binary outputs of the outputs of the first and second low-pass filters, respectively. Comparing the magnitudes of the outputs of the first and second low-pass filters with the first and second comparators, and the magnitude comparison after inverting the polarity of one of the third and fourth comparators, respectively. A comparator, the first and First and second exclusive-OR gates for obtaining an exclusive-OR between outputs of the second comparator and between outputs of the third and fourth comparators, and the first and second exclusive-OR gates, respectively. A third exclusive OR gate for obtaining an exclusive OR of the outputs of the OR gates, and a smoothing output of the third exclusive OR gate
A QPSK synchronous circuit, comprising a loop filter which feeds back to an O frequency control voltage input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6081120A JPH07273824A (en) | 1994-03-29 | 1994-03-29 | Qpsk synchronizing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6081120A JPH07273824A (en) | 1994-03-29 | 1994-03-29 | Qpsk synchronizing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07273824A true JPH07273824A (en) | 1995-10-20 |
Family
ID=13737528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6081120A Pending JPH07273824A (en) | 1994-03-29 | 1994-03-29 | Qpsk synchronizing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07273824A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009071833A (en) * | 2007-09-14 | 2009-04-02 | Fujitsu Ltd | Phase imbalance observation apparatus, amplitude imbalance observation apparatus, and device using them |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50159660A (en) * | 1974-06-13 | 1975-12-24 |
-
1994
- 1994-03-29 JP JP6081120A patent/JPH07273824A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50159660A (en) * | 1974-06-13 | 1975-12-24 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009071833A (en) * | 2007-09-14 | 2009-04-02 | Fujitsu Ltd | Phase imbalance observation apparatus, amplitude imbalance observation apparatus, and device using them |
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